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gardenia/loader
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hydrogenium2020 ce26824ed9 feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 
Here is the detail:
1. It has 2Ranks and 8bit*8.
2. There are some differences between H5TC4G63AFR-RDA and H5TC4G63AFR-PBA, and the parameters are not universal. If mixed use, it may lead to unstable data in memory writing (for example, data loss during writing).
2024-02-11 14:49:57 +08:00
..
bootrom.h First commit. 2024-01-14 16:20:28 +08:00
clock_lp0.h feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
clock.c Feat:Clock:Init! 2024-01-31 16:40:19 +08:00
clock.h feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
emc.h feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
fuse.c First commit. 2024-01-14 16:20:28 +08:00
fuse.h First commit. 2024-01-14 16:20:28 +08:00
gpio.c refactor:Clean up all code of clocks and registers. 2024-01-21 16:39:28 +08:00
gpio.h First commit. 2024-01-14 16:20:28 +08:00
heap.c feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
heap.h feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
i2c.h First commit. 2024-01-14 16:20:28 +08:00
io.c feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
io.h feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
link.ld First commit. 2024-01-14 16:20:28 +08:00
main.c Feat:MC,EMC:(WIP)Try to init SDRAM 2024-01-31 16:44:10 +08:00
mc.c feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
mc.h feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
memory_map.h feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
pinmux.c Feat:Try to bring UART(Not Tested) 2024-01-31 16:41:45 +08:00
pinmux.h feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
pmc_lp0.h feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
pmc.h Feat:Clock:Init! 2024-01-31 16:40:19 +08:00
power.h refactor:Clean up all code of clocks and registers. 2024-01-21 16:39:28 +08:00
sdram_config_h5tc4g63afr-rda-792mhz.inl feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
sdram_lp0.c feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
sdram_lp0.h feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
sdram.c feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
sdram.h feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
se.h refactor:Clean up all code of clocks and registers. 2024-01-21 16:39:28 +08:00
stack.S Feat:MC,EMC:(WIP)Try to init SDRAM 2024-01-31 16:44:10 +08:00
t124.h feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
timer.c First commit. 2024-01-14 16:20:28 +08:00
timer.h First commit. 2024-01-14 16:20:28 +08:00
types.h feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! 2024-02-11 14:49:57 +08:00
uart.c Feat:Try to bring UART(Not Tested) 2024-01-31 16:41:45 +08:00
uart.h Feat:Try to bring UART(Not Tested) 2024-01-31 16:41:45 +08:00
usb.c First commit. 2024-01-14 16:20:28 +08:00
usb.h First commit. 2024-01-14 16:20:28 +08:00
util.c Feat:Clock:Init! 2024-01-31 16:40:19 +08:00
util.h Feat:Clock:Init! 2024-01-31 16:40:19 +08:00