Commit Graph

6 Commits

Author SHA1 Message Date
hydrogenium2020
ce26824ed9 feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz!
Here is the detail:
1. It has 2Ranks and 8bit*8.
2. There are some differences between H5TC4G63AFR-RDA and H5TC4G63AFR-PBA, and the parameters are not universal. If mixed use, it may lead to unstable data in memory writing (for example, data loss during writing).
2024-02-11 14:49:57 +08:00
hydrogenium2020
0e2ba99d22 Feat:MC,EMC:(WIP)Try to init SDRAM 2024-01-31 16:44:10 +08:00
hydrogenium2020
621ec31ea6 Feat:Try to bring UART(Not Tested)
Because my board didn't have any UART port.
2024-01-31 16:41:45 +08:00
hydrogenium2020
d4a5b5f87f Feat:Clock:Init!
OSC freq,PLLC,PLLX,PLLU,PLLP,UART clock bring up
2024-01-31 16:40:19 +08:00
hydrogenium2020
b5d514cfac refactor:Clean up all code of clocks and registers.
We need to rewrite the code from coreboot or uboot's porting for Tegra T124.Instead of simply learning the init process from hekate.(Many heakte codes are only in Tegra T210)
2024-01-21 16:39:28 +08:00
hydrogenium2020
a84c7a7f9d First commit. 2024-01-14 16:20:28 +08:00