EljakimHerrewijnen/gardenia
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  • c8e1094f1a added ndk for building t124 Eljakim Herrewijnen 2024-05-17 14:59:52 +0200
  • 277ffc3f28 feat:Update README.md hydrogenium2020 2024-02-11 15:05:26 +0800
  • 4a9dbdaeda Fix: Correct the copyright and avoid repeated inclusion of header files. hydrogenium2020 2024-02-11 14:51:13 +0800
  • ce26824ed9 feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz! Here is the detail: 1. It has 2Ranks and 8bit*8. 2. There are some differences between H5TC4G63AFR-RDA and H5TC4G63AFR-PBA, and the parameters are not universal. If mixed use, it may lead to unstable data in memory writing (for example, data loss during writing). hydrogenium2020 2024-02-11 14:49:57 +0800
  • f808633517 Fix:Update Makefile and README.md hydrogenium2020 2024-01-31 16:45:11 +0800
  • 0e2ba99d22 Feat:MC,EMC:(WIP)Try to init SDRAM hydrogenium2020 2024-01-31 16:44:10 +0800
  • 621ec31ea6 Feat:Try to bring UART(Not Tested) Because my board didn't have any UART port. hydrogenium2020 2024-01-31 16:41:45 +0800
  • d4a5b5f87f Feat:Clock:Init! OSC freq,PLLC,PLLX,PLLU,PLLP,UART clock bring up hydrogenium2020 2024-01-31 16:40:19 +0800
  • b5d514cfac refactor:Clean up all code of clocks and registers. We need to rewrite the code from coreboot or uboot's porting for Tegra T124.Instead of simply learning the init process from hekate.(Many heakte codes are only in Tegra T210) hydrogenium2020 2024-01-21 16:39:28 +0800
  • a84c7a7f9d First commit. hydrogenium2020 2024-01-14 16:20:28 +0800
  • 267f02c2f6 [HACK] Support raw nand dump Kostas Missos 2018-05-01 15:28:48 +0300
  • 8365426fc3 So it has come to this. nwert 2018-05-01 17:15:48 +1200
  • 6181b39f14 License. nwert 2018-03-27 12:04:16 +1300
  • fb1ebd9a06 Fix uart for opt, actually use params. nwert 2018-03-16 10:14:09 +1300
  • 3077c47c39
         Add readme. nwert 2018-03-15 12:44:43 +1300
  • 332e5921aa Remove superfluous files. nwert 2018-03-15 12:42:06 +1300
  • 10b4b7d1cb Add hardware buttons, cpu booting, tsec booting. nwert 2018-03-15 12:26:19 +1300
  • 6f6683e05b Initial commit. nwert 2018-03-07 14:11:46 +1300