hydrogenium2020
4a9dbdaeda
Fix: Correct the copyright and avoid repeated inclusion of header files.
2024-02-11 14:51:13 +08:00
hydrogenium2020
ce26824ed9
feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz!
...
Here is the detail:
1. It has 2Ranks and 8bit*8.
2. There are some differences between H5TC4G63AFR-RDA and H5TC4G63AFR-PBA, and the parameters are not universal. If mixed use, it may lead to unstable data in memory writing (for example, data loss during writing).
2024-02-11 14:49:57 +08:00
hydrogenium2020
f808633517
Fix:Update Makefile and README.md
2024-01-31 16:45:11 +08:00
hydrogenium2020
0e2ba99d22
Feat:MC,EMC:(WIP)Try to init SDRAM
2024-01-31 16:44:10 +08:00
hydrogenium2020
621ec31ea6
Feat:Try to bring UART(Not Tested)
...
Because my board didn't have any UART port.
2024-01-31 16:41:45 +08:00
hydrogenium2020
d4a5b5f87f
Feat:Clock:Init!
...
OSC freq,PLLC,PLLX,PLLU,PLLP,UART clock bring up
2024-01-31 16:40:19 +08:00
hydrogenium2020
b5d514cfac
refactor:Clean up all code of clocks and registers.
...
We need to rewrite the code from coreboot or uboot's porting for Tegra T124.Instead of simply learning the init process from hekate.(Many heakte codes are only in Tegra T210)
2024-01-21 16:39:28 +08:00
hydrogenium2020
a84c7a7f9d
First commit.
2024-01-14 16:20:28 +08:00
Kostas Missos
267f02c2f6
[HACK] Support raw nand dump
...
Lets you dump the raw USER, the BOOT0 and BOOT1 partitions.
The USER dumping is done in 4 8GB parts, splitted in 4GB files.
2018-05-01 15:28:48 +03:00
nwert
8365426fc3
So it has come to this.
2018-05-01 17:22:03 +12:00
nwert
6181b39f14
License.
2018-03-27 12:04:16 +13:00
nwert
fb1ebd9a06
Fix uart for opt, actually use params.
2018-03-16 10:21:31 +13:00
nwert
3077c47c39
Add readme.
2018-03-15 12:44:43 +13:00
nwert
332e5921aa
Remove superfluous files.
2018-03-15 12:42:06 +13:00
nwert
10b4b7d1cb
Add hardware buttons, cpu booting, tsec booting.
2018-03-15 12:30:46 +13:00
nwert
6f6683e05b
Initial commit.
2018-03-07 14:13:23 +13:00
