Chuanhong Guo cf50f72069 ath79: ar913x: fix eth pll register ... PLL for eth0 internal clock on ar913x is at 0x18050014 and AR913X_ETH0_PLL_SHIFT is 20 instead of 17 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>		2018-08-13 08:37:19 +02:00
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adm5120
adm8668
apm821xx
ar7
ar71xx	kernel: bump 4.9 to 4.9.119	2018-08-10 18:43:23 +02:00
arc770
archs38
armvirt
at91	at91: do not build image for at91-q5xr5	2018-08-12 11:34:50 +02:00
ath25
ath79	ath79: ar913x: fix eth pll register	2018-08-13 08:37:19 +02:00
au1000
bcm53xx
brcm47xx
brcm63xx
brcm2708
cns3xxx	cns3xxx: correct size specifier in watchdog init print	2018-08-08 16:05:16 +02:00
gemini
generic	kernel: bump 4.14 to 4.14.62	2018-08-10 18:43:23 +02:00
imx6
ipq40xx
ipq806x
ixp4xx
kirkwood
lantiq
layerscape	kernel: bump 4.9 to 4.9.119	2018-08-10 18:43:23 +02:00
malta
mcs814x
mediatek	kernel: bump 4.14 to 4.14.62	2018-08-10 18:43:23 +02:00
mpc85xx
mvebu
mxs
octeon
octeontx
omap
omap24xx
orion
oxnas
pistachio
ppc40x
ppc44x
ramips	ramips: fix BR-6478ACv2 support	2018-08-13 08:37:19 +02:00
rb532
samsung
sunxi	kernel: bump 4.14 to 4.14.62	2018-08-10 18:43:23 +02:00
uml
x86
xburst
zynq
Makefile