310 lines
7.2 KiB
C
310 lines
7.2 KiB
C
/*
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* Misc useful routines to access NIC local SROM/OTP .
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*
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* Copyright 2007, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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*/
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#ifndef _bcmsrom_h_
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#define _bcmsrom_h_
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/* Maximum srom: 4 Kilobits == 512 bytes */
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#define SROM_MAX 512
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#define SROM_WORDS 64
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#define SROM3_SWRGN_OFF 28 /* s/w region offset in words */
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#define SROM_SSID 2
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#define SROM_WL1LHMAXP 29
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#define SROM_WL1LPAB0 30
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#define SROM_WL1LPAB1 31
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#define SROM_WL1LPAB2 32
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#define SROM_WL1HPAB0 33
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#define SROM_WL1HPAB1 34
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#define SROM_WL1HPAB2 35
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#define SROM_MACHI_IL0 36
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#define SROM_MACMID_IL0 37
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#define SROM_MACLO_IL0 38
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#define SROM_MACHI_ET0 39
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#define SROM_MACMID_ET0 40
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#define SROM_MACLO_ET0 41
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#define SROM_MACHI_ET1 42
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#define SROM_MACMID_ET1 43
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#define SROM_MACLO_ET1 44
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#define SROM3_MACHI 37
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#define SROM3_MACMID 38
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#define SROM3_MACLO 39
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#define SROM_BXARSSI2G 40
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#define SROM_BXARSSI5G 41
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#define SROM_TRI52G 42
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#define SROM_TRI5GHL 43
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#define SROM_RXPO52G 45
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#define SROM2_ENETPHY 45
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#define SROM_AABREV 46
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/* Fields in AABREV */
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#define SROM_BR_MASK 0x00ff
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#define SROM_CC_MASK 0x0f00
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#define SROM_CC_SHIFT 8
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#define SROM_AA0_MASK 0x3000
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#define SROM_AA0_SHIFT 12
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#define SROM_AA1_MASK 0xc000
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#define SROM_AA1_SHIFT 14
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#define SROM_WL0PAB0 47
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#define SROM_WL0PAB1 48
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#define SROM_WL0PAB2 49
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#define SROM_LEDBH10 50
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#define SROM_LEDBH32 51
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#define SROM_WL10MAXP 52
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#define SROM_WL1PAB0 53
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#define SROM_WL1PAB1 54
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#define SROM_WL1PAB2 55
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#define SROM_ITT 56
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#define SROM_BFL 57
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#define SROM_BFL2 28
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#define SROM3_BFL2 61
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#define SROM_AG10 58
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#define SROM_CCODE 59
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#define SROM_OPO 60
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#define SROM3_LEDDC 62
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#define SROM_CRCREV 63
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/* SROM Rev 4: Reallocate the software part of the srom to accomodate
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* MIMO features. It assumes up to two PCIE functions and 440 bytes
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* of useable srom i.e. the useable storage in chips with OTP that
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* implements hardware redundancy.
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*/
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#define SROM4_WORDS 220
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#define SROM4_SIGN 32
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#define SROM4_SIGNATURE 0x5372
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#define SROM4_BREV 33
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#define SROM4_BFL0 34
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#define SROM4_BFL1 35
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#define SROM4_BFL2 36
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#define SROM4_BFL3 37
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#define SROM5_BFL0 37
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#define SROM5_BFL1 38
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#define SROM5_BFL2 39
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#define SROM5_BFL3 40
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#define SROM4_MACHI 38
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#define SROM4_MACMID 39
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#define SROM4_MACLO 40
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#define SROM5_MACHI 41
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#define SROM5_MACMID 42
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#define SROM5_MACLO 43
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#define SROM4_CCODE 41
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#define SROM4_REGREV 42
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#define SROM5_CCODE 34
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#define SROM5_REGREV 35
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#define SROM4_LEDBH10 43
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#define SROM4_LEDBH32 44
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#define SROM5_LEDBH10 59
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#define SROM5_LEDBH32 60
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#define SROM4_LEDDC 45
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#define SROM5_LEDDC 45
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#define SROM4_AA 46
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#define SROM4_AA2G_MASK 0x00ff
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#define SROM4_AA2G_SHIFT 0
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#define SROM4_AA5G_MASK 0xff00
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#define SROM4_AA5G_SHIFT 8
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#define SROM4_AG10 47
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#define SROM4_AG32 48
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#define SROM4_TXPID2G 49
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#define SROM4_TXPID5G 51
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#define SROM4_TXPID5GL 53
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#define SROM4_TXPID5GH 55
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#define SROM4_TXRXC 61
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#define SROM4_TXCHAIN_MASK 0x000f
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#define SROM4_TXCHAIN_SHIFT 0
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#define SROM4_RXCHAIN_MASK 0x00f0
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#define SROM4_RXCHAIN_SHIFT 4
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#define SROM4_SWITCH_MASK 0xff00
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#define SROM4_SWITCH_SHIFT 8
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/* Per-path fields */
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#define MAX_PATH 4
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#define SROM4_PATH0 64
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#define SROM4_PATH1 87
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#define SROM4_PATH2 110
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#define SROM4_PATH3 133
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#define SROM4_2G_ITT_MAXP 0
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#define SROM4_2G_PA 1
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#define SROM4_5G_ITT_MAXP 5
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#define SROM4_5GLH_MAXP 6
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#define SROM4_5G_PA 7
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#define SROM4_5GL_PA 11
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#define SROM4_5GH_PA 15
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/* Fields in the ITT_MAXP and 5GLH_MAXP words */
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#define B2G_MAXP_MASK 0xff
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#define B2G_ITT_SHIFT 8
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#define B5G_MAXP_MASK 0xff
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#define B5G_ITT_SHIFT 8
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#define B5GH_MAXP_MASK 0xff
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#define B5GL_MAXP_SHIFT 8
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/* All the miriad power offsets */
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#define SROM4_2G_CCKPO 156
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#define SROM4_2G_OFDMPO 157
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#define SROM4_5G_OFDMPO 159
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#define SROM4_5GL_OFDMPO 161
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#define SROM4_5GH_OFDMPO 163
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#define SROM4_2G_MCSPO 165
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#define SROM4_5G_MCSPO 173
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#define SROM4_5GL_MCSPO 181
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#define SROM4_5GH_MCSPO 189
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#define SROM4_CDDPO 197
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#define SROM4_STBCPO 198
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#define SROM4_BW40PO 199
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#define SROM4_BWDUPPO 200
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#define SROM4_CRCREV 219
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/*SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
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* This is acombined srom for both MIMO and SISO boards, usable in
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* the .130 4Kilobit OTP with hardware redundancy.
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*/
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#define SROM8_SIGN 64
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#define SROM8_BREV 65
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#define SROM8_BFL0 66
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#define SROM8_BFL1 67
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#define SROM8_BFL2 68
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#define SROM8_BFL3 69
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#define SROM8_MACHI 70
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#define SROM8_MACMID 71
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#define SROM8_MACLO 72
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#define SROM8_CCODE 73
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#define SROM8_REGREV 74
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#define SROM8_LEDBH10 75
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#define SROM8_LEDBH32 76
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#define SROM8_LEDDC 77
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#define SROM8_AA 78
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#define SROM8_AG10 79
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#define SROM8_AG32 80
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#define SROM8_TXRXC 81
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#define SROM8_BXARSSI2G 82
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#define SROM8_BXARSSI5G 83
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#define SROM8_TRI52G 84
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#define SROM8_TRI5GHL 85
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#define SROM8_RXPO52G 86
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/* Per-path offsets & fields */
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#define SROM8_PATH0 96
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#define SROM8_PATH1 112
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#define SROM8_PATH2 128
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#define SROM8_PATH3 144
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#define SROM8_2G_ITT_MAXP 0
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#define SROM8_2G_PA 1
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#define SROM8_5G_ITT_MAXP 4
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#define SROM8_5GLH_MAXP 5
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#define SROM8_5G_PA 6
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#define SROM8_5GL_PA 9
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#define SROM8_5GH_PA 12
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/* All the miriad power offsets */
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#define SROM8_2G_CCKPO 160
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#define SROM8_2G_OFDMPO 161
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#define SROM8_5G_OFDMPO 163
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#define SROM8_5GL_OFDMPO 165
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#define SROM8_5GH_OFDMPO 167
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#define SROM8_2G_MCSPO 169
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#define SROM8_5G_MCSPO 177
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#define SROM8_5GL_MCSPO 185
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#define SROM8_5GH_MCSPO 193
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#define SROM8_CDDPO 201
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#define SROM8_STBCPO 202
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#define SROM8_BW40PO 203
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#define SROM8_BWDUPPO 204
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/* SISO PA parameters are in the path0 spaces */
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#define SROM8_SISO 96
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/* Legacy names for SISO PA paramters */
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#define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP)
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#define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA)
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#define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1)
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#define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2)
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#define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP)
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#define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP)
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#define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA)
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#define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1)
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#define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2)
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#define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA)
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#define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1)
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#define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2)
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#define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA)
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#define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1)
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#define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2)
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#define SROM8_CRCREV 219
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/* Prototypes */
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extern int srom_var_init(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
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char **vars, uint *count);
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extern int srom_read(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
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uint byteoff, uint nbytes, uint16 *buf);
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extern int srom_write(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
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uint byteoff, uint nbytes, uint16 *buf);
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extern int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt,
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char **vars, uint *count);
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#endif /* _bcmsrom_h_ */
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