86 lines
3.3 KiB
Diff
86 lines
3.3 KiB
Diff
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From c57a0efc17627d0077408544ded02674aefdecae Mon Sep 17 00:00:00 2001
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From: Vladimir Oltean <vladimir.oltean@nxp.com>
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Date: Mon, 6 Jan 2020 16:59:02 +0200
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Subject: [PATCH] Revert "arm64: dts: LS1028a-rdb: use Ethernet PHY interrupt"
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This reverts commit 841edb98671cfc4d6f010393ac429c78082ec4bd.
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There are 2 separate issues with interrupts on the LS1028A-RDB board:
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1. The GPIO1_DAT25 interrupt line is shared, so there is a real risk of
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race conditions if used in edge-triggered mode, as we currently do.
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This can be illustrated in the following setup:
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- Take 2 LS1028A-RDB boards
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- Connect swp0 to swp0, swp1 to swp1, swp2 to swp2
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- Plug/unplug the power to board 2, 10 times in a row. This will make
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the PHYs lose link simultaneously.
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- Notice that at one point, the net devices on board 1 remain in a
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state where not all the links are down (visible in "ip link"):
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5: swp0: <BROADCAST,MULTICAST,UP> mtu 1468 qdisc pfifo_fast master br0 state UP mode DEFAULT group default qlen 1000
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link/ether be:97:36:d3:3d:70 brd ff:ff:ff:ff:ff:ff
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6: swp1: <BROADCAST,MULTICAST,UP> mtu 1468 qdisc pfifo_fast master br0 state UP mode DEFAULT group default qlen 1000
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link/ether be:97:36:d3:3d:71 brd ff:ff:ff:ff:ff:ff
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7: swp2: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1468 qdisc pfifo_fast master br0 state DOWN mode DEFAULT group default qlen 1000
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link/ether be:97:36:d3:3d:72 brd ff:ff:ff:ff:ff:ff
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This cannot be solved by making the interrupts level-triggered,
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because the gpio-mpc8xxx controller only supports generating
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edge-triggered interrupts. So the effective reality is that we
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cannot not use shared interrupts connected to the gpio1
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interrupt-parent.
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2. The uBUS1 and uBUS2 slots that share this interrupt line with the
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Ethernet PHYs are not pulled up by default, they are left floating on
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current revisions of the LS1028A-RDB boards. So sufficient electrical
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noise on these lines will make the CPLD think there's an interrupt
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request, so it asserts the GPIO1_DAT25 signal and leaves it asserted.
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This means that the PHYs on those boards will never have link when
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used in interrupt mode, because their IRQ will be masked by the uBUS
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line that is erroneously kept asserted. In poll mode this issue does
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not occur.
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Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 10 ----------
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1 file changed, 10 deletions(-)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
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@@ -206,8 +206,6 @@
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#size-cells = <0>;
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sgmii_phy0: ethernet-phy@2 {
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reg = <0x2>;
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- interrupt-parent = <&gpio1>;
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- interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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};
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@@ -219,26 +217,18 @@
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&enetc_mdio_pf3 {
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qsgmii_phy1: ethernet-phy@4 {
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reg = <0x10>;
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- interrupt-parent = <&gpio1>;
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- interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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};
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qsgmii_phy2: ethernet-phy@5 {
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reg = <0x11>;
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- interrupt-parent = <&gpio1>;
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- interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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};
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qsgmii_phy3: ethernet-phy@6 {
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reg = <0x12>;
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- interrupt-parent = <&gpio1>;
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- interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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};
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qsgmii_phy4: ethernet-phy@7 {
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reg = <0x13>;
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- interrupt-parent = <&gpio1>;
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- interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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