43 lines
1.4 KiB
C
43 lines
1.4 KiB
C
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#ifndef _HW_TIMER_H
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#define _HW_TIMER_H
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#if APB_CLK_FREQ == 80 * 1000000
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// 80 MHz divided by 16 is 5 MHz count rate.
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#define US_TO_RTC_TIMER_TICKS(t) ((t) * 5)
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#else
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#define US_TO_RTC_TIMER_TICKS(t) \
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((t) ? \
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(((t) > 0x35A) ? \
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(((t)>>2) * ((APB_CLK_FREQ>>4)/250000) + ((t)&0x3) * ((APB_CLK_FREQ>>4)/1000000)) : \
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(((t) *(APB_CLK_FREQ>>4)) / 1000000)) : \
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0)
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#endif
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typedef enum {
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FRC1_SOURCE = 0,
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NMI_SOURCE = 1,
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} FRC1_TIMER_SOURCE_TYPE;
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bool ICACHE_RAM_ATTR platform_hw_timer_arm_ticks(os_param_t owner, uint32_t ticks);
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bool ICACHE_RAM_ATTR platform_hw_timer_arm_us(os_param_t owner, uint32_t microseconds);
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bool platform_hw_timer_set_func(os_param_t owner, void (* user_hw_timer_cb_set)(os_param_t), os_param_t arg);
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bool platform_hw_timer_init(os_param_t owner, FRC1_TIMER_SOURCE_TYPE source_type, bool autoload);
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bool ICACHE_RAM_ATTR platform_hw_timer_close(os_param_t owner);
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uint32_t ICACHE_RAM_ATTR platform_hw_timer_get_delay_ticks(os_param_t owner);
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bool platform_hw_timer_init_exclusive(FRC1_TIMER_SOURCE_TYPE source_type, bool autoload, void (* frc1_timer_cb)(os_param_t), os_param_t arg, void (*nmi_timer_cb)(void) );
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bool ICACHE_RAM_ATTR platform_hw_timer_close_exclusive();
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bool ICACHE_RAM_ATTR platform_hw_timer_arm_ticks_exclusive(uint32_t ticks);
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bool ICACHE_RAM_ATTR platform_hw_timer_arm_us_exclusive(uint32_t microseconds);
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#endif
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