265 lines
10 KiB
Python
265 lines
10 KiB
Python
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"""Transformation for inserting refrecence count inc/dec opcodes.
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This transformation happens towards the end of compilation. Before this
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transformation, reference count management is not explicitly handled at all.
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By postponing this pass, the previous passes are simpler as they don't have
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to update reference count opcodes.
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The approach is to decrement reference counts soon after a value is no
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longer live, to quickly free memory (and call __del__ methods), though
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there are no strict guarantees -- other than that local variables are
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freed before return from a function.
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Function arguments are a little special. They are initially considered
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'borrowed' from the caller and their reference counts don't need to be
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decremented before returning. An assignment to a borrowed value turns it
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into a regular, owned reference that needs to freed before return.
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"""
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from typing import Dict, Iterable, List, Set, Tuple
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from mypyc.analysis.dataflow import (
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get_cfg,
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analyze_must_defined_regs,
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analyze_live_regs,
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analyze_borrowed_arguments,
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cleanup_cfg,
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AnalysisDict
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)
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from mypyc.ir.ops import (
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BasicBlock, Assign, RegisterOp, DecRef, IncRef, Branch, Goto, Op, ControlOp, Value, Register,
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LoadAddress, Integer, KeepAlive
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)
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from mypyc.ir.func_ir import FuncIR, all_values
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Decs = Tuple[Tuple[Value, bool], ...]
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Incs = Tuple[Value, ...]
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# A cache of basic blocks that decrement and increment specific values
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# and then jump to some target block. This lets us cut down on how
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# much code we generate in some circumstances.
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BlockCache = Dict[Tuple[BasicBlock, Decs, Incs], BasicBlock]
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def insert_ref_count_opcodes(ir: FuncIR) -> None:
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"""Insert reference count inc/dec opcodes to a function.
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This is the entry point to this module.
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"""
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cfg = get_cfg(ir.blocks)
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values = all_values(ir.arg_regs, ir.blocks)
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borrowed = {value for value in values if value.is_borrowed}
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args: Set[Value] = set(ir.arg_regs)
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live = analyze_live_regs(ir.blocks, cfg)
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borrow = analyze_borrowed_arguments(ir.blocks, cfg, borrowed)
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defined = analyze_must_defined_regs(ir.blocks, cfg, args, values, strict_errors=True)
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ordering = make_value_ordering(ir)
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cache: BlockCache = {}
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for block in ir.blocks[:]:
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if isinstance(block.ops[-1], (Branch, Goto)):
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insert_branch_inc_and_decrefs(block,
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cache,
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ir.blocks,
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live.before,
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borrow.before,
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borrow.after,
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defined.after,
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ordering)
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transform_block(block, live.before, live.after, borrow.before, defined.after)
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cleanup_cfg(ir.blocks)
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def is_maybe_undefined(post_must_defined: Set[Value], src: Value) -> bool:
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return isinstance(src, Register) and src not in post_must_defined
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def maybe_append_dec_ref(ops: List[Op], dest: Value,
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defined: 'AnalysisDict[Value]', key: Tuple[BasicBlock, int]) -> None:
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if dest.type.is_refcounted and not isinstance(dest, Integer):
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ops.append(DecRef(dest, is_xdec=is_maybe_undefined(defined[key], dest)))
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def maybe_append_inc_ref(ops: List[Op], dest: Value) -> None:
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if dest.type.is_refcounted:
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ops.append(IncRef(dest))
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def transform_block(block: BasicBlock,
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pre_live: 'AnalysisDict[Value]',
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post_live: 'AnalysisDict[Value]',
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pre_borrow: 'AnalysisDict[Value]',
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post_must_defined: 'AnalysisDict[Value]') -> None:
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old_ops = block.ops
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ops: List[Op] = []
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for i, op in enumerate(old_ops):
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key = (block, i)
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assert op not in pre_live[key]
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dest = op.dest if isinstance(op, Assign) else op
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stolen = op.stolen()
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# Incref any references that are being stolen that stay live, were borrowed,
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# or are stolen more than once by this operation.
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for i, src in enumerate(stolen):
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if src in post_live[key] or src in pre_borrow[key] or src in stolen[:i]:
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maybe_append_inc_ref(ops, src)
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# For assignments to registers that were already live,
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# decref the old value.
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if (dest not in pre_borrow[key] and dest in pre_live[key]):
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assert isinstance(op, Assign)
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maybe_append_dec_ref(ops, dest, post_must_defined, key)
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# Strip KeepAlive. Its only purpose is to help with this transform.
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if not isinstance(op, KeepAlive):
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ops.append(op)
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# Control ops don't have any space to insert ops after them, so
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# their inc/decrefs get inserted by insert_branch_inc_and_decrefs.
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if isinstance(op, ControlOp):
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continue
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for src in op.unique_sources():
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# Decrement source that won't be live afterwards.
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if src not in post_live[key] and src not in pre_borrow[key] and src not in stolen:
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maybe_append_dec_ref(ops, src, post_must_defined, key)
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# Decrement the destination if it is dead after the op and
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# wasn't a borrowed RegisterOp
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if (not dest.is_void and dest not in post_live[key]
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and not (isinstance(op, RegisterOp) and dest.is_borrowed)):
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maybe_append_dec_ref(ops, dest, post_must_defined, key)
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block.ops = ops
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def insert_branch_inc_and_decrefs(
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block: BasicBlock,
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cache: BlockCache,
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blocks: List[BasicBlock],
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pre_live: 'AnalysisDict[Value]',
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pre_borrow: 'AnalysisDict[Value]',
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post_borrow: 'AnalysisDict[Value]',
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post_must_defined: 'AnalysisDict[Value]',
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ordering: Dict[Value, int]) -> None:
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"""Insert inc_refs and/or dec_refs after a branch/goto.
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Add dec_refs for registers that become dead after a branch.
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Add inc_refs for registers that become unborrowed after a branch or goto.
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Branches are special as the true and false targets may have a different
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live and borrowed register sets. Add new blocks before the true/false target
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blocks that tweak reference counts.
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Example where we need to add an inc_ref:
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def f(a: int) -> None
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if a:
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a = 1
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return a # a is borrowed if condition is false and unborrowed if true
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"""
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prev_key = (block, len(block.ops) - 1)
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source_live_regs = pre_live[prev_key]
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source_borrowed = post_borrow[prev_key]
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source_defined = post_must_defined[prev_key]
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term = block.terminator
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for i, target in enumerate(term.targets()):
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# HAX: After we've checked against an error value the value we must not touch the
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# refcount since it will be a null pointer. The correct way to do this would be
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# to perform data flow analysis on whether a value can be null (or is always
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# null).
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omitted: Iterable[Value]
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if isinstance(term, Branch) and term.op == Branch.IS_ERROR and i == 0:
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omitted = (term.value,)
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else:
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omitted = ()
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decs = after_branch_decrefs(
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target, pre_live, source_defined,
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source_borrowed, source_live_regs, ordering, omitted)
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incs = after_branch_increfs(
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target, pre_live, pre_borrow, source_borrowed, ordering)
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term.set_target(i, add_block(decs, incs, cache, blocks, target))
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def after_branch_decrefs(label: BasicBlock,
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pre_live: 'AnalysisDict[Value]',
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source_defined: Set[Value],
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source_borrowed: Set[Value],
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source_live_regs: Set[Value],
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ordering: Dict[Value, int],
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omitted: Iterable[Value]) -> Tuple[Tuple[Value, bool], ...]:
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target_pre_live = pre_live[label, 0]
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decref = source_live_regs - target_pre_live - source_borrowed
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if decref:
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return tuple((reg, is_maybe_undefined(source_defined, reg))
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for reg in sorted(decref, key=lambda r: ordering[r])
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if reg.type.is_refcounted and reg not in omitted)
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return ()
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def after_branch_increfs(label: BasicBlock,
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pre_live: 'AnalysisDict[Value]',
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pre_borrow: 'AnalysisDict[Value]',
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source_borrowed: Set[Value],
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ordering: Dict[Value, int]) -> Tuple[Value, ...]:
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target_pre_live = pre_live[label, 0]
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target_borrowed = pre_borrow[label, 0]
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incref = (source_borrowed - target_borrowed) & target_pre_live
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if incref:
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return tuple(reg
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for reg in sorted(incref, key=lambda r: ordering[r])
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if reg.type.is_refcounted)
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return ()
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def add_block(decs: Decs, incs: Incs, cache: BlockCache,
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blocks: List[BasicBlock], label: BasicBlock) -> BasicBlock:
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if not decs and not incs:
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return label
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# TODO: be able to share *partial* results
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if (label, decs, incs) in cache:
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return cache[label, decs, incs]
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block = BasicBlock()
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blocks.append(block)
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block.ops.extend(DecRef(reg, is_xdec=xdec) for reg, xdec in decs)
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block.ops.extend(IncRef(reg) for reg in incs)
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block.ops.append(Goto(label))
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cache[label, decs, incs] = block
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return block
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def make_value_ordering(ir: FuncIR) -> Dict[Value, int]:
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"""Create a ordering of values that allows them to be sorted.
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This omits registers that are only ever read.
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"""
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# TODO: Never initialized values??
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result: Dict[Value, int] = {}
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n = 0
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for arg in ir.arg_regs:
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result[arg] = n
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n += 1
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for block in ir.blocks:
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for op in block.ops:
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if (isinstance(op, LoadAddress)
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and isinstance(op.src, Register)
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and op.src not in result):
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# Taking the address of a register allows initialization.
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result[op.src] = n
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n += 1
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if isinstance(op, Assign):
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if op.dest not in result:
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result[op.dest] = n
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n += 1
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elif op not in result:
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result[op] = n
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n += 1
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return result
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