317 lines
12 KiB
C
317 lines
12 KiB
C
/*
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* Copyright (c) 2024 hydrogenium2020-offical
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* Copyright (c) 2018 naehrwert
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "t124.h"
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#include "clock.h"
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#include "timer.h"
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#include "pmc.h"
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#include "printf.h"
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#include "util.h"
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#include "types.h"
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enum {
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OSC_FREQ_13 = 0,
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OSC_FREQ_16P8 = 1,
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OSC_FREQ_19P2 = 4,
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OSC_FREQ_38P4 = 5,
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OSC_FREQ_12 = 8,
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OSC_FREQ_48 = 9,
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OSC_FREQ_26 = 12
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};
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/* This table defines the frequency dividers for every PLL to turn the external
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* OSC clock into the frequencies defined by TEGRA_PLL*_KHZ in soc/clock.h.
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* All PLLs have three dividers (n, m and p), with the governing formula for
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* the output frequency being CF = (IN / m), VCO = CF * n and OUT = VCO / (2^p).
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* All divisor configurations must meet the PLL's constraints for VCO and CF:
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* PLLX: 12 MHz < CF < 50 MHz, 700 MHz < VCO < 3000 MHz
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* PLLC: 12 MHz < CF < 50 MHz, 600 MHz < VCO < 1400 MHz
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* PLLM: 12 MHz < CF < 50 MHz, 400 MHz < VCO < 1066 MHz
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* PLLP: 1 MHz < CF < 6 MHz, 200 MHz < VCO < 700 MHz
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* PLLD: 1 MHz < CF < 6 MHz, 500 MHz < VCO < 1000 MHz
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* PLLU: 1 MHz < CF < 6 MHz, 480 MHz < VCO < 960 MHz
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* PLLDP: 12 MHz < CF < 38 MHz, 600 MHz < VCO < 1200 MHz
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* (values taken from Linux' drivers/clk/tegra/clk-tegra124.c). */
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struct {
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int khz;
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struct pllcx_dividers pllx; /* target: CONFIG_PLLX_KHZ */
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struct pllcx_dividers pllc; /* target: 600 MHz */
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/* PLLM is set up dynamically by clock_sdram(). */
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/* PLLP is hardwired to 408 MHz in HW (unless we set BASE_OVRD). */
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struct pllu_dividers pllu; /* target; 960 MHz */
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struct pllcx_dividers plldp; /* target; 270 MHz */
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/* PLLDP treats p differently (OUT = VCO / (p + 1) for p < 6). */
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} static const osc_table[16] = {
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[OSC_FREQ_12] = {
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.khz = 12000,
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.pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0},
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.pllc = {.n = 50, .m = 1, .p = 0},
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.pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2},
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.plldp = {.n = 90, .m = 1, .p = 3},
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},
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[OSC_FREQ_13] = {
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.khz = 13000,
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.pllx = {.n = TEGRA_PLLX_KHZ / 13000, .m = 1, .p = 0},
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.pllc = {.n = 46, .m = 1, .p = 0}, /* 598.0 MHz */
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.pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12, .lfcon = 2},
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.plldp = {.n = 83, .m = 1, .p = 3}, /* 269.8 MHz */
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},
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[OSC_FREQ_16P8] = {
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.khz = 16800,
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.pllx = {.n = TEGRA_PLLX_KHZ / 16800, .m = 1, .p = 0},
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.pllc = {.n = 71, .m = 1, .p = 1}, /* 596.4 MHz */
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.pllu = {.n = 400, .m = 7, .p = 0, .cpcon = 5, .lfcon = 2},
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.plldp = {.n = 64, .m = 1, .p = 3}, /* 268.8 MHz */
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},
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[OSC_FREQ_19P2] = {
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.khz = 19200,
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.pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m = 1, .p = 0},
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.pllc = {.n = 62, .m = 1, .p = 1}, /* 595.2 MHz */
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.pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2},
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.plldp = {.n = 56, .m = 1, .p = 3}, /* 268.8 MHz */
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},
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[OSC_FREQ_26] = {
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.khz = 26000,
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.pllx = {.n = TEGRA_PLLX_KHZ / 26000, .m = 1, .p = 0},
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.pllc = {.n = 23, .m = 1, .p = 0}, /* 598.0 MHz */
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.pllu = {.n = 960, .m = 26, .p = 0, .cpcon = 12, .lfcon = 2},
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.plldp = {.n = 83, .m = 2, .p = 3}, /* 269.8 MHz */
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},
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/* These oscillators get predivided as PLL inputs... n/m/p divisors for
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* 38.4 should always match 19.2, and 48 should always match 12. */
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[OSC_FREQ_38P4] = {
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.khz = 38400,
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.pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m = 1, .p = 0},
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.pllc = {.n = 62, .m = 1, .p = 1}, /* 595.2 MHz */
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.pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2},
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.plldp = {.n = 56, .m = 1, .p = 3}, /* 268.8 MHz */
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},
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[OSC_FREQ_48] = {
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.khz = 48000,
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.pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0},
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.pllc = {.n = 50, .m = 1, .p = 0},
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.pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2},
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.plldp = {.n = 90, .m = 1, .p = 3},
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},
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};
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enum {
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SCLK_SYS_STATE_STDBY,
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SCLK_SYS_STATE_IDLE,
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SCLK_SYS_STATE_RUN,
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SCLK_SYS_STATE_IRQ = 4U,
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SCLK_SYS_STATE_FIQ = 8U,
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};
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void clock_enable(const clk_rst_t *clk)
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{
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// Put clock into reset.
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CLOCK(clk->reset) = (CLOCK(clk->reset) & ~BIT(clk->index)) | BIT(clk->index);
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// Disable.
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CLOCK(clk->enable) &= ~BIT(clk->index);
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// Configure clock source if required.
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if (clk->source)
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CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29);
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// Enable.
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CLOCK(clk->enable) = (CLOCK(clk->enable) & ~BIT(clk->index)) | BIT(clk->index);
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sleep(2);
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// Take clock off reset.
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CLOCK(clk->reset) &= ~BIT(clk->index);
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}
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void clock_disable(const clk_rst_t *clk)
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{
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// Put clock into reset.
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CLOCK(clk->reset) = (CLOCK(clk->reset) & ~BIT(clk->index)) | BIT(clk->index);
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// Disable.
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CLOCK(clk->enable) &= ~BIT(clk->index);
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}
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static void init_pll(u32 pll_base_offset, u32 pll_misc_offset, const union pll_fields pll, u32 lock)
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{
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//TODO: rename
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u32 dividers = pll.div.n << PLL_BASE_DIVN_SHIFT |
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pll.div.m << PLL_BASE_DIVM_SHIFT |
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pll.div.p << PLL_BASE_DIVP_SHIFT;
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u32 misc_con = pll.div.cpcon << PLL_MISC_CPCON_SHIFT |
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pll.div.lfcon << PLL_MISC_LFCON_SHIFT;
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/* Write dividers but BYPASS the PLL while we're messing with it. */
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CLOCK(pll_base_offset)=dividers | (1<<CLK_RST_CONTROLLER_PLLC_BASE_PLLC_BYPASS_SHIFT);
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/*
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* Set Lock bit, CPCON and LFCON fields (default to 0 if it doesn't
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* exist for this PLL)
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*/
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CLOCK(pll_misc_offset)=(lock | misc_con);
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/* Enable PLL and take it back out of BYPASS */
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CLOCK(pll_base_offset)=dividers | (1 << CLK_RST_CONTROLLER_PLLC_BASE_PLLC_ENABLE_SHIFT);
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/* Wait for lock ready */
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while (!(CLOCK(pll_base_offset) & (1 << CLK_RST_CONTROLLER_PLLC_BASE_PLLC_LOCK_SHIFT)));
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}
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/* From Coreboot */
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/* Clock configuration. */
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void config_oscillators()
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{
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// clock_get_osc_bits()
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// Copied from coreboot
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// OSC_FREQ_13 = 0,
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// OSC_FREQ_16P8 = 1,
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// OSC_FREQ_19P2 = 4,
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// OSC_FREQ_38P4 = 5,
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// OSC_FREQ_12 = 8,
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// OSC_FREQ_48 = 9,
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// OSC_FREQ_26 = 12
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//
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// 8 is 12mhz
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//TODO other osc freq porting
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u32 clk_osc_bit=(CLOCK(CLK_RST_CONTROLLER_OSC_CTRL)&CLK_OSC_FREQ_MASK)>>CLK_OSC_FREQ_SHIFT;
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/* Set PLLC dynramp_step A to 0x2b and B to 0xb (from U-Boot -- why? */
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC2)=(0x2b << 17 | 0xb << 9);
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// static const osc_table[16] = {
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// [OSC_FREQ_12] = {
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// .khz = 12000,
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// .pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0},
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// .pllc = {.n = 50, .m = 1, .p = 0},
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// .pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2},
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// .plldp = {.n = 90, .m = 1, .p = 3},
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// },
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/* Max out the AVP clock before everything else (need PLLC for that). */
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init_pll(CLK_RST_CONTROLLER_PLLC_BASE,CLK_RST_CONTROLLER_PLLC_MISC,osc_table[clk_osc_bit].pllc,(1 << CLK_RST_CONTROLLER_PLLC_MISC_PLLC_LOCK_ENABLE_SHIFT));
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printf_("[x] PLLC setup\n");
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/* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA
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* features section in the TRM). */
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE)=
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TEGRA_HCLK_RATIO << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_AHB_RATE_SHIFT |
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TEGRA_PCLK_RATIO << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_APB_RATE_SHIFT;
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT)=CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ)
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<< CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_RATIO_SHIFT | (1 << CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_CLKEN_SHIFT) | (1 << CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_RSTN_SHIFT);
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/* sclk = 300 MHz */
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY)=
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CLK_RST_CONTROLLER_SCLK_BURST_POLICY_SYS_STATE_RUN << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_SYS_STATE_SHIFT |
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CLK_RST_CONTROLLER_SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE_PLLC_OUT1 <<CLK_RST_CONTROLLER_SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE_SHIFT;
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printf_("[x] System Clock:300 Mhz\n");
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// Read oscillator drive strength from OSC_EDPD_OVER.XOFS and copy
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// to OSC_CTRL.XOFS and set XOE. --copied from lp0
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/*
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* Ambiguous quote from u-boot. TODO: what's this mean?
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* "should update same value in PMC_OSC_EDPD_OVER XOFS
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* field for warmboot "
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*/
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u32 xofs = (PMC(APBDEV_PMC_OSC_EDPD_OVER) &
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PMC_XOFS_MASK) >> PMC_XOFS_SHIFT;
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/*Change the oscillator drive strength (from U-Boot -- why?) */
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u32 osc_ctrl = CLOCK(CLK_RST_CONTROLLER_OSC_CTRL);
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osc_ctrl &= ~CLK_OSC_XOFS_MASK;
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osc_ctrl |= (xofs << CLK_OSC_XOFS_SHIFT);
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osc_ctrl |= CLK_OSC_XOE;
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CLOCK(CLK_RST_CONTROLLER_OSC_CTRL)=osc_ctrl;
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/* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */
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CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= ~PLLX_MISC3_IDDQ; // Disable IDDQ.
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/* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */
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//pll2 ovr shift should be 18?
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CLOCK(CLK_RST_CONTROLLER_PLLP_OUTA)=((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << (1 << CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_RATIO_SHIFT) |
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(1 << CLK_RST_CONTROLLER_PLLP_OUTA_PLLP_OUT1_OVRRIDE_SHIFT) | (1 << CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_CLKEN_SHIFT) | (1 << CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_RSTN_SHIFT)) << PLL_OUT1_SHIFT |
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(CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << (1 << CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_RATIO_SHIFT) |
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(1 << CLK_RST_CONTROLLER_PLLP_OUTA_PLLP_OUT1_OVRRIDE_SHIFT) | (1 << CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_CLKEN_SHIFT) | (1 << CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_RSTN_SHIFT)) << PLL_OUT2_SHIFT);
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CLOCK(CLK_RST_CONTROLLER_PLLP_OUTB)= ((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << (1 << CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_RATIO_SHIFT) |
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(1 << CLK_RST_CONTROLLER_PLLP_OUTA_PLLP_OUT1_OVRRIDE_SHIFT) | (1 << CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_CLKEN_SHIFT) | (1 << CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_RSTN_SHIFT)) << PLL_OUT3_SHIFT |
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(CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << (1 << CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_RATIO_SHIFT) |
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(1 << CLK_RST_CONTROLLER_PLLP_OUTA_PLLP_OUT1_OVRRIDE_SHIFT) | (1 << CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_CLKEN_SHIFT) | (1 << CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_RSTN_SHIFT)) << PLL_OUT4_SHIFT);
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init_pll(CLK_RST_CONTROLLER_PLLX_BASE,CLK_RST_CONTROLLER_PLLX_MISC,osc_table[clk_osc_bit].pllx,(1 << CLK_RST_CONTROLLER_PLLX_MISC_PLLX_LOCK_ENABLE_SHIFT));
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init_pll(CLK_RST_CONTROLLER_PLLU_BASE,CLK_RST_CONTROLLER_PLLU_MISC,osc_table[clk_osc_bit].pllu,(1 << CLK_RST_CONTROLLER_PLLU_MISC_PLLU_LOCK_ENABLE_SHIFT));
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//TODO usb device init later
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/* Graphics just has to be different. There's a few more bits we
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* need to set in here, but it makes sense just to restrict all the
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* special bits to this one function. Imported form graphics_pll(void)
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*/
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/* the vendor code sets the dither bit (28)
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* an undocumented bit (24)
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* and clamp while we mess with it (22)
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* Dither is pretty important to display port
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* so we really do need to handle these bits.
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* I'm not willing to not clamp it, even if
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* it might "mostly work" with it not set,
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* I don't want to find out in a few months
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* that it is needed.
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*/
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u32 scfg = (1<<28) | (1<<24) | (1<<22);
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CLOCK(CLK_RST_CONTROLLER_PLLDP_SS_CFG)=scfg;
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init_pll(CLK_RST_CONTROLLER_PLLDP_BASE, CLK_RST_CONTROLLER_PLLDP_MISC,
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osc_table[clk_osc_bit].plldp, (1 << CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_LOCK_ENABLE_SHIFT));
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/* leave dither and undoc bits set, release clamp */
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scfg = (1<<28) | (1<<24);
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CLOCK(CLK_RST_CONTROLLER_PLLDP_SS_CFG)=scfg;
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/* disp1 will be set when panel information (pixel clock) is
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* retrieved (clock_display).
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*/
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printf_("[X] PLLP,PLLX,PLLU,PLLDP setup\n");
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}
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static const clk_rst_t _clock_uart[] = {
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{ CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, CLK_L_UARTA, 0, 2 },
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{ CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, CLK_L_UARTB, 0, 2 },
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{ CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC, CLK_H_UARTC, 0, 2 },
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{ CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD, CLK_U_UARTD, 0, 2 },
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};
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void clock_enable_uart(u32 idx)
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{
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clock_enable(&_clock_uart[idx]);
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}
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#define UART_SRC_CLK_DIV_EN BIT(24)
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int clock_uart_use_src_div(u32 idx, u32 baud)
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{
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u32 clk_src_div = CLOCK(_clock_uart[idx].source) & 0xE0000000;
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if (baud == 3000000)
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CLOCK(_clock_uart[idx].source) = clk_src_div | UART_SRC_CLK_DIV_EN | 15;
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else if (baud == 1000000)
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CLOCK(_clock_uart[idx].source) = clk_src_div | UART_SRC_CLK_DIV_EN | 49;
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else
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{
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CLOCK(_clock_uart[idx].source) = clk_src_div | 2;
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return 1;
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}
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return 0;
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}
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