ce26824ed9
Here is the detail: 1. It has 2Ranks and 8bit*8. 2. There are some differences between H5TC4G63AFR-RDA and H5TC4G63AFR-PBA, and the parameters are not universal. If mixed use, it may lead to unstable data in memory writing (for example, data loss during writing).
278 lines
7.8 KiB
C
278 lines
7.8 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2022 CTCaer
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* Copyright (c) 2024 hydrogenium2020-offical
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _T124_CLOCK_H_
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#define _T124_CLOCK_H_
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#include "types.h"
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/*! Generic clock descriptor. */
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typedef struct _clk_rst_t
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{
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u16 reset;
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u16 enable;
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u16 source;
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u8 index;
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u8 clk_src;
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u8 clk_div;
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} clk_rst_t;
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/* soc-specific */
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#define TEGRA_CLK_M_KHZ 12000
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#define TEGRA_PLLX_KHZ 2000000
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#define TEGRA_PLLP_KHZ (408000)
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#define TEGRA_PLLC_KHZ (600000)
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#define TEGRA_PLLD_KHZ (925000)
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#define TEGRA_PLLU_KHZ (960000)
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#define TEGRA_SCLK_KHZ (300000)
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#define TEGRA_HCLK_RATIO 1
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#define TEGRA_HCLK_KHZ (TEGRA_SCLK_KHZ / (1 + TEGRA_HCLK_RATIO))
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#define TEGRA_PCLK_RATIO 0
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#define TEGRA_PCLK_KHZ (TEGRA_HCLK_KHZ / (1 + TEGRA_PCLK_RATIO))
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#define CLK_RST_CONTROLLER_OSC_CTRL 0x50
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#define CLK_OSC_DRIVE_STRENGTH 7
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//PLLC
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#define CLK_RST_CONTROLLER_PLLC_BASE 0x80
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#define CLK_RST_CONTROLLER_PLLC_MISC 0x8c
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#define CLK_RST_CONTROLLER_PLLC_MISC_PLLC_LOCK_ENABLE_SHIFT 24
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#define CLK_RST_CONTROLLER_PLLC_MISC2 0x88
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#define CLK_RST_CONTROLLER_PLLC_BASE_PLLC_BYPASS_SHIFT 31
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#define CLK_RST_CONTROLLER_PLLC_OUT 0x84
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#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30
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#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_AHB_RATE_SHIFT 4
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#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_APB_RATE_SHIFT 0
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#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY 0x28
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#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_SYS_STATE_SHIFT 28
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#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_SYS_STATE_IDLE 1
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#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_SYS_STATE_RUN 2
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#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE_PLLC_OUT1 1
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#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE_PLLP_OUT4 2
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#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE_PLLP_OUT3 3
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#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE_PLLP_OUT2 4
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#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE_SHIFT 4
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//PLLP
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#define CLK_RST_CONTROLLER_PLLP_OUTA 0xA4
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#define CLK_RST_CONTROLLER_PLLP_OUTB 0xA8
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#define CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_RATIO_SHIFT 8
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#define CLK_RST_CONTROLLER_PLLP_OUTA_PLLP_OUT1_OVRRIDE_SHIFT 2
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#define CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_CLKEN_SHIFT 1
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#define CLK_RST_CONTROLLER_PLLM_OUT_PLLM_OUT1_RSTN_SHIFT 0
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//PLLX
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#define PLLX_MISC3_IDDQ (1U << 3)
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#define CLK_RST_CONTROLLER_PLLX_BASE 0xe0
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#define CLK_RST_CONTROLLER_PLLX_MISC 0xe4
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#define CLK_RST_CONTROLLER_PLLX_MISC_3 0x518
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#define CLK_RST_CONTROLLER_PLLX_MISC_PLLX_LOCK_ENABLE_SHIFT 18
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//PLLU
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#define CLK_RST_CONTROLLER_PLLU_BASE 0xc0
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#define CLK_RST_CONTROLLER_PLLU_MISC 0xcc
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#define CLK_RST_CONTROLLER_PLLU_MISC_PLLU_LOCK_ENABLE_SHIFT 22
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//PLLDP (Graphis PLL)
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#define CLK_RST_CONTROLLER_PLLDP_SS_CFG 0x598
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#define CLK_RST_CONTROLLER_PLLDP_BASE 0x590
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#define CLK_RST_CONTROLLER_PLLDP_MISC 0x594
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#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_LOCK_ENABLE_SHIFT 30
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#define PLL_OUT1_SHIFT 0
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#define PLL_OUT2_SHIFT 16
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#define PLL_OUT3_SHIFT 0
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#define PLL_OUT4_SHIFT 16
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#define PLL_BASE_DIVN_SHIFT 8
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#define PLL_BASE_DIVM_SHIFT 0
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#define PLL_BASE_DIVP_SHIFT 20
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#define PLL_MISC_CPCON_SHIFT 8
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#define PLL_MISC_LFCON_SHIFT 4
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#define CLK_RST_CONTROLLER_PLLC_BASE_PLLC_ENABLE_SHIFT 30
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#define CLK_RST_CONTROLLER_PLLC_BASE_PLLC_LOCK_SHIFT 27
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#define PLLCX_BASE_LOCK BIT(27)
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#define DIV_ROUND_UP(x, y) ({ \
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__typeof__(x) _div_local_x = (x); \
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__typeof__(y) _div_local_y = (y); \
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(_div_local_x + _div_local_y - 1) / _div_local_y; \
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})
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#define CLK_DIVIDER(REF, FREQ) (DIV_ROUND_UP(((REF) * 2), (FREQ)) - 2)
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//MC
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#define CLK_RST_CONTROLLER_CLK_ENB_H_SET 0x328
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#define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284
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#define CLK_RST_CONTROLLER_RST_DEV_H_SET 0x308
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#define CLK_RST_CONTROLLER_RST_DEV_H_CLR 0x30C
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3a4
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/* SPECIAL CASE: PLLM, PLLC and PLLX use different-sized fields here */
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#define PLLCX_BASE_DIVP_MASK (0xfU << PLL_BASE_DIVP_SHIFT)
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#define PLLM_BASE_DIVP_MASK (0x1U << PLL_BASE_DIVP_SHIFT)
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#define PLLCMX_BASE_DIVN_MASK (0xffU << PLL_BASE_DIVN_SHIFT)
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#define PLLCMX_BASE_DIVM_MASK (0xffU << PLL_BASE_DIVM_SHIFT)
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enum {
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MC_EMEM_CFG_SIZE_MB_SHIFT = 0,
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MC_EMEM_CFG_SIZE_MB_MASK = 0x3fff,
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MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27,
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MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27,
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MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED = 1,
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MC_TIMING_CONTROL_TIMING_UPDATE = 1,
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};
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//EMC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19c
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#define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ (1 << 16)
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//PLLM
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#define PLLM_BASE 0x90
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#define PLLM_MISC1_BASE 0x98
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#define PLLM_MISC2_BASE 0x9c
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#define PLLM_MISC1_SETUP_SHIFT 0
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#define PLLM_MISC1_PD_LSHIFT_PH45_SHIFT 28
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#define PLLM_MISC1_PD_LSHIFT_PH90_SHIFT 29
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#define PLLM_MISC1_PD_LSHIFT_PH135_SHIFT 30
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#define PLLM_MISC2_KCP_SHIFT 1
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#define PLLM_MISC2_KVCO_SHIFT 0
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#define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0)
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/* CLK_RST_CONTROLLER_PLL*_BASE_0 */
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#define PLL_BASE_BYPASS (1U << 31)
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#define PLL_BASE_ENABLE (1U << 30)
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#define PLL_BASE_REF_DIS (1U << 29)
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#define PLL_BASE_OVRRIDE (1U << 28)
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#define PLL_BASE_LOCK (1U << 27)
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#define IO_STABILIZATION_DELAY (2)
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#define PLL_BASE_DIVP_SHIFT 20
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#define PLL_BASE_DIVP_MASK (7U << PLL_BASE_DIVP_SHIFT)
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#define PLL_BASE_DIVN_SHIFT 8
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#define PLL_BASE_DIVN_MASK (0x3ffU << PLL_BASE_DIVN_SHIFT)
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#define PLL_BASE_DIVM_SHIFT 0
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#define PLL_BASE_DIVM_MASK (0x1f << PLL_BASE_DIVM_SHIFT)
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//Reset
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#define CLK_RST_CONTROLLER_RST_DEVICES_L 0x4
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#define CLK_RST_CONTROLLER_RST_DEVICES_H 0x8
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#define CLK_RST_CONTROLLER_RST_DEVICES_U 0xC
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L 0x10
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H 0x14
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U 0x18
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//UART
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA 0x178
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB 0x17C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC 0x1A0
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD 0x1C0
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enum CLK_L_DEV
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{
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CLK_L_UARTA = 6,
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CLK_L_UARTB = 7,
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};
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enum CLK_H_DEV
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{
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CLK_H_UARTC = 23,
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};
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enum CLK_U_DEV
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{
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CLK_U_UARTD = 1,
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};
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enum {
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CLK_OSC_XOE = 0x1 << 0,
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CLK_OSC_XOFS_SHIFT = 4,
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CLK_OSC_XOFS_MASK = 0x3f << CLK_OSC_XOFS_SHIFT,
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CLK_OSC_FREQ_SHIFT = 28,
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CLK_OSC_FREQ_MASK = 0xf << CLK_OSC_FREQ_SHIFT
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};
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struct pll_dividers {
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u32 n : 10;
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u32 m : 8;
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u32 p : 4;
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u32 cpcon : 4;
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u32 lfcon : 4;
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u32 : 2;
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};
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/* Some PLLs have more restrictive divider bit lengths or are missing some
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* fields. Make sure to use the right struct in the osc_table definition to get
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* compile-time checking, but keep the bits aligned with struct pll_dividers so
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* they can be used interchangeably at run time. Add new formats as required. */
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struct pllcx_dividers {
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u32 n : 8;
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u32 : 2;
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u32 m : 8;
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u32 p : 4;
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u32 : 10;
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};
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struct pllpad_dividers {
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u32 n : 10;
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u32 m : 5;
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u32 : 3;
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u32 p : 3;
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u32 : 1;
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u32 cpcon : 4;
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u32 : 6;
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};
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struct pllu_dividers {
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u32 n : 10;
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u32 m : 5;
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u32 : 3;
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u32 p : 1;
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u32 : 3;
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u32 cpcon : 4;
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u32 lfcon : 4;
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u32 : 2;
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};
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union __attribute__((transparent_union)) pll_fields {
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u32 raw;
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struct pll_dividers div;
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struct pllcx_dividers cx;
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struct pllpad_dividers pad;
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struct pllu_dividers u;
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};
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void clock_enable(const clk_rst_t *clk);
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void clock_disable(const clk_rst_t *clk);
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void clock_enable_cl_dvfs();
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void clock_enable_i2c(u32 idx);
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void clock_enable_uart(u32 idx);
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void config_oscillators();
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int clock_uart_use_src_div(u32 idx, u32 baud);
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#endif
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