115 lines
4.5 KiB
C
115 lines
4.5 KiB
C
/*
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* Copyright (c) 2024 hydrogenium2020-offical
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* Copyright (c) 2018 naehrwert
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "t124.h"
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#include "clock.h"
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#include "timer.h"
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#include "pmc.h"
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#include "printf.h"
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#include "util.h"
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static clk_rst_t _clock_cl_dvfs = { 0x35C, 0x364, 0, 0x1B, 0, 0 };
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//I2C default parameters - TLOW: 4, THIGH: 2, DEBOUNCE: 0, FM_DIV: 26.
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static const clk_rst_t _clock_i2c[] = {
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{ CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 12, 0, 19 }, //20.4MHz -> 100KHz
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{ CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2, 22, 0, 4 }, //81.6MHz -> 400KHz
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{ 0, 0, 0, 0, 0, 4 }, //81.6MHz -> 400KHz
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{ 0, 0, 0, 0, 0, 19 }, //20.4MHz -> 100KHz
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{ CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 15, 0, 4 }, //81.6MHz -> 400KHz
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{ 0, 0, 0, 0, 0, 19 } //20.4MHz -> 100KHz
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};
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void clock_enable(const clk_rst_t *clk)
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{
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// Put clock into reset.
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CLOCK(clk->reset) = (CLOCK(clk->reset) & ~BIT(clk->index)) | BIT(clk->index);
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// Disable.
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CLOCK(clk->enable) &= ~BIT(clk->index);
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// Configure clock source if required.
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if (clk->source)
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CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29);
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// Enable.
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CLOCK(clk->enable) = (CLOCK(clk->enable) & ~BIT(clk->index)) | BIT(clk->index);
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sleep(2);
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// Take clock off reset.
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CLOCK(clk->reset) &= ~BIT(clk->index);
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}
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void clock_disable(const clk_rst_t *clk)
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{
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// Put clock into reset.
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CLOCK(clk->reset) = (CLOCK(clk->reset) & ~BIT(clk->index)) | BIT(clk->index);
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// Disable.
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CLOCK(clk->enable) &= ~BIT(clk->index);
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}
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//For NS Switch
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/*
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* CLK_OSC - 38.4 MHz crystal.
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* CLK_M - 19.2 MHz (osc/2).
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* CLK_S - 32.768 KHz (from PMIC).
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* SCLK - 204MHz init (-> 408MHz -> OC).
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* HCLK - 204MHz init (-> 408MHz -> OC).
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* PCLK - 68MHz init (-> 136MHz -> OC/4).
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*/
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//For P1761(Ardbeg,Fuze F1)
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/*
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* CLK_OSC - 12 MHz crystal.
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* CLK_M - 12 MHz (osc/2).
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* CLK_S - 32.768 KHz (from PMIC).
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* SCLK - 127.5MHz init (-> 408MHz -> OC).
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* HCLK - 127.5MHz init (-> 408MHz -> OC).
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* PCLK - 31.875?MHz init (-> 136MHz -> OC/4).
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*/
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void config_oscillators()
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{
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CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 0; // Clear 3-2bit and set CLK_M_DIVISOR to 1.the 3-2bit is divisor.
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SYSCTR0(SYSCTR0_CNTFID0) = 12000000; // Set counter frequency. 12Mhz
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//This register is for 1 microsecond. bit7-0->DIVISOR bit15-8->DIVIDEND.So we need 1/12
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TIMER0(TIMERUS_USEC_CFG) = 0x0B; // For 12MHz clk_m. 1/12 -> 0x00/0x0b
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CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x80000071; // Set OSC to 12MHz and drive strength.
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PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81) | 0xE; // Set LP0 OSC drive strength.
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PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF) | PMC_OSC_EDPD_OVER_OSC_CTRL_OVER;
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PMC(APBDEV_PMC_CNTRL2) = (PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF) | PMC_CNTRL2_HOLD_CKE_LOW_EN;
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//Not impl in T124?Only in T210 and newer
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//PMC(APB_MISC_GP_ASDBGREG) = (PMC(APB_MISC_GP_ASDBGREG) & 0xFCFFFFFF) | (2 << 24); // CFG2TMC_RAM_SVOP_PDP.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x00; // Set HCLK div to 1 and PCLK div to 1.
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//CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF; // PLLMB disable.
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PMC(APBDEV_PMC_TSC_MULT) = (PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000) | 0x16E0; // 0x249F = 12000000 * (16 / 32.768 kHz).
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set BPMP/SCLK div to 1.
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set BPMP/SCLK source to Run and PLLP_OUT2 (204MHz).
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CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; // Enable SUPER_SDIV to 1.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3.
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}
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void clock_enable_cl_dvfs(){
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clock_enable(&_clock_cl_dvfs);
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}
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void clock_enable_i2c(u32 idx)
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{
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clock_enable(&_clock_i2c[idx]);
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} |