ce26824ed9
Here is the detail: 1. It has 2Ranks and 8bit*8. 2. There are some differences between H5TC4G63AFR-RDA and H5TC4G63AFR-PBA, and the parameters are not universal. If mixed use, it may lead to unstable data in memory writing (for example, data loss during writing).
438 lines
13 KiB
C
438 lines
13 KiB
C
/*
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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/**
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* Defines the SDRAM parameter structure.
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*
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* Note that PLLM is used by EMC. The field names are in camel case to ease
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* directly converting BCT config files (*.cfg) into C structure.
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*/
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#ifndef _T124_SDRAM_LP0_
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#define _T124_SDRAM_LP0_
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#include <stddef.h>
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#include <stdint.h>
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#include "types.h"
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void sdram_lp0_save_params(const sdram_params_t124 *sdram);
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// Memory Controller registers we need/care about
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struct tegra_mc_regs {
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u32 rsvd_0x0[4]; /* 0x00 */
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u32 smmu_config; /* 0x10 */
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u32 smmu_tlb_config; /* 0x14 */
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u32 smmu_ptc_config; /* 0x18 */
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u32 smmu_ptb_asid; /* 0x1c */
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u32 smmu_ptb_data; /* 0x20 */
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u32 rsvd_0x24[3]; /* 0x24 */
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u32 smmu_tlb_flush; /* 0x30 */
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u32 smmu_ptc_flush; /* 0x34 */
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u32 rsvd_0x38[6]; /* 0x38 */
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u32 emem_cfg; /* 0x50 */
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u32 emem_adr_cfg; /* 0x54 */
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u32 emem_adr_cfg_dev0; /* 0x58 */
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u32 emem_adr_cfg_dev1; /* 0x5c */
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u32 rsvd_0x60[1]; /* 0x60 */
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u32 emem_adr_cfg_bank_mask_0; /* 0x64 */
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u32 emem_adr_cfg_bank_mask_1; /* 0x68 */
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u32 emem_adr_cfg_bank_mask_2; /* 0x6c */
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u32 rsvd_0x70[8]; /* 0x70 */
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u32 emem_arb_cfg; /* 0x90 */
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u32 emem_arb_outstanding_req; /* 0x94 */
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u32 emem_arb_timing_rcd; /* 0x98 */
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u32 emem_arb_timing_rp; /* 0x9c */
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u32 emem_arb_timing_rc; /* 0xa0 */
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u32 emem_arb_timing_ras; /* 0xa4 */
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u32 emem_arb_timing_faw; /* 0xa8 */
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u32 emem_arb_timing_rrd; /* 0xac */
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u32 emem_arb_timing_rap2pre; /* 0xb0 */
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u32 emem_arb_timing_wap2pre; /* 0xb4 */
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u32 emem_arb_timing_r2r; /* 0xb8 */
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u32 emem_arb_timing_w2w; /* 0xbc */
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u32 emem_arb_timing_r2w; /* 0xc0 */
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u32 emem_arb_timing_w2r; /* 0xc4 */
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u32 rsvd_0xc8[2]; /* 0xc8 */
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u32 emem_arb_da_turns; /* 0xd0 */
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u32 emem_arb_da_covers; /* 0xd4 */
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u32 emem_arb_misc0; /* 0xd8 */
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u32 emem_arb_misc1; /* 0xdc */
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u32 emem_arb_ring1_throttle; /* 0xe0 */
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u32 emem_arb_ring3_throttle; /* 0xe4 */
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u32 emem_arb_override; /* 0xe8 */
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u32 emem_arb_rsv; /* 0xec */
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u32 rsvd_0xf0[1]; /* 0xf0 */
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u32 clken_override; /* 0xf4 */
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u32 timing_control_dbg; /* 0xf8 */
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u32 timing_control; /* 0xfc */
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u32 stat_control; /* 0x100 */
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u32 rsvd_0x104[65]; /* 0x104 */
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u32 emem_arb_isochronous_0; /* 0x208 */
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u32 emem_arb_isochronous_1; /* 0x20c */
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u32 emem_arb_isochronous_2; /* 0x210 */
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u32 rsvd_0x214[38]; /* 0x214 */
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u32 dis_extra_snap_levels; /* 0x2ac */
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u32 rsvd_0x2b0[90]; /* 0x2b0 */
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u32 video_protect_vpr_override; /* 0x418 */
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u32 rsvd_0x41c[93]; /* 0x41c */
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u32 video_protect_vpr_override1; /* 0x590 */
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u32 rsvd_0x594[29]; /* 0x594 */
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u32 display_snap_ring; /* 0x608 */
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u32 rsvd_0x60c[15]; /* 0x60c */
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u32 video_protect_bom; /* 0x648 */
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u32 video_protect_size_mb; /* 0x64c */
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u32 video_protect_reg_ctrl; /* 0x650 */
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u32 rsvd_0x654[4]; /* 0x654 */
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u32 emem_cfg_access_ctrl; /* 0x664 */
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u32 rsvd_0x668[2]; /* 0x668 */
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u32 sec_carveout_bom; /* 0x670 */
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u32 sec_carveout_size_mb; /* 0x674 */
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u32 sec_carveout_reg_ctrl; /* 0x678 */
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u32 rsvd_0x67c[187]; /* 0x67c */
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u32 emem_arb_override_1; /* 0x968 */
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u32 rsvd_0x96c[3]; /* 0x96c */
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u32 video_protect_bom_adr_hi; /* 0x978 */
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u32 rsvd_0x97c[2]; /* 0x97c */
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u32 video_protect_gpu_override_0; /* 0x984 */
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u32 video_protect_gpu_override_1; /* 0x988 */
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u32 rsvd_0x98c[5]; /* 0x98c */
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u32 mts_carveout_bom; /* 0x9a0 */
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u32 mts_carveout_size_mb; /* 0x9a4 */
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u32 mts_carveout_adr_hi; /* 0x9a8 */
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u32 mts_carveout_reg_ctrl; /* 0x9ac */
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u32 rsvd_0x9b0[4]; /* 0x9b0 */
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u32 emem_bank_swizzle_cfg0; /* 0x9c0 */
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u32 emem_bank_swizzle_cfg1; /* 0x9c4 */
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u32 emem_bank_swizzle_cfg2; /* 0x9c8 */
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u32 emem_bank_swizzle_cfg3; /* 0x9cc */
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u32 rsvd_0x9d0[1]; /* 0x9d0 */
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u32 sec_carveout_adr_hi; /* 0x9d4 */
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};
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enum {
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MC_EMEM_CFG_SIZE_MB_SHIFT = 0,
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MC_EMEM_CFG_SIZE_MB_MASK = 0x3fff,
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MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27,
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MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27,
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MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED = 1,
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MC_TIMING_CONTROL_TIMING_UPDATE = 1,
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};
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struct tegra_emc_regs {
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u32 intstatus; /* 0x0 */
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u32 intmask; /* 0x4 */
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u32 dbg; /* 0x8 */
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u32 cfg; /* 0xc */
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u32 adr_cfg; /* 0x10 */
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u32 rsvd_0x14[3]; /* 0x14 */
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u32 refctrl; /* 0x20 */
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u32 pin; /* 0x24 */
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u32 timing_control; /* 0x28 */
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u32 rc; /* 0x2c */
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u32 rfc; /* 0x30 */
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u32 ras; /* 0x34 */
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u32 rp; /* 0x38 */
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u32 r2w; /* 0x3c */
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u32 w2r; /* 0x40 */
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u32 r2p; /* 0x44 */
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u32 w2p; /* 0x48 */
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u32 rd_rcd; /* 0x4c */
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u32 wr_rcd; /* 0x50 */
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u32 rrd; /* 0x54 */
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u32 rext; /* 0x58 */
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u32 wdv; /* 0x5c */
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u32 quse; /* 0x60 */
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u32 qrst; /* 0x64 */
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u32 qsafe; /* 0x68 */
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u32 rdv; /* 0x6c */
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u32 refresh; /* 0x70 */
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u32 burst_refresh_num; /* 0x74 */
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u32 pdex2wr; /* 0x78 */
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u32 pdex2rd; /* 0x7c */
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u32 pchg2pden; /* 0x80 */
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u32 act2pden; /* 0x84 */
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u32 ar2pden; /* 0x88 */
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u32 rw2pden; /* 0x8c */
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u32 txsr; /* 0x90 */
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u32 tcke; /* 0x94 */
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u32 tfaw; /* 0x98 */
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u32 trpab; /* 0x9c */
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u32 tclkstable; /* 0xa0 */
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u32 tclkstop; /* 0xa4 */
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u32 trefbw; /* 0xa8 */
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u32 rsvd_0xac[1]; /* 0xac */
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u32 odt_write; /* 0xb0 */
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u32 odt_read; /* 0xb4 */
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u32 wext; /* 0xb8 */
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u32 ctt; /* 0xbc */
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u32 rfc_slr; /* 0xc0 */
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u32 mrs_wait_cnt2; /* 0xc4 */
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u32 mrs_wait_cnt; /* 0xc8 */
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u32 mrs; /* 0xcc */
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u32 emrs; /* 0xd0 */
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u32 ref; /* 0xd4 */
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u32 pre; /* 0xd8 */
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u32 nop; /* 0xdc */
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u32 self_ref; /* 0xe0 */
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u32 dpd; /* 0xe4 */
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u32 mrw; /* 0xe8 */
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u32 mrr; /* 0xec */
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u32 cmdq; /* 0xf0 */
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u32 mc2emcq; /* 0xf4 */
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u32 xm2dqspadctrl3; /* 0xf8 */
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u32 rsvd_0xfc[1]; /* 0xfc */
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u32 fbio_spare; /* 0x100 */
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u32 fbio_cfg5; /* 0x104 */
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u32 fbio_wrptr_eq_2; /* 0x108 */
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u32 rsvd_0x10c[2]; /* 0x10c */
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u32 fbio_cfg6; /* 0x114 */
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u32 rsvd_0x118[2]; /* 0x118 */
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u32 cfg_rsv; /* 0x120 */
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u32 acpd_control; /* 0x124 */
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u32 rsvd_0x128[1]; /* 0x128 */
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u32 emrs2; /* 0x12c */
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u32 emrs3; /* 0x130 */
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u32 mrw2; /* 0x134 */
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u32 mrw3; /* 0x138 */
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u32 mrw4; /* 0x13c */
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u32 clken_override; /* 0x140 */
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u32 r2r; /* 0x144 */
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u32 w2w; /* 0x148 */
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u32 einput; /* 0x14c */
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u32 einput_duration; /* 0x150 */
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u32 puterm_extra; /* 0x154 */
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u32 tckesr; /* 0x158 */
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u32 tpd; /* 0x15c */
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u32 rsvd_0x160[81]; /* 0x160 */
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u32 auto_cal_config; /* 0x2a4 */
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u32 auto_cal_interval; /* 0x2a8 */
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u32 auto_cal_status; /* 0x2ac */
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u32 req_ctrl; /* 0x2b0 */
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u32 status; /* 0x2b4 */
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u32 cfg_2; /* 0x2b8 */
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u32 cfg_dig_dll; /* 0x2bc */
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u32 cfg_dig_dll_period; /* 0x2c0 */
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u32 rsvd_0x2c4[1]; /* 0x2c4 */
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u32 dig_dll_status; /* 0x2c8 */
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u32 rdv_mask; /* 0x2cc */
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u32 wdv_mask; /* 0x2d0 */
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u32 rsvd_0x2d4[1]; /* 0x2d4 */
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u32 ctt_duration; /* 0x2d8 */
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u32 ctt_term_ctrl; /* 0x2dc */
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u32 zcal_interval; /* 0x2e0 */
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u32 zcal_wait_cnt; /* 0x2e4 */
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u32 zcal_mrw_cmd; /* 0x2e8 */
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u32 zq_cal; /* 0x2ec */
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u32 xm2cmdpadctrl; /* 0x2f0 */
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u32 xm2cmdpadctrl2; /* 0x2f4 */
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u32 xm2dqspadctrl; /* 0x2f8 */
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u32 xm2dqspadctrl2; /* 0x2fc */
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u32 xm2dqpadctrl; /* 0x300 */
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u32 xm2dqpadctrl2; /* 0x304 */
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u32 xm2clkpadctrl; /* 0x308 */
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u32 xm2comppadctrl; /* 0x30c */
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u32 xm2vttgenpadctrl; /* 0x310 */
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u32 xm2vttgenpadctrl2; /* 0x314 */
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u32 xm2vttgenpadctrl3; /* 0x318 */
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u32 emcpaden; /* 0x31c */
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u32 xm2dqspadctrl4; /* 0x320 */
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u32 scratch0; /* 0x324 */
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u32 dll_xform_dqs0; /* 0x328 */
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u32 dll_xform_dqs1; /* 0x32c */
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u32 dll_xform_dqs2; /* 0x330 */
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u32 dll_xform_dqs3; /* 0x334 */
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u32 dll_xform_dqs4; /* 0x338 */
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u32 dll_xform_dqs5; /* 0x33c */
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u32 dll_xform_dqs6; /* 0x340 */
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u32 dll_xform_dqs7; /* 0x344 */
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u32 dll_xform_quse0; /* 0x348 */
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u32 dll_xform_quse1; /* 0x34c */
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u32 dll_xform_quse2; /* 0x350 */
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u32 dll_xform_quse3; /* 0x354 */
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u32 dll_xform_quse4; /* 0x358 */
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u32 dll_xform_quse5; /* 0x35c */
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u32 dll_xform_quse6; /* 0x360 */
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u32 dll_xform_quse7; /* 0x364 */
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u32 dll_xform_dq0; /* 0x368 */
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u32 dll_xform_dq1; /* 0x36c */
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u32 dll_xform_dq2; /* 0x370 */
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u32 dll_xform_dq3; /* 0x374 */
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u32 dli_rx_trim0; /* 0x378 */
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u32 dli_rx_trim1; /* 0x37c */
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u32 dli_rx_trim2; /* 0x380 */
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u32 dli_rx_trim3; /* 0x384 */
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u32 dli_rx_trim4; /* 0x388 */
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u32 dli_rx_trim5; /* 0x38c */
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u32 dli_rx_trim6; /* 0x390 */
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u32 dli_rx_trim7; /* 0x394 */
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u32 dli_tx_trim0; /* 0x398 */
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u32 dli_tx_trim1; /* 0x39c */
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u32 dli_tx_trim2; /* 0x3a0 */
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u32 dli_tx_trim3; /* 0x3a4 */
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u32 dli_trim_txdqs0; /* 0x3a8 */
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u32 dli_trim_txdqs1; /* 0x3ac */
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u32 dli_trim_txdqs2; /* 0x3b0 */
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u32 dli_trim_txdqs3; /* 0x3b4 */
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u32 dli_trim_txdqs4; /* 0x3b8 */
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u32 dli_trim_txdqs5; /* 0x3bc */
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u32 dli_trim_txdqs6; /* 0x3c0 */
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u32 dli_trim_txdqs7; /* 0x3c4 */
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u32 rsvd_0x3c8[1]; /* 0x3c8 */
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u32 stall_then_exe_after_clkchange; /* 0x3cc */
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u32 rsvd_0x3d0[1]; /* 0x3d0 */
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u32 auto_cal_clk_status; /* 0x3d4 */
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u32 sel_dpd_ctrl; /* 0x3d8 */
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u32 pre_refresh_req_cnt; /* 0x3dc */
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u32 dyn_self_ref_control; /* 0x3e0 */
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u32 txsrdll; /* 0x3e4 */
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u32 ccfifo_addr; /* 0x3e8 */
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u32 ccfifo_data; /* 0x3ec */
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u32 ccfifo_status; /* 0x3f0 */
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u32 cdb_cntl_1; /* 0x3f4 */
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u32 cdb_cntl_2; /* 0x3f8 */
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u32 xm2clkpadctrl2; /* 0x3fc */
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u32 swizzle_rank0_byte_cfg; /* 0x400 */
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u32 swizzle_rank0_byte0; /* 0x404 */
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u32 swizzle_rank0_byte1; /* 0x408 */
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u32 swizzle_rank0_byte2; /* 0x40c */
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u32 swizzle_rank0_byte3; /* 0x410 */
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u32 swizzle_rank1_byte_cfg; /* 0x414 */
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u32 swizzle_rank1_byte0; /* 0x418 */
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u32 swizzle_rank1_byte1; /* 0x41c */
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u32 swizzle_rank1_byte2; /* 0x420 */
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u32 swizzle_rank1_byte3; /* 0x424 */
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u32 ca_training_start; /* 0x428 */
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u32 ca_training_busy; /* 0x42c */
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u32 ca_training_cfg; /* 0x430 */
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u32 ca_training_timing_cntl1; /* 0x434 */
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u32 ca_training_timing_cntl2; /* 0x438 */
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u32 ca_training_ca_lead_in; /* 0x43c */
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u32 ca_training_ca; /* 0x440 */
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u32 ca_training_ca_lead_out; /* 0x444 */
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u32 ca_training_result1; /* 0x448 */
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u32 ca_training_result2; /* 0x44c */
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u32 ca_training_result3; /* 0x450 */
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u32 ca_training_result4; /* 0x454 */
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u32 auto_cal_config2; /* 0x458 */
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u32 auto_cal_config3; /* 0x45c */
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u32 auto_cal_status2; /* 0x460 */
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u32 xm2cmdpadctrl3; /* 0x464 */
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u32 ibdly; /* 0x468 */
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u32 dll_xform_addr0; /* 0x46c */
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u32 dll_xform_addr1; /* 0x470 */
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u32 dll_xform_addr2; /* 0x474 */
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u32 dli_addr_trim; /* 0x478 */
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u32 dsr_vttgen_drv; /* 0x47c */
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u32 txdsrvttgen; /* 0x480 */
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u32 xm2cmdpadctrl4; /* 0x484 */
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u32 xm2cmdpadctrl5; /* 0x488 */
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u32 rsvd_0x48c[5]; /* 0x48c */
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u32 dll_xform_dqs8; /* 0x4a0 */
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u32 dll_xform_dqs9; /* 0x4a4 */
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u32 dll_xform_dqs10; /* 0x4a8 */
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u32 dll_xform_dqs11; /* 0x4ac */
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u32 dll_xform_dqs12; /* 0x4b0 */
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u32 dll_xform_dqs13; /* 0x4b4 */
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u32 dll_xform_dqs14; /* 0x4b8 */
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u32 dll_xform_dqs15; /* 0x4bc */
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u32 dll_xform_quse8; /* 0x4c0 */
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u32 dll_xform_quse9; /* 0x4c4 */
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u32 dll_xform_quse10; /* 0x4c8 */
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u32 dll_xform_quse11; /* 0x4cc */
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u32 dll_xform_quse12; /* 0x4d0 */
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u32 dll_xform_quse13; /* 0x4d4 */
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u32 dll_xform_quse14; /* 0x4d8 */
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u32 dll_xform_quse15; /* 0x4dc */
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u32 dll_xform_dq4; /* 0x4e0 */
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u32 dll_xform_dq5; /* 0x4e4 */
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u32 dll_xform_dq6; /* 0x4e8 */
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u32 dll_xform_dq7; /* 0x4ec */
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u32 rsvd_0x4f0[12]; /* 0x4f0 */
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u32 dli_trim_txdqs8; /* 0x520 */
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u32 dli_trim_txdqs9; /* 0x524 */
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u32 dli_trim_txdqs10; /* 0x528 */
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u32 dli_trim_txdqs11; /* 0x52c */
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u32 dli_trim_txdqs12; /* 0x530 */
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u32 dli_trim_txdqs13; /* 0x534 */
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u32 dli_trim_txdqs14; /* 0x538 */
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u32 dli_trim_txdqs15; /* 0x53c */
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u32 cdb_cntl_3; /* 0x540 */
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u32 xm2dqspadctrl5; /* 0x544 */
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u32 xm2dqspadctrl6; /* 0x548 */
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u32 xm2dqpadctrl3; /* 0x54c */
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u32 dll_xform_addr3; /* 0x550 */
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u32 dll_xform_addr4; /* 0x554 */
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u32 dll_xform_addr5; /* 0x558 */
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u32 rsvd_0x55c[1]; /* 0x55c */
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u32 cfg_pipe; /* 0x560 */
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u32 qpop; /* 0x564 */
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u32 quse_width; /* 0x568 */
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u32 puterm_width; /* 0x56c */
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u32 bgbias_ctl0; /* 0x570 */
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u32 puterm_adj; /* 0x574 */
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} __packed;
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enum {
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EMC_PIN_RESET_MASK = 1 << 8,
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EMC_PIN_RESET_ACTIVE = 0 << 8,
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EMC_PIN_RESET_INACTIVE = 1 << 8,
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EMC_PIN_DQM_MASK = 1 << 4,
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EMC_PIN_DQM_NORMAL = 0 << 4,
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EMC_PIN_DQM_INACTIVE = 1 << 4,
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EMC_PIN_CKE_MASK = 1 << 0,
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EMC_PIN_CKE_POWERDOWN = 0 << 0,
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EMC_PIN_CKE_NORMAL = 1 << 0,
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EMC_REF_CMD_MASK = 1 << 0,
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EMC_REF_CMD_REFRESH = 1 << 0,
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EMC_REF_NORMAL_MASK = 1 << 1,
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EMC_REF_NORMAL_INIT = 0 << 1,
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EMC_REF_NORMAL_ENABLED = 1 << 1,
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EMC_REF_NUM_SHIFT = 8,
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EMC_REF_NUM_MASK = 0xFF << EMC_REF_NUM_SHIFT,
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EMC_REF_DEV_SELECTN_SHIFT = 30,
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EMC_REF_DEV_SELECTN_MASK = 3 << EMC_REF_DEV_SELECTN_SHIFT,
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EMC_REFCTRL_REF_VALID_MASK = 1 << 31,
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EMC_REFCTRL_REF_VALID_DISABLED = 0 << 31,
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EMC_REFCTRL_REF_VALID_ENABLED = 1 << 31,
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EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK = 1 << 1,
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EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK = 1 << 2,
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EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK = 1 << 3,
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|
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EMC_NOP_NOP_CMD_SHIFT = 0,
|
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EMC_NOP_NOP_CMD_MASK = 1 << EMC_NOP_NOP_CMD_SHIFT,
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EMC_NOP_NOP_DEV_SELECTN_SHIFT = 30,
|
|
EMC_NOP_NOP_DEV_SELECTN_MASK = 3 << EMC_NOP_NOP_DEV_SELECTN_SHIFT,
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|
|
|
EMC_TIMING_CONTROL_TIMING_UPDATE = 1,
|
|
};
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#endif /* __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ */
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