ce26824ed9
Here is the detail: 1. It has 2Ranks and 8bit*8. 2. There are some differences between H5TC4G63AFR-RDA and H5TC4G63AFR-PBA, and the parameters are not universal. If mixed use, it may lead to unstable data in memory writing (for example, data loss during writing).
45 lines
1.5 KiB
C
45 lines
1.5 KiB
C
/*
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* Copyright (c) 2024 hydrogenium2020-offical
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2022 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "clock.h"
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#include "printf.h"
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#include "t124.h"
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#include "util.h"
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#include "mc.h"
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void mc_enable_ahb_redirect()
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{
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) = CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) & 0xFFF7FFFF | 0x80000;
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//MC(MC_IRAM_REG_CTRL) &= 0xFFFFFFFE;
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MC(MC_IRAM_BOM) = 0x40000000;
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MC(MC_IRAM_TOM) = 0x4003F000;
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}
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void mc_enable()
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{
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF | 0x40000000;
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//Enable MC clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFFFFFFFE | 1;
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//Enable EMC DLL clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) & 0xFFFFBFFF | 0x4000;
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x2000001; //Clear EMC and MC reset.
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sleep(5);
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//Enable ahb redirect
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mc_enable_ahb_redirect();
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} |