ce26824ed9
Here is the detail: 1. It has 2Ranks and 8bit*8. 2. There are some differences between H5TC4G63AFR-RDA and H5TC4G63AFR-PBA, and the parameters are not universal. If mixed use, it may lead to unstable data in memory writing (for example, data loss during writing).
248 lines
7.1 KiB
C
248 lines
7.1 KiB
C
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#ifndef _T124_EMC_H_
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#define _T124_EMC_H_
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#include "types.h"
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#define EMC_INTSTATUS 0x0
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#define EMC_INTMASK 0x4
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#define EMC_DBG 0x8
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#define EMC_CFG 0xC
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#define EMC_ADR_CFG 0x10
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#define EMC_REFCTRL 0x20
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#define EMC_PIN 0x24
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#define EMC_TIMING_CONTROL 0x28
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#define EMC_RC 0x2C
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#define EMC_RFC 0x30
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#define EMC_RAS 0x34
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#define EMC_RP 0x38
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#define EMC_R2W 0x3C
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#define EMC_W2R 0x40
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#define EMC_R2P 0x44
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#define EMC_W2P 0x48
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#define EMC_RD_RCD 0x4C
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#define EMC_WR_RCD 0x50
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#define EMC_RRD 0x54
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#define EMC_REXT 0x58
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#define EMC_WDV 0x5C
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#define EMC_QUSE 0x60
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#define EMC_QRST 0x64
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#define EMC_QSAFE 0x68
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#define EMC_RDV 0x6C
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#define EMC_REFRESH 0x70
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#define EMC_BURST_REFRESH_NUM 0x74
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#define EMC_PDEX2WR 0x78
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#define EMC_PDEX2RD 0x7C
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#define EMC_PCHG2PDEN 0x80
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#define EMC_ACT2PDEN 0x84
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#define EMC_AR2PDEN 0x88
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#define EMC_RW2PDEN 0x8C
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#define EMC_TXSR 0x90
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#define EMC_TCKE 0x94
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#define EMC_TFAW 0x98
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#define EMC_TRPAB 0x9C
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#define EMC_TCLKSTABLE 0xA0
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#define EMC_TCLKSTOP 0xA4
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#define EMC_TREFBW 0xA8
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#define EMC_ODT_WRITE 0xB0
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#define EMC_ODT_READ 0xB4
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#define EMC_WEXT 0xB8
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#define EMC_CTT 0xBC
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#define EMC_RFC_SLR 0xC0
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#define EMC_MRS_WAIT_CNT2 0xC4
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#define EMC_MRS_WAIT_CNT 0xC8
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#define EMC_MRS 0xCC
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#define EMC_EMRS 0xD0
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#define EMC_REF 0xD4
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#define EMC_PRE 0xD8
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#define EMC_NOP 0xDC
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#define EMC_SELF_REF 0xE0
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#define EMC_DPD 0xE4
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#define EMC_MRW 0xE8
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#define EMC_MRR 0xEC
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#define EMC_CMDQ 0xF0
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#define EMC_MC2EMCQ 0xF4
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#define EMC_XM2DQSPADCTRL3 0xF8
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#define EMC_FBIO_SPARE 0x100
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#define EMC_FBIO_CFG5 0x104
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#define EMC_FBIO_WRPTR_EQ_2 0x108
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#define EMC_FBIO_CFG6 0x114
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#define EMC_CFG_RSV 0x120
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#define EMC_ACPD_CONTROL 0x124
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#define EMC_EMRS2 0x12C
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#define EMC_EMRS3 0x130
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#define EMC_MRW2 0x134
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#define EMC_MRW3 0x138
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#define EMC_MRW4 0x13C
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#define EMC_CLKEN_OVERRIDE 0x140
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#define EMC_R2R 0x144
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#define EMC_W2W 0x148
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#define EMC_EINPUT 0x14C
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#define EMC_EINPUT_DURATION 0x150
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#define EMC_PUTERM_EXTRA 0x154
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#define EMC_TCKESR 0x158
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#define EMC_TPD 0x15C
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#define EMC_AUTO_CAL_CONFIG 0x2A4
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#define EMC_AUTO_CAL_INTERVAL 0x2A8
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#define EMC_AUTO_CAL_STATUS 0x2AC
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#define EMC_REQ_CTRL 0x2B0
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#define EMC_STATUS 0x2B4
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#define EMC_CFG_2 0x2B8
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#define EMC_CFG_DIG_DLL 0x2BC
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#define EMC_CFG_DIG_DLL_PERIOD 0x2C0
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#define EMC_DIG_DLL_STATUS 0x2C8
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#define EMC_RDV_MASK 0x2CC
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#define EMC_WDV_MASK 0x2D0
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#define EMC_CTT_DURATION 0x2D8
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#define EMC_CTT_TERM_CTRL 0x2DC
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#define EMC_ZCAL_INTERVAL 0x2E0
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#define EMC_ZCAL_WAIT_CNT 0x2E4
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#define EMC_ZCAL_MRW_CMD 0x2E8
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#define EMC_ZQ_CAL 0x2EC
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#define EMC_XM2CMDPADCTRL 0x2F0
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#define EMC_XM2CMDPADCTRL2 0x2F4
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#define EMC_XM2DQSPADCTRL 0x2F8
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#define EMC_XM2DQSPADCTRL2 0x2FC
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#define EMC_XM2DQPADCTRL 0x300
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#define EMC_XM2DQPADCTRL2 0x304
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#define EMC_XM2CLKPADCTRL 0x308
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#define EMC_XM2COMPPADCTRL 0x30C
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#define EMC_XM2VTTGENPADCTRL 0x310
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#define EMC_XM2VTTGENPADCTRL2 0x314
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#define EMC_XM2VTTGENPADCTRL3 0x318
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#define EMC_EMCPADEN 0x31C
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#define EMC_XM2DQSPADCTRL4 0x320
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#define EMC_SCRATCH0 0x324
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#define EMC_DLL_XFORM_DQS0 0x328
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#define EMC_DLL_XFORM_DQS1 0x32C
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#define EMC_DLL_XFORM_DQS2 0x330
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#define EMC_DLL_XFORM_DQS3 0x334
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#define EMC_DLL_XFORM_DQS4 0x338
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#define EMC_DLL_XFORM_DQS5 0x33C
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#define EMC_DLL_XFORM_DQS6 0x340
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#define EMC_DLL_XFORM_DQS7 0x344
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#define EMC_DLL_XFORM_QUSE0 0x348
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#define EMC_DLL_XFORM_QUSE1 0x34C
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#define EMC_DLL_XFORM_QUSE2 0x350
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#define EMC_DLL_XFORM_QUSE3 0x354
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#define EMC_DLL_XFORM_QUSE4 0x358
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#define EMC_DLL_XFORM_QUSE5 0x35C
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#define EMC_DLL_XFORM_QUSE6 0x360
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#define EMC_DLL_XFORM_QUSE7 0x364
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#define EMC_DLL_XFORM_DQ0 0x368
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#define EMC_DLL_XFORM_DQ1 0x36C
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#define EMC_DLL_XFORM_DQ2 0x370
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#define EMC_DLL_XFORM_DQ3 0x374
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#define EMC_DLI_RX_TRIM0 0x378
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#define EMC_DLI_RX_TRIM1 0x37C
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#define EMC_DLI_RX_TRIM2 0x380
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#define EMC_DLI_RX_TRIM3 0x384
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#define EMC_DLI_RX_TRIM4 0x388
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#define EMC_DLI_RX_TRIM5 0x38C
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#define EMC_DLI_RX_TRIM6 0x390
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#define EMC_DLI_RX_TRIM7 0x394
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#define EMC_DLI_TX_TRIM0 0x398
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#define EMC_DLI_TX_TRIM1 0x39C
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#define EMC_DLI_TX_TRIM2 0x3A0
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#define EMC_DLI_TX_TRIM3 0x3A4
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#define EMC_DLI_TRIM_TXDQS0 0x3A8
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#define EMC_DLI_TRIM_TXDQS1 0x3AC
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#define EMC_DLI_TRIM_TXDQS2 0x3B0
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#define EMC_DLI_TRIM_TXDQS3 0x3B4
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#define EMC_DLI_TRIM_TXDQS4 0x3B8
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#define EMC_DLI_TRIM_TXDQS5 0x3BC
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#define EMC_DLI_TRIM_TXDQS6 0x3C0
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#define EMC_DLI_TRIM_TXDQS7 0x3C4
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#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3CC
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#define EMC_AUTO_CAL_CLK_STATUS 0x3D4
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#define EMC_SEL_DPD_CTRL 0x3D8
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#define EMC_PRE_REFRESH_REQ_CNT 0x3DC
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#define EMC_DYN_SELF_REF_CONTROL 0x3E0
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#define EMC_TXSRDLL 0x3E4
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#define EMC_CCFIFO_ADDR 0x3E8
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#define EMC_CCFIFO_DATA 0x3EC
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#define EMC_CCFIFO_STATUS 0x3F0
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#define EMC_CDB_CNTL_1 0x3F4
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#define EMC_CDB_CNTL_2 0x3F8
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#define EMC_XM2CLKPADCTRL2 0x3FC
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#define EMC_SWIZZLE_RANK0_BYTE_CFG 0x400
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#define EMC_SWIZZLE_RANK0_BYTE0 0x404
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#define EMC_SWIZZLE_RANK0_BYTE1 0x408
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#define EMC_SWIZZLE_RANK0_BYTE2 0x40C
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#define EMC_SWIZZLE_RANK0_BYTE3 0x410
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#define EMC_SWIZZLE_RANK1_BYTE_CFG 0x414
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#define EMC_SWIZZLE_RANK1_BYTE0 0x418
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#define EMC_SWIZZLE_RANK1_BYTE1 0x41C
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#define EMC_SWIZZLE_RANK1_BYTE2 0x420
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#define EMC_SWIZZLE_RANK1_BYTE3 0x424
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#define EMC_CA_TRAINING_START 0x428
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#define EMC_CA_TRAINING_BUSY 0x42C
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#define EMC_CA_TRAINING_CFG 0x430
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#define EMC_CA_TRAINING_TIMING_CNTL1 0x434
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#define EMC_CA_TRAINING_TIMING_CNTL2 0x438
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#define EMC_CA_TRAINING_CA_LEAD_IN 0x43C
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#define EMC_CA_TRAINING_CA 0x440
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#define EMC_CA_TRAINING_CA_LEAD_OUT 0x444
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#define EMC_CA_TRAINING_RESULT1 0x448
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#define EMC_CA_TRAINING_RESULT2 0x44C
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#define EMC_CA_TRAINING_RESULT3 0x450
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#define EMC_CA_TRAINING_RESULT4 0x454
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#define EMC_AUTO_CAL_CONFIG2 0x458
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#define EMC_AUTO_CAL_CONFIG3 0x45C
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#define EMC_AUTO_CAL_STATUS2 0x460
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#define EMC_XM2CMDPADCTRL3 0x464
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#define EMC_IBDLY 0x468
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#define EMC_DLL_XFORM_ADDR0 0x46C
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#define EMC_DLL_XFORM_ADDR1 0x470
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#define EMC_DLL_XFORM_ADDR2 0x474
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#define EMC_DLI_ADDR_TRIM 0x478
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#define EMC_DSR_VTTGEN_DRV 0x47C
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#define EMC_TXDSRVTTGEN 0x480
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#define EMC_XM2CMDPADCTRL4 0x484
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#define EMC_XM2CMDPADCTRL5 0x488
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#define EMC_DLL_XFORM_DQS8 0x4A0
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#define EMC_DLL_XFORM_DQS9 0x4A4
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#define EMC_DLL_XFORM_DQS10 0x4A8
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#define EMC_DLL_XFORM_DQS11 0x4AC
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#define EMC_DLL_XFORM_DQS12 0x4B0
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#define EMC_DLL_XFORM_DQS13 0x4B4
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#define EMC_DLL_XFORM_DQS14 0x4B8
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#define EMC_DLL_XFORM_DQS15 0x4BC
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#define EMC_DLL_XFORM_QUSE8 0x4C0
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#define EMC_DLL_XFORM_QUSE9 0x4C4
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#define EMC_DLL_XFORM_QUSE10 0x4C8
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#define EMC_DLL_XFORM_QUSE11 0x4CC
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#define EMC_DLL_XFORM_QUSE12 0x4D0
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#define EMC_DLL_XFORM_QUSE13 0x4D4
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#define EMC_DLL_XFORM_QUSE14 0x4D8
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#define EMC_DLL_XFORM_QUSE15 0x4DC
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#define EMC_DLL_XFORM_DQ4 0x4E0
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#define EMC_DLL_XFORM_DQ5 0x4E4
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#define EMC_DLL_XFORM_DQ6 0x4E8
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#define EMC_DLL_XFORM_DQ7 0x4EC
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#define EMC_DLI_TRIM_TXDQS8 0x520
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#define EMC_DLI_TRIM_TXDQS9 0x524
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#define EMC_DLI_TRIM_TXDQS10 0x528
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#define EMC_DLI_TRIM_TXDQS11 0x52C
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#define EMC_DLI_TRIM_TXDQS12 0x530
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#define EMC_DLI_TRIM_TXDQS13 0x534
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#define EMC_DLI_TRIM_TXDQS14 0x538
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#define EMC_DLI_TRIM_TXDQS15 0x53C
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#define EMC_CDB_CNTL_3 0x540
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#define EMC_XM2DQSPADCTRL5 0x544
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#define EMC_XM2DQSPADCTRL6 0x548
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#define EMC_XM2DQPADCTRL3 0x54C
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#define EMC_DLL_XFORM_ADDR3 0x550
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#define EMC_DLL_XFORM_ADDR4 0x554
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#define EMC_DLL_XFORM_ADDR5 0x558
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#define EMC_CFG_PIPE 0x560
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#define EMC_QPOP 0x564
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#define EMC_QUSE_WIDTH 0x568
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#define EMC_PUTERM_WIDTH 0x56C
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#define EMC_BGBIAS_CTL0 0x570
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#define EMC_PUTERM_ADJ 0x574
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#endif
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