feat:SDRAM:bring up for 4GB DDR3L H5TC4G63AFR-RDA 792Mhz!

Here is the detail: 1. It has 2Ranks and 8bit*8. 2. There are some differences between H5TC4G63AFR-RDA and H5TC4G63AFR-PBA, and the parameters are not universal. If mixed use, it may lead to unstable data in memory writing (for example, data loss during writing).
2024-02-11 14:49:57 +08:00 · 2024-02-11 14:49:57 +08:00 · ce26824ed9
commit ce26824ed9
parent f808633517
20 changed files with 4595 additions and 21 deletions
--- a/3
+++ b/3
@ -20,6 +20,9 @@ OBJS = $(addprefix $(BUILD)/, \
 	gpio.o		\
 	heap.o		\
 	uart.o      \
+	sdram.o 	\
+	sdram_lp0.o \
+	io.o 		\
 )

 OBJS += $(addprefix $(BUILD)/, \
--- a/loader/clock.h
+++ b/loader/clock.h
@ -1,6 +1,7 @@
 /*
-* Copyright (c) 2024 hydrogenium2020-offical
 * Copyright (c) 2018 naehrwert
+* Copyright (c) 2018-2022 CTCaer
+* Copyright (c) 2024 hydrogenium2020-offical
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@ -14,9 +15,12 @@
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
-#include "types.h"

-/*! Generic clock descriptor. */
+#ifndef _T124_CLOCK_H_
+#define _T124_CLOCK_H_
+
+#include "types.h"
+	/*! Generic clock descriptor. */
 typedef struct _clk_rst_t
 {
 	u16 reset;
@ -85,6 +89,8 @@ typedef struct _clk_rst_t
 #define CLK_RST_CONTROLLER_PLLU_MISC 0xcc
 #define CLK_RST_CONTROLLER_PLLU_MISC_PLLU_LOCK_ENABLE_SHIFT 22

+
+
 //PLLDP (Graphis PLL)
 #define CLK_RST_CONTROLLER_PLLDP_SS_CFG 0x598
 #define CLK_RST_CONTROLLER_PLLDP_BASE 0x590
@ -116,12 +122,64 @@ typedef struct _clk_rst_t
 #define CLK_DIVIDER(REF, FREQ)	(DIV_ROUND_UP(((REF) * 2), (FREQ)) - 2)

 //MC
-#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19c
 #define CLK_RST_CONTROLLER_CLK_ENB_H_SET 0x328
 #define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284
 #define CLK_RST_CONTROLLER_RST_DEV_H_SET 0x308
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR 0x30C
 #define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3a4

+
+/* SPECIAL CASE: PLLM, PLLC and PLLX use different-sized fields here */
+#define PLLCX_BASE_DIVP_MASK		(0xfU << PLL_BASE_DIVP_SHIFT)
+#define PLLM_BASE_DIVP_MASK		(0x1U << PLL_BASE_DIVP_SHIFT)
+#define PLLCMX_BASE_DIVN_MASK		(0xffU << PLL_BASE_DIVN_SHIFT)
+#define PLLCMX_BASE_DIVM_MASK		(0xffU << PLL_BASE_DIVM_SHIFT)
+enum {
+	MC_EMEM_CFG_SIZE_MB_SHIFT = 0,
+	MC_EMEM_CFG_SIZE_MB_MASK = 0x3fff,
+
+	MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27,
+	MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27,
+
+	MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED = 1,
+
+	MC_TIMING_CONTROL_TIMING_UPDATE = 1,
+};
+
+//EMC
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19c
+#define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ (1 << 16)
+
+//PLLM
+#define PLLM_BASE 0x90
+#define PLLM_MISC1_BASE 0x98
+#define PLLM_MISC2_BASE 0x9c
+#define PLLM_MISC1_SETUP_SHIFT			0
+#define PLLM_MISC1_PD_LSHIFT_PH45_SHIFT		28
+#define PLLM_MISC1_PD_LSHIFT_PH90_SHIFT		29
+#define PLLM_MISC1_PD_LSHIFT_PH135_SHIFT	30
+#define PLLM_MISC2_KCP_SHIFT			1
+#define PLLM_MISC2_KVCO_SHIFT			0
+#define PLLM_OUT1_RSTN_RESET_DISABLE		(1 << 0)
+
+/* CLK_RST_CONTROLLER_PLL*_BASE_0 */
+#define PLL_BASE_BYPASS			(1U << 31)
+#define PLL_BASE_ENABLE			(1U << 30)
+#define PLL_BASE_REF_DIS		(1U << 29)
+#define PLL_BASE_OVRRIDE		(1U << 28)
+#define PLL_BASE_LOCK			(1U << 27)
+#define IO_STABILIZATION_DELAY (2)
+
+#define PLL_BASE_DIVP_SHIFT		20
+#define PLL_BASE_DIVP_MASK		(7U << PLL_BASE_DIVP_SHIFT)
+
+#define PLL_BASE_DIVN_SHIFT		8
+#define PLL_BASE_DIVN_MASK		(0x3ffU << PLL_BASE_DIVN_SHIFT)
+
+#define PLL_BASE_DIVM_SHIFT		0
+#define PLL_BASE_DIVM_MASK		(0x1f << PLL_BASE_DIVM_SHIFT)
+
+
 //Reset
 #define CLK_RST_CONTROLLER_RST_DEVICES_L 0x4
 #define CLK_RST_CONTROLLER_RST_DEVICES_H 0x8
@ -215,3 +273,5 @@ void clock_enable_i2c(u32 idx);
 void clock_enable_uart(u32 idx);
 void config_oscillators();
 int clock_uart_use_src_div(u32 idx, u32 baud);
+
+#endif
--- a/loader/clock_lp0.h
+++ b/loader/clock_lp0.h
@ -0,0 +1,550 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "types.h"
+#ifndef _TEGRA124_CLOCK_LP0_H_
+#define _TEGRA124_CLOCK_LP0_H_
+
+/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
+struct clk_rst_ctlr {
+	u32 rst_src;			/* _RST_SOURCE,             0x000 */
+	u32 rst_dev_l;			/* _RST_DEVICES_L,          0x004 */
+	u32 rst_dev_h;			/* _RST_DEVICES_H,          0x008 */
+	u32 rst_dev_u;			/* _RST_DEVICES_U,          0x00c */
+	u32 clk_out_enb_l;		/* _CLK_OUT_ENB_L,          0x010 */
+	u32 clk_out_enb_h;		/* _CLK_OUT_ENB_H,          0x014 */
+	u32 clk_out_enb_u;		/* _CLK_OUT_ENB_U,          0x018 */
+	u32 _rsv0;			/*                          0x01c */
+	u32 cclk_brst_pol;		/* _CCLK_BURST_POLICY,      0x020 */
+	u32 super_cclk_div;		/* _SUPER_CCLK_DIVIDER,     0x024 */
+	u32 sclk_brst_pol;		/* _SCLK_BURST_POLICY,      0x028 */
+	u32 super_sclk_div;		/* _SUPER_SCLK_DIVIDER,     0x02C */
+	u32 clk_sys_rate;		/* _CLK_SYSTEM_RATE,        0x030 */
+	u32 _rsv1[3];			/*                      0x034-03c */
+	u32 cop_clk_skip_plcy;		/* _COP_CLK_SKIP_POLICY,    0x040 */
+	u32 clk_mask_arm;		/* _CLK_MASK_ARM,           0x044 */
+	u32 misc_clk_enb;		/* _MISC_CLK_ENB,           0x048 */
+	u32 clk_cpu_cmplx;		/* _CLK_CPU_CMPLX,          0x04C */
+	u32 osc_ctrl;			/* _OSC_CTRL,               0x050 */
+	u32 pll_lfsr;			/* _PLL_LFSR,               0x054 */
+	u32 osc_freq_det;		/* _OSC_FREQ_DET,           0x058 */
+	u32 osc_freq_det_stat;		/* _OSC_FREQ_DET_STATUS,    0x05C */
+	u32 _rsv2[8];			/*                      0x060-07C */
+	u32 pllc_base;			/* _PLLC_BASE,              0x080 */
+	u32 pllc_out;			/* _PLLC_OUT,               0x084 */
+	u32 pllc_misc2;			/* _PLLC_MISC2,             0x088 */
+	u32 pllc_misc;			/* _PLLC_MISC,              0x08c */
+	u32 pllm_base;			/* _PLLM_BASE,              0x090 */
+	u32 pllm_out;			/* _PLLM_OUT,               0x094 */
+	u32 pllm_misc1;			/* _PLLM_MISC1,             0x098 */
+	u32 pllm_misc2;			/* _PLLM_MISC2,             0x09c */
+	u32 pllp_base;			/* _PLLP_BASE,              0x0a0 */
+	u32 pllp_outa;			/* _PLLP_OUTA,              0x0a4 */
+	u32 pllp_outb;			/* _PLLP_OUTB,              0x0a8 */
+	u32 pllp_misc;			/* _PLLP_MISC,              0x0ac */
+	u32 plla_base;			/* _PLLA_BASE,              0x0b0 */
+	u32 plla_out;			/* _PLLA_OUT,               0x0b4 */
+	u32 _rsv3;			/*                          0x0b8 */
+	u32 plla_misc;			/* _PLLA_MISC,              0x0bc */
+	u32 pllu_base;			/* _PLLU_BASE,              0x0c0 */
+	u32 _rsv4[2];			/*                      0x0c4-0c8 */
+	u32 pllu_misc;			/* _PLLU_MISC,              0x0cc */
+	u32 plld_base;			/* _PLLD_BASE,              0x0d0 */
+	u32 _rsv5[2];			/*                      0x0d4-0d8 */
+	u32 plld_misc;			/* _PLLD_MISC,              0x0dc */
+	u32 pllx_base;			/* _PLLX_BASE,              0x0e0 */
+	u32 pllx_misc;			/* _PLLX_MISC,              0x0e4 */
+	u32 plle_base;			/* _PLLE_BASE,              0x0e8 */
+	u32 plle_misc;			/* _PLLE_MISC,              0x0ec */
+	u32 plls_base;			/* _PLLS_BASE,              0x0f0 */
+	u32 plls_misc;			/* _PLLS_MISC,              0x0f4 */
+	u32 _rsv6[2];			/*                      0x0f8-0fc */
+        u32 clk_src_i2s1;		/* _CLK_SOURCE_I2S1,        0x100 */
+        u32 clk_src_i2s2;		/* _CLK_SOURCE_I2S2,        0x104 */
+        u32 clk_src_spdif_out;		/* _CLK_SOURCE_SPDIF_OUT,   0x108 */
+        u32 clk_src_spdif_in;		/* _CLK_SOURCE_SPDIF_IN,    0x10c */
+        u32 clk_src_pwm;		/* _CLK_SOURCE_PWM,         0x110 */
+        u32 _rsv7;			/*                          0x114 */
+        u32 clk_src_sbc2;		/* _CLK_SOURCE_SBC2,        0x118 */
+        u32 clk_src_sbc3;		/* _CLK_SOURCE_SBC3,        0x11c */
+        u32 _rsv8;			/*                          0x120 */
+        u32 clk_src_i2c1;		/* _CLK_SOURCE_I2C1,        0x124 */
+        u32 clk_src_i2c5;		/* _CLK_SOURCE_I2C5,        0x128 */
+        u32 _rsv9[2];			/*                      0x12c-130 */
+        u32 clk_src_sbc1;		/* _CLK_SOURCE_SBC1,        0x134 */
+        u32 clk_src_disp1;		/* _CLK_SOURCE_DISP1,       0x138 */
+        u32 clk_src_disp2;		/* _CLK_SOURCE_DISP2,       0x13c */
+        u32 _rsv10[2];			/*                      0x140-144 */
+        u32 clk_src_vi;			/* _CLK_SOURCE_VI,          0x148 */
+        u32 _rsv11;			/*                          0x14c */
+        u32 clk_src_sdmmc1;		/* _CLK_SOURCE_SDMMC1,      0x150 */
+        u32 clk_src_sdmmc2;		/* _CLK_SOURCE_SDMMC2,      0x154 */
+        u32 clk_src_g3d;		/* _CLK_SOURCE_G3D,         0x158 */
+        u32 clk_src_g2d;		/* _CLK_SOURCE_G2D,         0x15c */
+        u32 clk_src_ndflash;		/* _CLK_SOURCE_NDFLASH,     0x160 */
+        u32 clk_src_sdmmc4;		/* _CLK_SOURCE_SDMMC4,      0x164 */
+        u32 clk_src_vfir;		/* _CLK_SOURCE_VFIR,        0x168 */
+        u32 clk_src_epp;		/* _CLK_SOURCE_EPP,         0x16c */
+        u32 clk_src_mpe;		/* _CLK_SOURCE_MPE,         0x170 */
+        u32 clk_src_hsi;		/* _CLK_SOURCE_HSI,         0x174 */
+        u32 clk_src_uarta;		/* _CLK_SOURCE_UARTA,       0x178 */
+        u32 clk_src_uartb;		/* _CLK_SOURCE_UARTB,       0x17c */
+        u32 clk_src_host1x;		/* _CLK_SOURCE_HOST1X,      0x180 */
+        u32 _rsv12[2];			/*                      0x184-188 */
+        u32 clk_src_hdmi;		/* _CLK_SOURCE_HDMI,        0x18c */
+        u32 _rsv13[2];			/*                      0x190-194 */
+        u32 clk_src_i2c2;		/* _CLK_SOURCE_I2C2,        0x198 */
+        u32 clk_src_emc;		/* _CLK_SOURCE_EMC,         0x19c */
+        u32 clk_src_uartc;		/* _CLK_SOURCE_UARTC,       0x1a0 */
+	u32 _rsv14;			/*                          0x1a4 */
+        u32 clk_src_vi_sensor;		/* _CLK_SOURCE_VI_SENSOR,   0x1a8 */
+        u32 _rsv15[2];			/*                      0x1ac-1b0 */
+        u32 clk_src_sbc4;		/* _CLK_SOURCE_SBC4,        0x1b4 */
+        u32 clk_src_i2c3;		/* _CLK_SOURCE_I2C3,        0x1b8 */
+        u32 clk_src_sdmmc3;		/* _CLK_SOURCE_SDMMC3,      0x1bc */
+        u32 clk_src_uartd;		/* _CLK_SOURCE_UARTD,       0x1c0 */
+        u32 clk_src_uarte;		/* _CLK_SOURCE_UARTE,       0x1c4 */
+        u32 clk_src_vde;		/* _CLK_SOURCE_VDE,         0x1c8 */
+        u32 clk_src_owr;		/* _CLK_SOURCE_OWR,         0x1cc */
+        u32 clk_src_nor;		/* _CLK_SOURCE_NOR,         0x1d0 */
+        u32 clk_src_csite;		/* _CLK_SOURCE_CSITE,       0x1d4 */
+        u32 clk_src_i2s0;		/* _CLK_SOURCE_I2S0,        0x1d8 */
+        u32 clk_src_dtv;		/* _CLK_SOURCE_DTV,         0x1dc */
+        u32 _rsv16[4];			/*                      0x1e0-1ec */
+        u32 clk_src_msenc;		/* _CLK_SOURCE_MSENC,       0x1f0 */
+        u32 clk_src_tsec;		/* _CLK_SOURCE_TSEC,        0x1f4 */
+	u32 _rsv17;			/*                          0x1f8 */
+        u32 clk_src_osc;		/* _CLK_SOURCE_OSC,         0x1fc */
+	u32 _rsv18[32];			/*                      0x200-27c */
+	u32 clk_out_enb_x;		/* _CLK_OUT_ENB_X_0,        0x280 */
+	u32 clk_enb_x_set;		/* _CLK_ENB_X_SET_0,        0x284 */
+	u32 clk_enb_x_clr;		/* _CLK_ENB_X_CLR_0,        0x288 */
+	u32 rst_devices_x;		/* _RST_DEVICES_X_0,        0x28c */
+	u32 rst_dev_x_set;		/* _RST_DEV_X_SET_0,        0x290 */
+	u32 rst_dev_x_clr;		/* _RST_DEV_X_CLR_0,        0x294 */
+	u32 _rsv19[23];			/*                      0x298-2f0 */
+	u32 dfll_base;			/* _DFLL_BASE_0,            0x2f4 */
+	u32 _rsv20[2];			/*                      0x2f8-2fc */
+	u32 rst_dev_l_set;		/* _RST_DEV_L_SET           0x300 */
+	u32 rst_dev_l_clr;		/* _RST_DEV_L_CLR           0x304 */
+	u32 rst_dev_h_set;		/* _RST_DEV_H_SET           0x308 */
+	u32 rst_dev_h_clr;		/* _RST_DEV_H_CLR           0x30c */
+	u32 rst_dev_u_set;		/* _RST_DEV_U_SET           0x310 */
+	u32 rst_dev_u_clr;		/* _RST_DEV_U_CLR           0x314 */
+	u32 _rsv21[2];			/*                      0x318-31c */
+	u32 clk_enb_l_set;		/* _CLK_ENB_L_SET           0x320 */
+	u32 clk_enb_l_clr;		/* _CLK_ENB_L_CLR           0x324 */
+	u32 clk_enb_h_set;		/* _CLK_ENB_H_SET           0x328 */
+	u32 clk_enb_h_clr;		/* _CLK_ENB_H_CLR           0x32c */
+	u32 clk_enb_u_set;		/* _CLK_ENB_U_SET           0x330 */
+	u32 clk_enb_u_clk;		/* _CLK_ENB_U_CLR           0x334 */
+	u32 _rsv22;			/*                          0x338 */
+	u32 ccplex_pg_sm_ovrd;		/* _CCPLEX_PG_SM_OVRD,      0x33c */
+	u32 rst_cpu_cmplx_set;		/* _RST_CPU_CMPLX_SET,      0x340 */
+	u32 rst_cpu_cmplx_clr;		/* _RST_CPU_CMPLX_CLR,      0x344 */
+	u32 clk_cpu_cmplx_set;		/* _CLK_CPU_CMPLX_SET,      0x348 */
+	u32 clk_cpu_cmplx_clr;		/* _CLK_CPU_CMPLX_SET,      0x34c */
+	u32 _rsv23[2];			/*                      0x350-354 */
+	u32 rst_dev_v;			/* _RST_DEVICES_V,          0x358 */
+	u32 rst_dev_w;			/* _RST_DEVICES_W,          0x35c */
+	u32 clk_out_enb_v;		/* _CLK_OUT_ENB_V,          0x360 */
+	u32 clk_out_enb_w;		/* _CLK_OUT_ENB_W,          0x364 */
+	u32 cclkg_brst_pol;		/* _CCLKG_BURST_POLICY,     0x368 */
+	u32 super_cclkg_div;		/* _SUPER_CCLKG_DIVIDER,    0x36c */
+	u32 cclklp_brst_pol;		/* _CCLKLP_BURST_POLICY,    0x370 */
+	u32 super_cclkp_div;		/* _SUPER_CCLKLP_DIVIDER,   0x374 */
+	u32 clk_cpug_cmplx;		/* _CLK_CPUG_CMPLX,         0x378 */
+	u32 clk_cpulp_cmplx;		/* _CLK_CPULP_CMPLX,        0x37c */
+	u32 cpu_softrst_ctrl;		/* _CPU_SOFTRST_CTRL,       0x380 */
+	u32 cpu_softrst_ctrl1;		/* _CPU_SOFTRST_CTRL1,      0x384 */
+	u32 cpu_softrst_ctrl2;		/* _CPU_SOFTRST_CTRL2,      0x388 */
+	u32 _rsv24[9];			/*                      0x38c-3ac */
+	u32 clk_src_g3d2;		/* _CLK_SOURCE_G3D2,        0x3b0 */
+	u32 clk_src_mselect;		/* _CLK_SOURCE_MSELECT,     0x3b4 */
+	u32 clk_src_tsensor;		/* _CLK_SOURCE_TSENSOR,     0x3b8 */
+	u32 clk_src_i2s3;		/* _CLK_SOURCE_I2S3,        0x3bc */
+	u32 clk_src_i2s4;		/* _CLK_SOURCE_I2S4,        0x3c0 */
+	u32 clk_src_i2c4;		/* _CLK_SOURCE_I2C4,        0x3c4 */
+	u32 clk_src_sbc5;		/* _CLK_SOURCE_SBC5,        0x3c8 */
+	u32 clk_src_sbc6;		/* _CLK_SOURCE_SBC6,        0x3cc */
+	u32 clk_src_audio;		/* _CLK_SOURCE_AUDIO,       0x3d0 */
+	u32 _rsv25;			/*                          0x3d4 */
+	u32 clk_src_dam0;		/* _CLK_SOURCE_DAM0,        0x3d8 */
+	u32 clk_src_dam1;		/* _CLK_SOURCE_DAM1,        0x3dc */
+	u32 clk_src_dam2;		/* _CLK_SOURCE_DAM2,        0x3e0 */
+	u32 clk_src_hda2codec_2x;	/* _CLK_SOURCE_HDA2CODEC_2X,0x3e4 */
+	u32 clk_src_actmon;		/* _CLK_SOURCE_ACTMON,      0x3e8 */
+	u32 clk_src_extperiph1;		/* _CLK_SOURCE_EXTPERIPH1,  0x3ec */
+	u32 clk_src_extperiph2;		/* _CLK_SOURCE_EXTPERIPH2,  0x3f0 */
+	u32 clk_src_extperiph3;		/* _CLK_SOURCE_EXTPERIPH3,  0x3f4 */
+	u32 clk_src_nand_speed;		/* _CLK_SOURCE_NAND_SPEED,  0x3f8 */
+	u32 clk_src_i2c_slow;		/* _CLK_SOURCE_I2C_SLOW,    0x3fc */
+	u32 clk_src_sys;		/* _CLK_SOURCE_SYS,         0x400 */
+	u32 _rsv26[4];			/*                      0x404-410 */
+	u32 clk_src_sor;		/* _CLK_SOURCE_SOR_0,       0x414 */
+	u32 _rsv261[2];			/*                      0x404-410 */
+	u32 clk_src_sata_oob;		/* _CLK_SOURCE_SATA_OOB,    0x420 */
+	u32 clk_src_sata;		/* _CLK_SOURCE_SATA,        0x424 */
+	u32 clk_src_hda;		/* _CLK_SOURCE_HDA,         0x428 */
+	u32 _rsv27;			/*                          0x42c */
+	u32 rst_dev_v_set;		/* _RST_DEV_V_SET,          0x430 */
+	u32 rst_dev_v_clr;		/* _RST_DEV_V_CLR,          0x434 */
+	u32 rst_dev_w_set;		/* _RST_DEV_W_SET,          0x438 */
+	u32 rst_dev_w_clr;		/* _RST_DEV_W_CLR,          0x43c */
+	u32 clk_enb_v_set;		/* _CLK_ENB_V_SET,          0x440 */
+	u32 clk_enb_v_clr;		/* _CLK_ENB_V_CLR,          0x444 */
+	u32 clk_enb_w_set;		/* _CLK_ENB_W_SET,          0x448 */
+	u32 clk_enb_w_clr;		/* _CLK_ENB_W_CLR,          0x44c */
+	u32 rst_cpug_cmplx_set;		/* _RST_CPUG_CMPLX_SET,     0x450 */
+	u32 rst_cpug_cmplx_clr;		/* _RST_CPUG_CMPLX_CLR,     0x454 */
+	u32 rst_cpulp_cmplx_set;	/* _RST_CPULP_CMPLX_SET,    0x458 */
+	u32 rst_cpulp_cmplx_clr;	/* _RST_CPULP_CMPLX_CLR,    0x45C */
+	u32 clk_cpug_cmplx_set;		/* _CLK_CPUG_CMPLX_SET,     0x460 */
+	u32 clk_cpug_cmplx_clr;		/* _CLK_CPUG_CMPLX_CLR,     0x464 */
+	u32 clk_cpulp_cmplx_set;	/* _CLK_CPULP_CMPLX_SET,    0x468 */
+	u32 clk_cpulp_cmplx_clr;	/* _CLK_CPULP_CMPLX_CLR,    0x46c */
+	u32 cpu_cmplx_status;		/* _CPU_CMPLX_STATUS,       0x470 */
+	u32 _rsv28;			/*                          0x474 */
+	u32 intstatus;			/* _INTSTATUS,              0x478 */
+	u32 intmask;			/* _INTMASK,                0x47c */
+	u32 utmip_pll_cfg0;		/* _UTMIP_PLL_CFG0,         0x480 */
+	u32 utmip_pll_cfg1;		/* _UTMIP_PLL_CFG1,         0x484 */
+	u32 utmip_pll_cfg2;		/* _UTMIP_PLL_CFG2,         0x488 */
+	u32 plle_aux;			/* _PLLE_AUX,               0x48c */
+	u32 sata_pll_cfg0;		/* _SATA_PLL_CFG0,          0x490 */
+	u32 sata_pll_cfg1;		/* _SATA_PLL_CFG1,          0x494 */
+	u32 pcie_pll_cfg0;		/* _PCIE_PLL_CFG0,          0x498 */
+	u32 prog_audio_dly_clk;		/* _PROG_AUDIO_DLY_CLK,     0x49c */
+	u32 audio_sync_clk_i2s0;	/* _AUDIO_SYNC_CLK_I2S0,    0x4a0 */
+	u32 audio_sync_clk_i2s1;	/* _AUDIO_SYNC_CLK_I2S1,    0x4a4 */
+	u32 audio_sync_clk_i2s2;	/* _AUDIO_SYNC_CLK_I2S2,    0x4a8 */
+	u32 audio_sync_clk_i2s3;	/* _AUDIO_SYNC_CLK_I2S3,    0x4ac */
+	u32 audio_sync_clk_i2s4;	/* _AUDIO_SYNC_CLK_I2S4,    0x4b0 */
+	u32 audio_sync_clk_spdif;	/* _AUDIO_SYNC_CLK_SPDIF,   0x4b4 */
+	u32 plld2_base;			/* _PLLD2_BASE,             0x4b8 */
+	u32 plld2_misc;			/* _PLLD2_MISC,             0x4bc */
+	u32 utmip_pll_cfg3;		/* _UTMIP_PLL_CFG3,         0x4c0 */
+	u32 pllrefe_base;		/* _PLLREFE_BASE,           0x4c4 */
+	u32 pllrefe_misc;		/* _PLLREFE_MISC,           0x4c8 */
+	u32 _rsv29[7];			/*                      0x4cc-4e4 */
+	u32 pllc2_base;			/* _PLLC2_BASE,             0x4e8 */
+	u32 pllc2_misc0;		/* _PLLC2_MISC_0,           0x4ec */
+	u32 pllc2_misc1;		/* _PLLC2_MISC_1,           0x4f0 */
+	u32 pllc2_misc2;		/* _PLLC2_MISC_2,           0x4f4 */
+	u32 pllc2_misc3;		/* _PLLC2_MISC_3,           0x4f8 */
+	u32 pllc3_base;			/* _PLLC3_BASE,             0x4fc */
+	u32 pllc3_misc0;		/* _PLLC3_MISC_0,           0x500 */
+	u32 pllc3_misc1;		/* _PLLC3_MISC_1,           0x504 */
+	u32 pllc3_misc2;		/* _PLLC3_MISC_2,           0x508 */
+	u32 pllc3_misc3;		/* _PLLC3_MISC_3,           0x50c */
+	u32 pllx_misc1;			/* _PLLX_MISC_1,            0x510 */
+	u32 pllx_misc2;			/* _PLLX_MISC_2,            0x514 */
+	u32 pllx_misc3;			/* _PLLX_MISC_3,            0x518 */
+	u32 xusbio_pll_cfg0;		/* _XUSBIO_PLL_CFG0,        0x51c */
+	u32 xusbio_pll_cfg1;		/* _XUSBIO_PLL_CFG1,        0x520 */
+	u32 plle_aux1;			/* _PLLE_AUX1,              0x524 */
+	u32 pllp_reshift;		/* _PLLP_RESHIFT,           0x528 */
+	u32 utmipll_hw_pwrdn_cfg0;	/* _UTMIPLL_HW_PWRDN_CFG0,  0x52c */
+	u32 pllu_hw_pwrdn_cfg0;		/* _PLLU_HW_PWRDN_CFG0,     0x530 */
+	u32 xusb_pll_cfg0;		/* _XUSB_PLL_CFG0,          0x534 */
+	u32 _rsv30;			/*                          0x538 */
+	u32 clk_cpu_misc;		/* _CLK_CPU_MISC,           0x53c */
+	u32 clk_cpug_misc;		/* _CLK_CPUG_MISC,          0x540 */
+	u32 clk_cpulp_misc;		/* _CLK_CPULP_MISC,         0x544 */
+	u32 pllx_hw_ctrl_cfg;		/* _PLLX_HW_CTRL_CFG,       0x548 */
+	u32 pllx_sw_ramp_cfg;		/* _PLLX_SW_RAMP_CFG,       0x54c */
+	u32 pllx_hw_ctrl_status;	/* _PLLX_HW_CTRL_STATUS,    0x550 */
+	u32 _rsv31;			/*                          0x554 */
+	u32 super_gr3d_clk_div;		/* _SUPER_GR3D_CLK_DIVIDER, 0x558 */
+	u32 spare_reg0;			/* _SPARE_REG0,             0x55c */
+	u32 _rsv32[4];                  /*                    0x560-0x56c */
+	u32 plld2_ss_cfg;               /* _PLLD2_SS_CFG            0x570 */
+	u32 _rsv32_1[7];		/*                      0x574-58c */
+	u32 plldp_base;			/* _PLLDP_BASE,             0x590 */
+	u32 plldp_misc;			/* _PLLDP_MISC,             0x594 */
+	u32 plldp_ss_cfg;		/* _PLLDP_SS_CFG,           0x598 */
+	u32 _rsrv32_2[25];
+	u32 clk_src_xusb_core_host;	/* _CLK_SOURCE_XUSB_CORE_HOST 0x600 */
+	u32 clk_src_xusb_falcon;	/* _CLK_SOURCE_XUSB_FALCON  0x604 */
+	u32 clk_src_xusb_fs;		/* _CLK_SOURCE_XUSB_FS      0x608 */
+	u32 clk_src_xusb_core_dev;	/* _CLK_SOURCE_XUSB_CORE_DEV 0x60c */
+	u32 clk_src_xusb_ss;		/* _CLK_SOURCE_XUSB_SS      0x610 */
+	u32 clk_src_cilab;		/* _CLK_SOURCE_CILAB        0x614 */
+	u32 clk_src_cilcd;		/* _CLK_SOURCE_CILCD        0x618 */
+	u32 clk_src_cile;		/* _CLK_SOURCE_CILE         0x61c */
+	u32 clk_src_dsia_lp;		/* _CLK_SOURCE_DSIA_LP      0x620 */
+	u32 clk_src_dsib_lp;		/* _CLK_SOURCE_DSIB_LP      0x624 */
+	u32 clk_src_entropy;		/* _CLK_SOURCE_ENTROPY      0x628 */
+	u32 clk_src_dvfs_ref;		/* _CLK_SOURCE_DVFS_REF     0x62c */
+	u32 clk_src_dvfs_soc;		/* _CLK_SOURCE_DVFS_SOC     0x630 */
+	u32 clk_src_traceclkin;		/* _CLK_SOURCE_TRACECLKIN   0x634 */
+	u32 clk_src_adx0;		/* _CLK_SOURCE_ADX0         0x638 */
+	u32 clk_src_amx0;		/* _CLK_SOURCE_AMX0         0x63c */
+	u32 clk_src_emc_latency;	/* _CLK_SOURCE_EMC_LATENCY  0x640 */
+	u32 clk_src_soc_therm;		/* _CLK_SOURCE_SOC_THERM    0x644 */
+};
+
+#define TEGRA_DEV_L			0
+#define TEGRA_DEV_H			1
+#define TEGRA_DEV_U			2
+#define TEGRA_DEV_V			0
+#define TEGRA_DEV_W			1
+
+#define SIMPLE_PLLX		(CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
+
+/* Bits to enable/reset modules */
+#define CLK_ENB_CPU			(1 << 0)
+#define SWR_TRIG_SYS_RST		(1 << 2)
+#define SWR_CSITE_RST			(1 << 9)
+#define CLK_ENB_CSITE			(1 << 9)
+
+/* CRC_SUPER_CCLK_DIVIDER_0 0x24 */
+#define SUPER_CDIV_ENB_ENABLE		(1 << 31)
+
+/* CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48 */
+#define EN_PPSB_STOPCLK			(1 << 0)
+
+/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 (0x4C) */
+#define CPU3_CLK_STP_SHIFT		11
+#define CPU2_CLK_STP_SHIFT		10
+#define CPU1_CLK_STP_SHIFT		9
+#define CPU0_CLK_STP_SHIFT		8
+#define CPU0_CLK_STP_MASK		(1U << CPU0_CLK_STP_SHIFT)
+
+/* CRC_OSC_CTRL_0 0x50 */
+#define OSC_FREQ_SHIFT			28
+#define OSC_FREQ_MASK			(0xf << OSC_FREQ_SHIFT)
+#define OSC_PREDIV_SHIFT		26
+#define OSC_PREDIV_MASK			(0x3 << OSC_PREDIV_SHIFT)
+#define OSC_XOFS_SHIFT			4
+#define OSC_XOFS_MASK			(0x3F << OSC_XOFS_SHIFT)
+#define OSC_DRIVE_STRENGTH		7
+#define OSC_XOBP			(1 << 1)
+#define OSC_XOE				(1 << 0)
+
+enum {
+	OSC_FREQ_12	= 8,	/* 12.0MHz */
+	OSC_FREQ_13	= 0,	/* 13.0MHz */
+	OSC_FREQ_16P8	= 1,	/* 16.8MHz */
+	OSC_FREQ_19P2	= 4,	/* 19.2MHz */
+	OSC_FREQ_26	= 12,	/* 26.0MHz */
+	OSC_FREQ_38P4	= 5,	/* 38.4MHz */
+	OSC_FREQ_48	= 9,	/* 48.0MHz */
+};
+
+/* CLK_RST_CONTROLLER_PLL*_BASE_0 */
+#define PLL_BASE_BYPASS			(1U << 31)
+#define PLL_BASE_ENABLE			(1U << 30)
+#define PLL_BASE_REF_DIS		(1U << 29)
+#define PLL_BASE_OVRRIDE		(1U << 28)
+#define PLL_BASE_LOCK			(1U << 27)
+
+#define PLL_BASE_DIVP_SHIFT		20
+#define PLL_BASE_DIVP_MASK		(7U << PLL_BASE_DIVP_SHIFT)
+
+#define PLL_BASE_DIVN_SHIFT		8
+#define PLL_BASE_DIVN_MASK		(0x3ffU << PLL_BASE_DIVN_SHIFT)
+
+#define PLL_BASE_DIVM_SHIFT		0
+#define PLL_BASE_DIVM_MASK		(0x1f << PLL_BASE_DIVM_SHIFT)
+
+/* SPECIAL CASE: PLLM, PLLC and PLLX use different-sized fields here */
+#define PLLCX_BASE_DIVP_MASK		(0xfU << PLL_BASE_DIVP_SHIFT)
+#define PLLM_BASE_DIVP_MASK		(0x1U << PLL_BASE_DIVP_SHIFT)
+#define PLLCMX_BASE_DIVN_MASK		(0xffU << PLL_BASE_DIVN_SHIFT)
+#define PLLCMX_BASE_DIVM_MASK		(0xffU << PLL_BASE_DIVM_SHIFT)
+
+/* PLLM specific registers */
+#define PLLM_MISC1_SETUP_SHIFT			0
+#define PLLM_MISC1_PD_LSHIFT_PH45_SHIFT		28
+#define PLLM_MISC1_PD_LSHIFT_PH90_SHIFT		29
+#define PLLM_MISC1_PD_LSHIFT_PH135_SHIFT	30
+#define PLLM_MISC2_KCP_SHIFT			1
+#define PLLM_MISC2_KVCO_SHIFT			0
+#define PLLM_OUT1_RSTN_RESET_DISABLE		(1 << 0)
+
+/* Generic, indiscriminate divisor mask. May catch some innocent bystander bits
+ * on the side that we don't particularly care about. */
+#define PLL_BASE_DIV_MASK		(0xffffff)
+
+/* CLK_RST_CONTROLLER_PLL*_OUT*_0 */
+#define PLL_OUT_RSTN			(1 << 0)
+#define PLL_OUT_CLKEN			(1 << 1)
+#define PLL_OUT_OVR			(1 << 2)
+
+#define PLL_OUT_RATIO_SHIFT		8
+#define PLL_OUT_RATIO_MASK		(0xffU << PLL_OUT_RATIO_SHIFT)
+
+#define PLL_OUT1_SHIFT			0
+#define PLL_OUT2_SHIFT			16
+#define PLL_OUT3_SHIFT			0
+#define PLL_OUT4_SHIFT			16
+
+/* CLK_RST_CONTROLLER_PLL*_MISC_0 */
+#define PLL_MISC_DCCON			(1 << 20)
+
+#define PLL_MISC_CPCON_SHIFT		8
+#define PLL_MISC_CPCON_MASK		(0xfU << PLL_MISC_CPCON_SHIFT)
+
+#define PLL_MISC_LFCON_SHIFT		4
+#define PLL_MISC_LFCON_MASK		(0xfU << PLL_MISC_LFCON_SHIFT)
+
+/* This bit is different all over the place. Oh joy... */
+#define PLLDPD2_MISC_LOCK_ENABLE	(1 << 30)
+#define PLLC_MISC_LOCK_ENABLE		(1 << 24)
+#define PLLUD_MISC_LOCK_ENABLE		(1 << 22)
+#define PLLD_MISC_CLK_ENABLE		(1 << 30)
+#define PLLPAXS_MISC_LOCK_ENABLE	(1 << 18)
+#define PLLE_MISC_LOCK_ENABLE		(1 << 9)
+
+#define PLLU_MISC_VCO_FREQ		(1 << 20)
+
+/* PLLX_BASE_0 0xe0 */
+#define PLLX_BASE_PLLX_ENABLE		(1 << 30)
+
+/* CLK_RST_CONTROLLER_PLLX_MISC_3 */
+#define PLLX_IDDQ_SHIFT			3
+#define PLLX_IDDQ_MASK			(1U << PLLX_IDDQ_SHIFT)
+
+#define CLK_DIVISOR_MASK		(0xffff)
+
+#define CLK_SOURCE_SHIFT		29
+#define CLK_SOURCE_MASK			(0x7 << CLK_SOURCE_SHIFT)
+
+#define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ (1 << 16)
+
+#define CLK_UART_DIV_OVERRIDE		(1 << 24)
+
+/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
+#define SCLK_SYS_STATE_SHIFT		28U
+#define SCLK_SYS_STATE_MASK		(15U << SCLK_SYS_STATE_SHIFT)
+enum {
+	SCLK_SYS_STATE_STDBY,
+	SCLK_SYS_STATE_IDLE,
+	SCLK_SYS_STATE_RUN,
+	SCLK_SYS_STATE_IRQ = 4U,
+	SCLK_SYS_STATE_FIQ = 8U,
+};
+#define SCLK_COP_FIQ_MASK		(1 << 27)
+#define SCLK_CPU_FIQ_MASK		(1 << 26)
+#define SCLK_COP_IRQ_MASK		(1 << 25)
+#define SCLK_CPU_IRQ_MASK		(1 << 24)
+
+#define SCLK_FIQ_SHIFT			12
+#define SCLK_FIQ_MASK			(7 << SCLK_FIQ_SHIFT)
+#define SCLK_IRQ_SHIFT			8
+#define SCLK_IRQ_MASK			(7 << SCLK_FIQ_SHIFT)
+#define SCLK_RUN_SHIFT			4
+#define SCLK_RUN_MASK			(7 << SCLK_FIQ_SHIFT)
+#define SCLK_IDLE_SHIFT			0
+#define SCLK_IDLE_MASK			(7 << SCLK_FIQ_SHIFT)
+enum {
+	SCLK_SOURCE_CLKM,
+	SCLK_SOURCE_PLLC_OUT1,
+	SCLK_SOURCE_PLLP_OUT4,
+	SCLK_SOURCE_PLLP_OUT3,
+	SCLK_SOURCE_PLLP_OUT2,
+	SCLK_SOURCE_PLLC_OUT0,
+	SCLK_SOURCE_CLKS,
+	SCLK_SOURCE_PLLM_OUT1,
+};
+
+/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER 0x2c */
+#define SCLK_DIV_ENB			(1 << 31)
+#define SCLK_DIVIDEND_SHIFT		8
+#define SCLK_DIVIDEND_MASK		(0xff << SCLK_DIVIDEND_SHIFT)
+#define SCLK_DIVISOR_SHIFT		0
+#define SCLK_DIVISOR_MASK		(0xff << SCLK_DIVISOR_SHIFT)
+
+/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */
+#define HCLK_DISABLE			(1 << 7)
+#define HCLK_DIVISOR_SHIFT		4
+#define HCLK_DIVISOR_MASK		(3 << AHB_RATE_SHIFT)
+#define PCLK_DISABLE			(1 << 3)
+#define PCLK_DIVISOR_SHIFT		0
+#define PCLK_DIVISOR_MASK		(3 << AHB_RATE_SHIFT)
+
+/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */
+#define MSELECT_CLK_SRC_PLLP_OUT0	(0 << 29)
+
+/* CRC_CLK_ENB_V_SET_0 0x440 */
+#define SET_CLK_ENB_CPUG_ENABLE		(1 << 0)
+#define SET_CLK_ENB_CPULP_ENABLE	(1 << 1)
+#define SET_CLK_ENB_MSELECT_ENABLE	(1 << 3)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */
+#define PLLU_POWERDOWN			(1 << 16)
+#define PLL_ENABLE_POWERDOWN		(1 << 14)
+#define PLL_ACTIVE_POWERDOWN		(1 << 12)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */
+#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN	(1 << 4)
+#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN	(1 << 2)
+#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN	(1 << 0)
+
+// CCLK_BRST_POL
+enum {
+	CRC_CCLK_BRST_POL_PLLX_OUT0 = 0x8,
+	CRC_CCLK_BRST_POL_CPU_STATE_RUN = 0x2
+};
+
+// SUPER_CCLK_DIVIDER
+enum {
+	CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB = 1 << 31
+};
+
+// CLK_CPU_CMPLX_CLR
+enum {
+	CRC_CLK_CLR_CPU0_STP = 0x1 << 8,
+	CRC_CLK_CLR_CPU1_STP = 0x1 << 9,
+	CRC_CLK_CLR_CPU2_STP = 0x1 << 10,
+	CRC_CLK_CLR_CPU3_STP = 0x1 << 11
+};
+
+// RST_CPUG_CMPLX_CLR
+enum {
+	CRC_RST_CPUG_CLR_CPU0 = 0x1 << 0,
+	CRC_RST_CPUG_CLR_CPU1 = 0x1 << 1,
+	CRC_RST_CPUG_CLR_CPU2 = 0x1 << 2,
+	CRC_RST_CPUG_CLR_CPU3 = 0x1 << 3,
+	CRC_RST_CPUG_CLR_DBG0 = 0x1 << 12,
+	CRC_RST_CPUG_CLR_DBG1 = 0x1 << 13,
+	CRC_RST_CPUG_CLR_DBG2 = 0x1 << 14,
+	CRC_RST_CPUG_CLR_DBG3 = 0x1 << 15,
+	CRC_RST_CPUG_CLR_CORE0 = 0x1 << 16,
+	CRC_RST_CPUG_CLR_CORE1 = 0x1 << 17,
+	CRC_RST_CPUG_CLR_CORE2 = 0x1 << 18,
+	CRC_RST_CPUG_CLR_CORE3 = 0x1 << 19,
+	CRC_RST_CPUG_CLR_CX0 = 0x1 << 20,
+	CRC_RST_CPUG_CLR_CX1 = 0x1 << 21,
+	CRC_RST_CPUG_CLR_CX2 = 0x1 << 22,
+	CRC_RST_CPUG_CLR_CX3 = 0x1 << 23,
+	CRC_RST_CPUG_CLR_L2 = 0x1 << 24,
+	CRC_RST_CPUG_CLR_NONCPU = 0x1 << 29,
+	CRC_RST_CPUG_CLR_PDBG = 0x1 << 30,
+};
+
+// RST_CPULP_CMPLX_CLR
+enum {
+	CRC_RST_CPULP_CLR_CPU0 = 0x1 << 0,
+	CRC_RST_CPULP_CLR_DBG0 = 0x1 << 12,
+	CRC_RST_CPULP_CLR_CORE0 = 0x1 << 16,
+	CRC_RST_CPULP_CLR_CX0 = 0x1 << 20,
+	CRC_RST_CPULP_CLR_L2 = 0x1 << 24,
+	CRC_RST_CPULP_CLR_NONCPU = 0x1 << 29,
+	CRC_RST_CPULP_CLR_PDBG = 0x1 << 30,
+};
+
+#endif	/* _TEGRA124_CLK_RST_H_ */
+
--- a/loader/emc.h
+++ b/loader/emc.h
@ -0,0 +1,247 @@
+
+#ifndef _T124_EMC_H_
+#define _T124_EMC_H_
+
+#include "types.h"
+#define	EMC_INTSTATUS	0x0
+#define	EMC_INTMASK	0x4
+#define	EMC_DBG	0x8
+#define	EMC_CFG	0xC
+#define	EMC_ADR_CFG	0x10
+#define	EMC_REFCTRL	0x20
+#define	EMC_PIN	0x24
+#define	EMC_TIMING_CONTROL	0x28
+#define	EMC_RC	0x2C
+#define	EMC_RFC	0x30
+#define	EMC_RAS	0x34
+#define	EMC_RP	0x38
+#define	EMC_R2W	0x3C
+#define	EMC_W2R	0x40
+#define	EMC_R2P	0x44
+#define	EMC_W2P	0x48
+#define	EMC_RD_RCD	0x4C
+#define	EMC_WR_RCD	0x50
+#define	EMC_RRD	0x54
+#define	EMC_REXT	0x58
+#define	EMC_WDV	0x5C
+#define	EMC_QUSE	0x60
+#define	EMC_QRST	0x64
+#define	EMC_QSAFE	0x68
+#define	EMC_RDV	0x6C
+#define	EMC_REFRESH	0x70
+#define	EMC_BURST_REFRESH_NUM	0x74
+#define	EMC_PDEX2WR	0x78
+#define	EMC_PDEX2RD	0x7C
+#define	EMC_PCHG2PDEN	0x80
+#define	EMC_ACT2PDEN	0x84
+#define	EMC_AR2PDEN	0x88
+#define	EMC_RW2PDEN	0x8C
+#define	EMC_TXSR	0x90
+#define	EMC_TCKE	0x94
+#define	EMC_TFAW	0x98
+#define	EMC_TRPAB	0x9C
+#define	EMC_TCLKSTABLE	0xA0
+#define	EMC_TCLKSTOP	0xA4
+#define	EMC_TREFBW	0xA8
+#define	EMC_ODT_WRITE	0xB0
+#define	EMC_ODT_READ	0xB4
+#define	EMC_WEXT	0xB8
+#define	EMC_CTT	0xBC
+#define	EMC_RFC_SLR	0xC0
+#define	EMC_MRS_WAIT_CNT2	0xC4
+#define	EMC_MRS_WAIT_CNT	0xC8
+#define	EMC_MRS	0xCC
+#define	EMC_EMRS	0xD0
+#define	EMC_REF	0xD4
+#define	EMC_PRE	0xD8
+#define	EMC_NOP	0xDC
+#define	EMC_SELF_REF	0xE0
+#define	EMC_DPD	0xE4
+#define	EMC_MRW	0xE8
+#define	EMC_MRR	0xEC
+#define	EMC_CMDQ	0xF0
+#define	EMC_MC2EMCQ	0xF4
+#define	EMC_XM2DQSPADCTRL3	0xF8
+#define	EMC_FBIO_SPARE	0x100
+#define	EMC_FBIO_CFG5	0x104
+#define	EMC_FBIO_WRPTR_EQ_2	0x108
+#define	EMC_FBIO_CFG6	0x114
+#define	EMC_CFG_RSV	0x120
+#define EMC_ACPD_CONTROL 0x124
+#define	EMC_EMRS2	0x12C
+#define	EMC_EMRS3	0x130
+#define	EMC_MRW2	0x134
+#define	EMC_MRW3	0x138
+#define	EMC_MRW4	0x13C
+#define	EMC_CLKEN_OVERRIDE	0x140
+#define	EMC_R2R	0x144
+#define	EMC_W2W	0x148
+#define	EMC_EINPUT	0x14C
+#define	EMC_EINPUT_DURATION	0x150
+#define	EMC_PUTERM_EXTRA	0x154
+#define	EMC_TCKESR	0x158
+#define	EMC_TPD	0x15C
+#define	EMC_AUTO_CAL_CONFIG	0x2A4
+#define	EMC_AUTO_CAL_INTERVAL	0x2A8
+#define	EMC_AUTO_CAL_STATUS	0x2AC
+#define	EMC_REQ_CTRL	0x2B0
+#define	EMC_STATUS	0x2B4
+#define	EMC_CFG_2	0x2B8
+#define	EMC_CFG_DIG_DLL	0x2BC
+#define	EMC_CFG_DIG_DLL_PERIOD	0x2C0
+#define	EMC_DIG_DLL_STATUS	0x2C8
+#define	EMC_RDV_MASK	0x2CC
+#define	EMC_WDV_MASK	0x2D0
+#define	EMC_CTT_DURATION	0x2D8
+#define	EMC_CTT_TERM_CTRL	0x2DC
+#define	EMC_ZCAL_INTERVAL	0x2E0
+#define	EMC_ZCAL_WAIT_CNT	0x2E4
+#define	EMC_ZCAL_MRW_CMD	0x2E8
+#define	EMC_ZQ_CAL	0x2EC
+#define	EMC_XM2CMDPADCTRL	0x2F0
+#define	EMC_XM2CMDPADCTRL2	0x2F4
+#define	EMC_XM2DQSPADCTRL	0x2F8
+#define	EMC_XM2DQSPADCTRL2	0x2FC
+#define	EMC_XM2DQPADCTRL	0x300
+#define	EMC_XM2DQPADCTRL2	0x304
+#define	EMC_XM2CLKPADCTRL	0x308
+#define	EMC_XM2COMPPADCTRL	0x30C
+#define	EMC_XM2VTTGENPADCTRL	0x310
+#define	EMC_XM2VTTGENPADCTRL2	0x314
+#define	EMC_XM2VTTGENPADCTRL3	0x318
+#define	EMC_EMCPADEN	0x31C
+#define	EMC_XM2DQSPADCTRL4	0x320
+#define	EMC_SCRATCH0	0x324
+#define	EMC_DLL_XFORM_DQS0	0x328
+#define	EMC_DLL_XFORM_DQS1	0x32C
+#define	EMC_DLL_XFORM_DQS2	0x330
+#define	EMC_DLL_XFORM_DQS3	0x334
+#define	EMC_DLL_XFORM_DQS4	0x338
+#define	EMC_DLL_XFORM_DQS5	0x33C
+#define	EMC_DLL_XFORM_DQS6	0x340
+#define	EMC_DLL_XFORM_DQS7	0x344
+#define	EMC_DLL_XFORM_QUSE0	0x348
+#define	EMC_DLL_XFORM_QUSE1	0x34C
+#define	EMC_DLL_XFORM_QUSE2	0x350
+#define	EMC_DLL_XFORM_QUSE3	0x354
+#define	EMC_DLL_XFORM_QUSE4	0x358
+#define	EMC_DLL_XFORM_QUSE5	0x35C
+#define	EMC_DLL_XFORM_QUSE6	0x360
+#define	EMC_DLL_XFORM_QUSE7	0x364
+#define	EMC_DLL_XFORM_DQ0	0x368
+#define	EMC_DLL_XFORM_DQ1	0x36C
+#define	EMC_DLL_XFORM_DQ2	0x370
+#define	EMC_DLL_XFORM_DQ3	0x374
+#define	EMC_DLI_RX_TRIM0	0x378
+#define	EMC_DLI_RX_TRIM1	0x37C
+#define	EMC_DLI_RX_TRIM2	0x380
+#define	EMC_DLI_RX_TRIM3	0x384
+#define	EMC_DLI_RX_TRIM4	0x388
+#define	EMC_DLI_RX_TRIM5	0x38C
+#define	EMC_DLI_RX_TRIM6	0x390
+#define	EMC_DLI_RX_TRIM7	0x394
+#define	EMC_DLI_TX_TRIM0	0x398
+#define	EMC_DLI_TX_TRIM1	0x39C
+#define	EMC_DLI_TX_TRIM2	0x3A0
+#define	EMC_DLI_TX_TRIM3	0x3A4
+#define	EMC_DLI_TRIM_TXDQS0	0x3A8
+#define	EMC_DLI_TRIM_TXDQS1	0x3AC
+#define	EMC_DLI_TRIM_TXDQS2	0x3B0
+#define	EMC_DLI_TRIM_TXDQS3	0x3B4
+#define	EMC_DLI_TRIM_TXDQS4	0x3B8
+#define	EMC_DLI_TRIM_TXDQS5	0x3BC
+#define	EMC_DLI_TRIM_TXDQS6	0x3C0
+#define	EMC_DLI_TRIM_TXDQS7	0x3C4
+#define	EMC_STALL_THEN_EXE_AFTER_CLKCHANGE	0x3CC
+#define	EMC_AUTO_CAL_CLK_STATUS	0x3D4
+#define	EMC_SEL_DPD_CTRL	0x3D8
+#define	EMC_PRE_REFRESH_REQ_CNT	0x3DC
+#define	EMC_DYN_SELF_REF_CONTROL	0x3E0
+#define	EMC_TXSRDLL	0x3E4
+#define	EMC_CCFIFO_ADDR	0x3E8
+#define	EMC_CCFIFO_DATA	0x3EC
+#define	EMC_CCFIFO_STATUS	0x3F0
+#define	EMC_CDB_CNTL_1	0x3F4
+#define	EMC_CDB_CNTL_2	0x3F8
+#define	EMC_XM2CLKPADCTRL2	0x3FC
+#define	EMC_SWIZZLE_RANK0_BYTE_CFG	0x400
+#define	EMC_SWIZZLE_RANK0_BYTE0	0x404
+#define	EMC_SWIZZLE_RANK0_BYTE1	0x408
+#define	EMC_SWIZZLE_RANK0_BYTE2	0x40C
+#define	EMC_SWIZZLE_RANK0_BYTE3	0x410
+#define	EMC_SWIZZLE_RANK1_BYTE_CFG	0x414
+#define	EMC_SWIZZLE_RANK1_BYTE0	0x418
+#define	EMC_SWIZZLE_RANK1_BYTE1	0x41C
+#define	EMC_SWIZZLE_RANK1_BYTE2	0x420
+#define	EMC_SWIZZLE_RANK1_BYTE3	0x424
+#define	EMC_CA_TRAINING_START	0x428
+#define	EMC_CA_TRAINING_BUSY	0x42C
+#define	EMC_CA_TRAINING_CFG	0x430
+#define	EMC_CA_TRAINING_TIMING_CNTL1	0x434
+#define	EMC_CA_TRAINING_TIMING_CNTL2	0x438
+#define	EMC_CA_TRAINING_CA_LEAD_IN	0x43C
+#define	EMC_CA_TRAINING_CA	0x440
+#define	EMC_CA_TRAINING_CA_LEAD_OUT	0x444
+#define	EMC_CA_TRAINING_RESULT1	0x448
+#define	EMC_CA_TRAINING_RESULT2	0x44C
+#define	EMC_CA_TRAINING_RESULT3	0x450
+#define	EMC_CA_TRAINING_RESULT4	0x454
+#define	EMC_AUTO_CAL_CONFIG2	0x458
+#define	EMC_AUTO_CAL_CONFIG3	0x45C
+#define	EMC_AUTO_CAL_STATUS2	0x460
+#define	EMC_XM2CMDPADCTRL3	0x464
+#define	EMC_IBDLY	0x468
+#define	EMC_DLL_XFORM_ADDR0	0x46C
+#define	EMC_DLL_XFORM_ADDR1	0x470
+#define	EMC_DLL_XFORM_ADDR2	0x474
+#define	EMC_DLI_ADDR_TRIM	0x478
+#define	EMC_DSR_VTTGEN_DRV	0x47C
+#define	EMC_TXDSRVTTGEN	0x480
+#define	EMC_XM2CMDPADCTRL4	0x484
+#define	EMC_XM2CMDPADCTRL5	0x488
+
+#define	EMC_DLL_XFORM_DQS8	0x4A0
+#define	EMC_DLL_XFORM_DQS9	0x4A4
+#define	EMC_DLL_XFORM_DQS10	0x4A8
+#define	EMC_DLL_XFORM_DQS11	0x4AC
+#define	EMC_DLL_XFORM_DQS12	0x4B0
+#define	EMC_DLL_XFORM_DQS13	0x4B4
+#define	EMC_DLL_XFORM_DQS14	0x4B8
+#define	EMC_DLL_XFORM_DQS15	0x4BC
+#define	EMC_DLL_XFORM_QUSE8	0x4C0
+#define	EMC_DLL_XFORM_QUSE9	0x4C4
+#define	EMC_DLL_XFORM_QUSE10	0x4C8
+#define	EMC_DLL_XFORM_QUSE11	0x4CC
+#define	EMC_DLL_XFORM_QUSE12	0x4D0
+#define	EMC_DLL_XFORM_QUSE13	0x4D4
+#define	EMC_DLL_XFORM_QUSE14	0x4D8
+#define	EMC_DLL_XFORM_QUSE15	0x4DC
+#define	EMC_DLL_XFORM_DQ4	0x4E0
+#define	EMC_DLL_XFORM_DQ5	0x4E4
+#define	EMC_DLL_XFORM_DQ6	0x4E8
+#define	EMC_DLL_XFORM_DQ7	0x4EC
+
+#define	EMC_DLI_TRIM_TXDQS8	0x520
+#define	EMC_DLI_TRIM_TXDQS9	0x524
+#define	EMC_DLI_TRIM_TXDQS10	0x528
+#define	EMC_DLI_TRIM_TXDQS11	0x52C
+#define	EMC_DLI_TRIM_TXDQS12	0x530
+#define	EMC_DLI_TRIM_TXDQS13	0x534
+#define	EMC_DLI_TRIM_TXDQS14	0x538
+#define	EMC_DLI_TRIM_TXDQS15	0x53C
+#define	EMC_CDB_CNTL_3	0x540
+#define	EMC_XM2DQSPADCTRL5	0x544
+#define	EMC_XM2DQSPADCTRL6	0x548
+#define	EMC_XM2DQPADCTRL3	0x54C
+#define	EMC_DLL_XFORM_ADDR3	0x550
+#define	EMC_DLL_XFORM_ADDR4	0x554
+#define	EMC_DLL_XFORM_ADDR5	0x558
+#define	EMC_CFG_PIPE	0x560
+#define	EMC_QPOP	0x564
+#define	EMC_QUSE_WIDTH	0x568
+#define	EMC_PUTERM_WIDTH	0x56C
+#define	EMC_BGBIAS_CTL0	0x570
+#define	EMC_PUTERM_ADJ	0x574
+
+
+#endif
--- a/loader/heap.c
+++ b/loader/heap.c
@ -1,5 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
+* Copyright (c) 2018-2020 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
--- a/loader/heap.h
+++ b/loader/heap.h
@ -1,5 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
+* Copyright (c) 2018-2020 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
--- a/loader/io.c
+++ b/loader/io.c
@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2024 hydrogenium2020-offical
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+#include "types.h"
+u32 read32(u32 *addr)
+{
+    return *(vu32 *)addr;
+}
+
+void write32(u32 *addr, u32 val)
+{
+    *(vu32 *)addr = val;
+}
+
+void setbits32(u32 *addr,u32 bits)
+{
+	write32(addr, read32(addr) | bits);
+}
+
+void clrbits32(u32 *addr,u32 bits)
+{
+	write32(addr, read32(addr) & ~bits);
+}
+
+void clrsetbits32(u32 *addr,u32 mask, u32 value)
+{
+    write32(addr,(read32(addr) & ~((u32)(mask))) | (value));
+}
--- a/loader/io.h
+++ b/loader/io.h
@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2024 hydrogenium2020-offical
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+#include "types.h"
+u32 read32(u32 *addr);
+void write32(u32 *addr, u32 val);
+void setbits32(u32 *addr,u32 bits);
+void clrbits32(u32 *addr,u32 bits);
+void clrsetbits32(u32 *addr,u32 mask, u32 value);
--- a/loader/mc.c
+++ b/loader/mc.c
@ -1,6 +1,7 @@
 /*
 * Copyright (c) 2024 hydrogenium2020-offical
 * Copyright (c) 2018 naehrwert
+* Copyright (c) 2018-2022 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
--- a/loader/mc.h
+++ b/loader/mc.h
@ -1,6 +1,7 @@
 /*
 * Copyright (c) 2024 hydrogenium2020-offical
 * Copyright (c) 2018 naehrwert
+* Copyright (c) 2018-2022 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@ -14,7 +15,265 @@
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
+#ifndef _T124_MC_H_
+#define _T124_MC_H_

+#include "types.h"
+#define	MC_SMMU_CONFIG				0x10
+#define	MC_SMMU_TLB_CONFIG			0x14
+#define	MC_SMMU_PTC_CONFIG			0x18
+#define	MC_SMMU_PTB_ASID			0x1c
+#define	MC_SMMU_PTB_DATA			0x20
+#define	MC_SMMU_TLB_FLUSH			0x30
+#define	MC_SMMU_PTC_FLUSH			0x34
+#define	MC_EMEM_CFG					0x50
+#define	MC_EMEM_ADR_CFG				0x54
+#define	MC_EMEM_ADR_CFG_DEV0		0x58
+#define	MC_EMEM_ADR_CFG_DEV1		0x5c
+#define	MC_EMEM_ADR_CFG_BANK_MASK_0	0x64
+#define	MC_EMEM_ADR_CFG_BANK_MASK_1	0x68
+#define	MC_EMEM_ADR_CFG_BANK_MASK_2	0x6c
+#define	MC_EMEM_ARB_CFG				0x90
+#define	MC_EMEM_ARB_OUTSTANDING_REQ	0x94
+#define	MC_EMEM_ARB_TIMING_RCD		0x98
+#define	MC_EMEM_ARB_TIMING_RP		0x9c
+#define	MC_EMEM_ARB_TIMING_RC		0xa0
+#define	MC_EMEM_ARB_TIMING_RAS		0xa4
+#define	MC_EMEM_ARB_TIMING_FAW		0xa8
+#define	MC_EMEM_ARB_TIMING_RRD		0xac
+#define	MC_EMEM_ARB_TIMING_RAP2PRE	0xb0
+#define	MC_EMEM_ARB_TIMING_WAP2PRE	0xb4
+#define	MC_EMEM_ARB_TIMING_R2R		0xb8
+#define	MC_EMEM_ARB_TIMING_W2W		0xbc
+#define	MC_EMEM_ARB_TIMING_R2W		0xc0
+#define	MC_EMEM_ARB_TIMING_W2R		0xc4
+#define	MC_EMEM_ARB_DA_TURNS		0xd0
+#define	MC_EMEM_ARB_DA_COVERS		0xd4
+#define	MC_EMEM_ARB_MISC0			0xd8
+#define	MC_EMEM_ARB_MISC1			0xdc
+#define	MC_EMEM_ARB_RING1_THROTTLE	0xe0
+#define	MC_EMEM_ARB_RING3_THROTTLE	0xe4
+#define	MC_EMEM_ARB_OVERRIDE		0xe8
+#define	MC_EMEM_ARB_RSV				0xec
+#define	MC_CLKEN_OVERRIDE			0xf4
+#define	MC_TIMING_CONTROL_DBG		0xf8
+#define	MC_TIMING_CONTROL			0xfc
+#define	MC_STAT_CONTROL				0x100
+#define	MC_EMEM_ARB_ISOCHRONOUS_0	0x208
+#define	MC_EMEM_ARB_ISOCHRONOUS_1	0x20c
+#define	MC_EMEM_ARB_ISOCHRONOUS_2	0x210
+#define	MC_DIS_EXTRA_SNAP_LEVELS	0x2ac
+#define	MC_VIDEO_PROTECT_VPR_OVERRIDE	0x418
+#define	MC_VIDEO_PROTECT_VPR_OVERRIDE1	0x590
+#define	MC_DISPLAY_SNAP_RING		0x608
+#define	MC_VIDEO_PROTECT_BOM		0x648
+#define	MC_VIDEO_PROTECT_SIZE_MB	0x64c
+#define	MC_VIDEO_PROTECT_REG_CTRL	0x650
 #define MC_IRAM_BOM                 0x65c
 #define MC_IRAM_TOM                 0x660
+#define	MC_EMEM_CFG_ACCESS_CTRL		0x664
+#define	MC_SEC_CARVEOUT_BOM			0x670
+#define	MC_SEC_CARVEOUT_SIZE_MB		0x674
+#define	MC_SEC_CARVEOUT_REG_CTRL	0x678
+#define	MC_EMEM_ARB_OVERRIDE_1		0x968
+#define	MC_VIDEO_PROTECT_BOM_ADR_HI	0x978
+#define	MC_VIDEO_PROTECT_GPU_OVERRIDE_0	0x984
+#define	MC_VIDEO_PROTECT_GPU_OVERRIDE_1	0x988
+#define	MC_MTS_CARVEOUT_BOM			0x9a0
+#define	MC_MTS_CARVEOUT_SIZE_MB		0x9a4
+#define	MC_MTS_CARVEOUT_ADR_HI		0x9a8
+#define	MC_MTS_CARVEOUT_REG_CTRL	0x9ac
+#define	MC_EMEM_BANK_SWIZZLE_CFG0	0x9c0
+#define	MC_EMEM_BANK_SWIZZLE_CFG1	0x9c4
+#define	MC_EMEM_BANK_SWIZZLE_CFG2	0x9c8
+#define	MC_EMEM_BANK_SWIZZLE_CFG3	0x9cc
+#define	MC_SEC_CARVEOUT_ADR_HI		0x9d4
+
+struct tegra_mc_regs {
+	u32 rsvd_0x0[4];			/* 0x00 */
+	u32 smmu_config;			/* 0x10 */
+	u32 smmu_tlb_config;		/* 0x14 */
+	u32 smmu_ptc_config;		/* 0x18 */
+	u32 smmu_ptb_asid;			/* 0x1c */
+	u32 smmu_ptb_data;			/* 0x20 */
+	u32 rsvd_0x24[3];			/* 0x24 */
+	u32 smmu_tlb_flush;		/* 0x30 */
+	u32 smmu_ptc_flush;		/* 0x34 */
+	u32 rsvd_0x38[6];			/* 0x38 */
+	u32 emem_cfg;			/* 0x50 */
+	u32 emem_adr_cfg;			/* 0x54 */
+	u32 emem_adr_cfg_dev0;		/* 0x58 */
+	u32 emem_adr_cfg_dev1;		/* 0x5c */
+	u32 emem_adr_cfg_channel_mask;	/* 0x60 */
+	u32 emem_adr_cfg_bank_mask_0;	/* 0x64 */
+	u32 emem_adr_cfg_bank_mask_1;	/* 0x68 */
+	u32 emem_adr_cfg_bank_mask_2;	/* 0x6c */
+	u32 security_cfg0;			/* 0x70 */
+	u32 security_cfg1;			/* 0x74 */
+	u32 rsvd_0x78[6];			/* 0x78 */
+	u32 emem_arb_cfg;			/* 0x90 */
+	u32 emem_arb_outstanding_req;	/* 0x94 */
+	u32 emem_arb_timing_rcd;		/* 0x98 */
+	u32 emem_arb_timing_rp;		/* 0x9c */
+	u32 emem_arb_timing_rc;		/* 0xa0 */
+	u32 emem_arb_timing_ras;		/* 0xa4 */
+	u32 emem_arb_timing_faw;		/* 0xa8 */
+	u32 emem_arb_timing_rrd;		/* 0xac */
+	u32 emem_arb_timing_rap2pre;	/* 0xb0 */
+	u32 emem_arb_timing_wap2pre;	/* 0xb4 */
+	u32 emem_arb_timing_r2r;		/* 0xb8 */
+	u32 emem_arb_timing_w2w;		/* 0xbc */
+	u32 emem_arb_timing_r2w;		/* 0xc0 */
+	u32 emem_arb_timing_w2r;		/* 0xc4 */
+	u32 emem_arb_misc2;		/* 0xC8 */
+	u32 rsvd_0xcc[1];			/* 0xCC */
+	u32 emem_arb_da_turns;		/* 0xd0 */
+	u32 emem_arb_da_covers;		/* 0xd4 */
+	u32 emem_arb_misc0;		/* 0xd8 */
+	u32 emem_arb_misc1;		/* 0xdc */
+	u32 emem_arb_ring1_throttle;	/* 0xe0 */
+	u32 emem_arb_ring3_throttle;	/* 0xe4 */
+	u32 emem_arb_override;		/* 0xe8 */
+	u32 emem_arb_rsv;			/* 0xec */
+	u32 rsvd_0xf0[1];			/* 0xf0 */
+	u32 clken_override;		/* 0xf4 */
+	u32 timing_control_dbg;		/* 0xf8 */
+	u32 timing_control;		/* 0xfc */
+	u32 stat_control;			/* 0x100 */
+	u32 rsvd_0x104[65];		/* 0x104 */
+	u32 emem_arb_isochronous_0;	/* 0x208 */
+	u32 emem_arb_isochronous_1;	/* 0x20c */
+	u32 emem_arb_isochronous_2;	/* 0x210 */
+	u32 rsvd_0x214[38];		/* 0x214 */
+	u32 dis_extra_snap_levels;		/* 0x2ac */
+	u32 rsvd_0x2b0[90];		/* 0x2b0 */
+	u32 video_protect_vpr_override;	/* 0x418 */
+	u32 rsvd_0x41c[93];		/* 0x41c */
+	u32 video_protect_vpr_override1;	/* 0x590 */
+	u32 rsvd_0x594[29];		/* 0x594 */
+	u32 display_snap_ring;		/* 0x608 */
+	u32 rsvd_0x60c[15];		/* 0x60c */
+	u32 video_protect_bom;		/* 0x648 */
+	u32 video_protect_size_mb;		/* 0x64c */
+	u32 video_protect_reg_ctrl;	/* 0x650 */
+	u32 rsvd_0x654[4];			/* 0x654 */
+	u32 emem_cfg_access_ctrl;		/* 0x664 */
+	u32 rsvd_0x668[2];			/* 0x668 */
+	u32 sec_carveout_bom;		/* 0x670 */
+	u32 sec_carveout_size_mb;		/* 0x674 */
+	u32 sec_carveout_reg_ctrl;		/* 0x678 */
+	u32 rsvd_0x67c[17];		/* 0x67C-0x6BC */
+
+	u32 emem_arb_timing_rfcpb;		/* 0x6C0 */
+	u32 emem_arb_timing_ccdmw;		/* 0x6C4 */
+	u32 rsvd_0x6c8[10];		/* 0x6C8-0x6EC */
+
+	u32 emem_arb_refpb_hp_ctrl;	/* 0x6F0 */
+	u32 emem_arb_refpb_bank_ctrl;	/* 0x6F4 */
+	u32 rsvd_0x6f8[156];		/* 0x6F8-0x964 */
+
+	u32 emem_arb_override_1;		/* 0x968 */
+	u32 rsvd_0x96c[3];			/* 0x96c */
+	u32 video_protect_bom_adr_hi;	/* 0x978 */
+	u32 rsvd_0x97c[2];			/* 0x97c */
+	u32 video_protect_gpu_override_0;	/* 0x984 */
+	u32 video_protect_gpu_override_1;	/* 0x988 */
+	u32 rsvd_0x98c[5];			/* 0x98c */
+	u32 mts_carveout_bom;		/* 0x9a0 */
+	u32 mts_carveout_size_mb;		/* 0x9a4 */
+	u32 mts_carveout_adr_hi;		/* 0x9a8 */
+	u32 mts_carveout_reg_ctrl;		/* 0x9ac */
+	u32 rsvd_0x9b0[4];			/* 0x9b0 */
+	u32 emem_bank_swizzle_cfg0;	/* 0x9c0 */
+	u32 emem_bank_swizzle_cfg1;	/* 0x9c4 */
+	u32 emem_bank_swizzle_cfg2;	/* 0x9c8 */
+	u32 emem_bank_swizzle_cfg3;	/* 0x9cc */
+	u32 rsvd_0x9d0[1];			/* 0x9d0 */
+	u32 sec_carveout_adr_hi;		/* 0x9d4 */
+	u32 rsvd_0x9d8;			/* 0x9D8 */
+	u32 da_config0;			/* 0x9DC */
+	u32 rsvd_0x9c0[138];		/* 0x9E0-0xc04 */
+
+	u32 security_carveout1_cfg0;	/* 0xc08 */
+	u32 security_carveout1_bom;	/* 0xc0c */
+	u32 security_carveout1_bom_hi;	/* 0xc10 */
+	u32 security_carveout1_size_128kb;	/* 0xc14 */
+	u32 security_carveout1_ca0;	/* 0xc18 */
+	u32 security_carveout1_ca1;	/* 0xc1c */
+	u32 security_carveout1_ca2;	/* 0xc20 */
+	u32 security_carveout1_ca3;	/* 0xc24 */
+	u32 security_carveout1_ca4;	/* 0xc28 */
+	u32 security_carveout1_cfia0;	/* 0xc2c */
+	u32 security_carveout1_cfia1;	/* 0xc30 */
+	u32 security_carveout1_cfia2;	/* 0xc34 */
+	u32 security_carveout1_cfia3;	/* 0xc38 */
+	u32 security_carveout1_cfia4;	/* 0xc3c */
+	u32 rsvd_0xc40[6];			/* 0xc40-0xc54 */
+
+	u32 security_carveout2_cfg0;	/* 0xc58 */
+	u32 security_carveout2_bom;	/* 0xc5c */
+	u32 security_carveout2_bom_hi;	/* 0xc60 */
+	u32 security_carveout2_size_128kb;	/* 0xc64 */
+	u32 security_carveout2_ca0;	/* 0xc68 */
+	u32 security_carveout2_ca1;	/* 0xc6c */
+	u32 security_carveout2_ca2;	/* 0xc70 */
+	u32 security_carveout2_ca3;	/* 0xc74 */
+	u32 security_carveout2_ca4;	/* 0xc78 */
+	u32 security_carveout2_cfia0;	/* 0xc7c */
+	u32 security_carveout2_cfia1;	/* 0xc80 */
+	u32 security_carveout2_cfia2;	/* 0xc84 */
+	u32 security_carveout2_cfia3;	/* 0xc88 */
+	u32 security_carveout2_cfia4;	/* 0xc8c */
+	u32 rsvd_0xc90[6];			/* 0xc90-0xca4 */
+
+	u32 security_carveout3_cfg0;	/* 0xca8 */
+	u32 security_carveout3_bom;	/* 0xcac */
+	u32 security_carveout3_bom_hi;	/* 0xcb0 */
+	u32 security_carveout3_size_128kb;	/* 0xcb4 */
+	u32 security_carveout3_ca0;	/* 0xcb8 */
+	u32 security_carveout3_ca1;	/* 0xcbc */
+	u32 security_carveout3_ca2;	/* 0xcc0 */
+	u32 security_carveout3_ca3;	/* 0xcc4 */
+	u32 security_carveout3_ca4;	/* 0xcc8 */
+	u32 security_carveout3_cfia0;	/* 0xccc */
+	u32 security_carveout3_cfia1;	/* 0xcd0 */
+	u32 security_carveout3_cfia2;	/* 0xcd4 */
+	u32 security_carveout3_cfia3;	/* 0xcd8 */
+	u32 security_carveout3_cfia4;	/* 0xcdc */
+	u32 rsvd_0xce0[6];			/* 0xce0-0xcf4 */
+
+	u32 security_carveout4_cfg0;	/* 0xcf8 */
+	u32 security_carveout4_bom;	/* 0xcfc */
+	u32 security_carveout4_bom_hi;	/* 0xd00 */
+	u32 security_carveout4_size_128kb;	/* 0xd04 */
+	u32 security_carveout4_ca0;	/* 0xd08 */
+	u32 security_carveout4_ca1;	/* 0xd0c */
+	u32 security_carveout4_ca2;	/* 0xd10 */
+	u32 security_carveout4_ca3;	/* 0xd14 */
+	u32 security_carveout4_ca4;	/* 0xd18 */
+	u32 security_carveout4_cfia0;	/* 0xd1c */
+	u32 security_carveout4_cfia1;	/* 0xd20 */
+	u32 security_carveout4_cfia2;	/* 0xd24 */
+	u32 security_carveout4_cfia3;	/* 0xd28 */
+	u32 security_carveout4_cfia4;	/* 0xd2c */
+	u32 rsvd_0xd30[6];			/* 0xd30-0xd44 */
+
+	u32 security_carveout5_cfg0;	/* 0xd48 */
+	u32 security_carveout5_bom;	/* 0xd4c */
+	u32 security_carveout5_bom_hi;	/* 0xd50 */
+	u32 security_carveout5_size_128kb;	/* 0xd54 */
+	u32 security_carveout5_ca0;	/* 0xd58 */
+	u32 security_carveout5_ca1;	/* 0xd5c */
+	u32 security_carveout5_ca2;	/* 0xd60 */
+	u32 security_carveout5_ca3;	/* 0xd64 */
+	u32 security_carveout5_ca4;	/* 0xd68 */
+	u32 security_carveout5_cfia0;	/* 0xd6c */
+	u32 security_carveout5_cfia1;	/* 0xd70 */
+	u32 security_carveout5_cfia2;	/* 0xd74 */
+	u32 security_carveout5_cfia3;	/* 0xd78 */
+	u32 security_carveout5_cfia4;	/* 0xd7c */
+};
+
 void mc_enable();
+
+#endif
--- a/loader/memory_map.h
+++ b/loader/memory_map.h
@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2024 hydrogenium2020-offical
+ * Copyright (c) 2019-2021 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _T124_MEMORY_MAP_H_
+#define _T124_MEMORY_MAP_H_
+
+#define SDRAM_PARAMS_ADDR 0x40030000 // SDRAM extraction buffer during sdram init.
+
+/* --- DRAM START --- */
+#define DRAM_START     0x80000000
+
+/* Stack theoretical max: 33MB */
+#define IPL_STACK_TOP  0x83100000
+#define IPL_HEAP_START 0x84000000
+#define  IPL_HEAP_SZ      SZ_512M
+
+#endif
--- a/loader/pinmux.h
+++ b/loader/pinmux.h
@ -14,6 +14,10 @@
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
+
+#ifndef _T124_PINMUX_H_
+#define _T124_PINMUX_H_
+
 enum {
 	PINMUX_FUNC_MASK = 3 << 0,

@ -48,4 +52,4 @@ enum {
 void pinmux_config_uart(u32 idx);
 void pinmux_config_i2c(u32 idx);

-
+#endif
--- a/loader/pmc_lp0.h
+++ b/loader/pmc_lp0.h
@ -0,0 +1,385 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _T124_PMC_LP0_H_
+#define _T124_PMC_LP0_H_
+
+#include "types.h"
+
+enum {
+	POWER_PARTID_CRAIL = 0,
+	POWER_PARTID_TD = 1,
+	POWER_PARTID_VE = 2,
+	POWER_PARTID_VDE = 4,
+	POWER_PARTID_L2C = 5,
+	POWER_PARTID_MPE = 6,
+	POWER_PARTID_HEG = 7,
+	POWER_PARTID_CE1 = 9,
+	POWER_PARTID_CE2 = 10,
+	POWER_PARTID_CE3 = 11,
+	POWER_PARTID_CELP = 12,
+	POWER_PARTID_CE0 = 14,
+	POWER_PARTID_C0NC = 15,
+	POWER_PARTID_C1NC = 16,
+	POWER_PARTID_DIS = 18,
+	POWER_PARTID_DISB = 19,
+	POWER_PARTID_XUSBA = 20,
+	POWER_PARTID_XUSBB = 21,
+	POWER_PARTID_XUSBC = 22
+};
+
+struct tegra_pmc_regs {
+	u32 cntrl;
+	u32 sec_disable;
+	u32 pmc_swrst;
+	u32 wake_mask;
+	u32 wake_lvl;
+	u32 wake_status;
+	u32 sw_wake_status;
+	u32 dpd_pads_oride;
+	u32 dpd_sample;
+	u32 dpd_enable;
+	u32 pwrgate_timer_off;
+	u32 clamp_status;
+	u32 pwrgate_toggle;
+	u32 remove_clamping_cmd;
+	u32 pwrgate_status;
+	u32 pwrgood_timer;
+	u32 blink_timer;
+	u32 no_iopower;
+	u32 pwr_det;
+	u32 pwr_det_latch;
+	u32 scratch0;
+	u32 scratch1;
+	u32 scratch2;
+	u32 scratch3;
+	u32 scratch4;
+	u32 scratch5;
+	u32 scratch6;
+	u32 scratch7;
+	u32 scratch8;
+	u32 scratch9;
+	u32 scratch10;
+	u32 scratch11;
+	u32 scratch12;
+	u32 scratch13;
+	u32 scratch14;
+	u32 scratch15;
+	u32 scratch16;
+	u32 scratch17;
+	u32 scratch18;
+	u32 scratch19;
+	u32 odmdata;
+	u32 scratch21;
+	u32 scratch22;
+	u32 scratch23;
+	u32 secure_scratch0;
+	u32 secure_scratch1;
+	u32 secure_scratch2;
+	u32 secure_scratch3;
+	u32 secure_scratch4;
+	u32 secure_scratch5;
+	u32 cpupwrgood_timer;
+	u32 cpupwroff_timer;
+	u32 pg_mask;
+	u32 pg_mask_1;
+	u32 auto_wake_lvl;
+	u32 auto_wake_lvl_mask;
+	u32 wake_delay;
+	u32 pwr_det_val;
+	u32 ddr_pwr;
+	u32 usb_debounce_del;
+	u32 usb_a0;
+	u32 crypto_op;
+	u32 pllp_wb0_override;
+	u32 scratch24;
+	u32 scratch25;
+	u32 scratch26;
+	u32 scratch27;
+	u32 scratch28;
+	u32 scratch29;
+	u32 scratch30;
+	u32 scratch31;
+	u32 scratch32;
+	u32 scratch33;
+	u32 scratch34;
+	u32 scratch35;
+	u32 scratch36;
+	u32 scratch37;
+	u32 scratch38;
+	u32 scratch39;
+	u32 scratch40;
+	u32 scratch41;
+	u32 scratch42;
+	u32 bondout_mirror[3];
+	u32 sys_33v_en;
+	u32 bondout_mirror_access;
+	u32 gate;
+	u32 wake2_mask;
+	u32 wake2_lvl;
+	u32 wake2_status;
+	u32 sw_wake2_status;
+	u32 auto_wake2_lvl_mask;
+	u32 pg_mask_2;
+	u32 pg_mask_ce1;
+	u32 pg_mask_ce2;
+	u32 pg_mask_ce3;
+	u32 pwrgate_timer_ce[7];
+	u32 pcx_edpd_cntrl;
+	u32 osc_edpd_over;
+	u32 clk_out_cntrl;
+	u32 sata_pwrgt;
+	u32 sensor_ctrl;
+	u32 rst_status;
+	u32 io_dpd_req;
+	u32 io_dpd_status;
+	u32 io_dpd2_req;
+	u32 io_dpd2_status;
+	u32 sel_dpd_tim;
+	u32 vddp_sel;
+	u32 ddr_cfg;
+	u32 e_no_vttgen;
+	u8 _rsv0[4];
+	u32 pllm_wb0_override_freq;
+	u32 test_pwrgate;
+	u32 pwrgate_timer_mult;
+	u32 dis_sel_dpd;
+	u32 utmip_uhsic_triggers;
+	u32 utmip_uhsic_saved_state;
+	u32 utmip_pad_cfg;
+	u32 utmip_term_pad_cfg;
+	u32 utmip_uhsic_sleep_cfg;
+	u32 utmip_uhsic_sleepwalk_cfg;
+	u32 utmip_sleepwalk_p[3];
+	u32 uhsic_sleepwalk_p0;
+	u32 utmip_uhsic_status;
+	u32 utmip_uhsic_fake;
+	u32 bondout_mirror3[5 - 3];
+	u32 secure_scratch6;
+	u32 secure_scratch7;
+	u32 scratch43;
+	u32 scratch44;
+	u32 scratch45;
+	u32 scratch46;
+	u32 scratch47;
+	u32 scratch48;
+	u32 scratch49;
+	u32 scratch50;
+	u32 scratch51;
+	u32 scratch52;
+	u32 scratch53;
+	u32 scratch54;
+	u32 scratch55;
+	u32 scratch0_eco;
+	u32 por_dpd_ctrl;
+	u32 scratch2_eco;
+	u32 utmip_uhsic_line_wakeup;
+	u32 utmip_bias_master_cntrl;
+	u32 utmip_master_config;
+	u32 td_pwrgate_inter_part_timer;
+	u32 utmip_uhsic2_triggers;
+	u32 utmip_uhsic2_saved_state;
+	u32 utmip_uhsic2_sleep_cfg;
+	u32 utmip_uhsic2_sleepwalk_cfg;
+	u32 uhsic2_sleepwalk_p1;
+	u32 utmip_uhsic2_status;
+	u32 utmip_uhsic2_fake;
+	u32 utmip_uhsic2_line_wakeup;
+	u32 utmip_master2_config;
+	u32 utmip_uhsic_rpd_cfg;
+	u32 pg_mask_ce0;
+	u32 pg_mask3[5 - 3];
+	u32 pllm_wb0_override2;
+	u32 tsc_mult;
+	u32 cpu_vsense_override;
+	u32 glb_amap_cfg;
+	u32 sticky_bits;
+	u32 sec_disable2;
+	u32 weak_bias;
+	u32 reg_short;
+	u32 pg_mask_andor;
+	u8 _rsv1[0x2c];
+	u32 secure_scratch8;
+	u32 secure_scratch9;
+	u32 secure_scratch10;
+	u32 secure_scratch11;
+	u32 secure_scratch12;
+	u32 secure_scratch13;
+	u32 secure_scratch14;
+	u32 secure_scratch15;
+	u32 secure_scratch16;
+	u32 secure_scratch17;
+	u32 secure_scratch18;
+	u32 secure_scratch19;
+	u32 secure_scratch20;
+	u32 secure_scratch21;
+	u32 secure_scratch22;
+	u32 secure_scratch23;
+	u32 secure_scratch24;
+	u32 secure_scratch25;
+	u32 secure_scratch26;
+	u32 secure_scratch27;
+	u32 secure_scratch28;
+	u32 secure_scratch29;
+	u32 secure_scratch30;
+	u32 secure_scratch31;
+	u32 secure_scratch32;
+	u32 secure_scratch33;
+	u32 secure_scratch34;
+	u32 secure_scratch35;
+	u8 _rsv2[0xd0];
+	u32 cntrl2;
+	u8 _rsv3[0x18];
+	u32 io_dpd3_req;
+	u32 io_dqd3_status;
+	u32 strapping_opt_a;
+	u8 _rsv4[0x198];
+	u32 scratch56;
+	u32 scratch57;
+	u32 scratch58;
+	u32 scratch59;
+	u32 scratch60;
+	u32 scratch61;
+	u32 scratch62;
+	u32 scratch63;
+	u32 scratch64;
+	u32 scratch65;
+	u32 scratch66;
+	u32 scratch67;
+	u32 scratch68;
+	u32 scratch69;
+	u32 scratch70;
+	u32 scratch71;
+	u32 scratch72;
+	u32 scratch73;
+	u32 scratch74;
+	u32 scratch75;
+	u32 scratch76;
+	u32 scratch77;
+	u32 scratch78;
+	u32 scratch79;
+	u32 scratch80;
+	u32 scratch81;
+	u32 scratch82;
+	u32 scratch83;
+	u32 scratch84;
+	u32 scratch85;
+	u32 scratch86;
+	u32 scratch87;
+	u32 scratch88;
+	u32 scratch89;
+	u32 scratch90;
+	u32 scratch91;
+	u32 scratch92;
+	u32 scratch93;
+	u32 scratch94;
+	u32 scratch95;
+	u32 scratch96;
+	u32 scratch97;
+	u32 scratch98;
+	u32 scratch99;
+	u32 scratch100;
+	u32 scratch101;
+	u32 scratch102;
+	u32 scratch103;
+	u32 scratch104;
+	u32 scratch105;
+	u32 scratch106;
+	u32 scratch107;
+	u32 scratch108;
+	u32 scratch109;
+	u32 scratch110;
+	u32 scratch111;
+	u32 scratch112;
+	u32 scratch113;
+	u32 scratch114;
+	u32 scratch115;
+	u32 scratch116;
+	u32 scratch117;
+	u32 scratch118;
+	u32 scratch119;
+};
+
+enum {
+	PMC_PWRGATE_TOGGLE_PARTID_MASK = 0x1f,
+	PMC_PWRGATE_TOGGLE_PARTID_SHIFT = 0,
+	PMC_PWRGATE_TOGGLE_START = 0x1 << 8
+};
+
+enum {
+	PMC_CNTRL_KBC_CLK_DIS = 0x1 << 0,
+	PMC_CNTRL_RTC_CLK_DIS = 0x1 << 1,
+	PMC_CNTRL_RTC_RST = 0x1 << 2,
+	PMC_CNTRL_KBC_RST = 0x1 << 3,
+	PMC_CNTRL_MAIN_RST = 0x1 << 4,
+	PMC_CNTRL_LATCHWAKE_EN = 0x1 << 5,
+	PMC_CNTRL_GLITCHDET_DIS = 0x1 << 6,
+	PMC_CNTRL_BLINK_EN = 0x1 << 7,
+	PMC_CNTRL_PWRREQ_POLARITY = 0x1 << 8,
+	PMC_CNTRL_PWRREQ_OE = 0x1 << 9,
+	PMC_CNTRL_SYSCLK_POLARITY = 0x1 << 10,
+	PMC_CNTRL_SYSCLK_OE = 0x1 << 11,
+	PMC_CNTRL_PWRGATE_DIS = 0x1 << 12,
+	PMC_CNTRL_AOINIT = 0x1 << 13,
+	PMC_CNTRL_SIDE_EFFECT_LP0 = 0x1 << 14,
+	PMC_CNTRL_CPUPWRREQ_POLARITY = 0x1 << 15,
+	PMC_CNTRL_CPUPWRREQ_OE = 0x1 << 16,
+	PMC_CNTRL_INTR_POLARITY = 0x1 << 17,
+	PMC_CNTRL_FUSE_OVERRIDE = 0x1 << 18,
+	PMC_CNTRL_CPUPWRGOOD_EN = 0x1 << 19,
+	PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT = 20,
+	PMC_CNTRL_CPUPWRGOOD_SEL_MASK =
+		0x3 << PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT
+};
+
+enum {
+	PMC_DDR_PWR_EMMC_MASK = 1 << 1,
+	PMC_DDR_PWR_VAL_MASK = 1 << 0,
+};
+
+enum {
+	PMC_DDR_CFG_PKG_MASK = 1 << 0,
+	PMC_DDR_CFG_IF_MASK = 1 << 1,
+	PMC_DDR_CFG_XM0_RESET_TRI_MASK = 1 << 12,
+	PMC_DDR_CFG_XM0_RESET_DPDIO_MASK = 1 << 13,
+};
+
+enum {
+	PMC_NO_IOPOWER_MEM_MASK = 1 << 7,
+	PMC_NO_IOPOWER_MEM_COMP_MASK = 1 << 16,
+};
+
+enum {
+	PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK = 1 << 0,
+	PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK = 1 << 1,
+	PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK = 1 << 31,
+};
+
+enum {
+	PMC_CNTRL2_HOLD_CKE_LOW_EN = 0x1 << 12
+};
+
+enum {
+	PMC_OSC_EDPD_OVER_XOFS_SHIFT = 1,
+	PMC_OSC_EDPD_OVER_XOFS_MASK =
+		0x3f << PMC_OSC_EDPD_OVER_XOFS_SHIFT
+};
+
+enum {
+	PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT = 4,
+	PMC_STRAPPING_OPT_A_RAM_CODE_MASK =
+		0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT,
+};
+
+#endif
--- a/loader/sdram.c
+++ b/loader/sdram.c
@ -0,0 +1,741 @@
+/*
+ * Copyright 2014 Google Inc.
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018 balika011
+ * Copyright (c) 2019-2023 CTCaer
+ * Copyright (c) 2024 hydrogenium2020-offical
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "sdram.h"
+#include "memory_map.h"
+//#include "pmc.h"
+#include "util.h"
+#include "string.h"
+#include "sdram_config_h5tc4g63afr-rda-792mhz.inl"
+#include "t124.h"
+#include "printf.h"
+#include "sdram_lp0.h"
+#include "pmc_lp0.h"
+#include "clock_lp0.h"
+#include "io.h"
+static struct clk_rst_ctlr *clk_rst = (void *)CLOCK_BASE;
+void *sdram_get_params_t124()
+{
+	// Copy base parameters.
+	u32 *params = (u32 *)SDRAM_PARAMS_ADDR;
+	memcpy(params, &dram_cfg_4gb_h5tc4g63afr_rda_792mhz, sizeof(sdram_params_t124));
+	printf_("%u",sizeof(sdram_params_t124));
+
+	return (void *)params;
+}
+
+
+static void sdram_patch(uintptr_t addr, u32 value)
+{
+	if (addr)
+		write32((u32 *)addr, value);
+}
+
+static void writebits(u32 value, u32 *addr, u32 mask)
+{
+	clrsetbits32(addr, mask, (value & mask));
+}
+
+/* PMC must be configured before clock-enable and de-reset of MC/EMC. */
+static void sdram_configure_pmc(const sdram_params_t124 *param,
+				struct tegra_pmc_regs *regs)
+{
+	/* VDDP Select */
+	write32(&regs->vddp_sel, param->PmcVddpSel);
+	sleep(param->PmcVddpSelWait);
+
+	/* Set DDR pad voltage */
+	writebits(param->PmcDdrPwr, &regs->ddr_pwr, PMC_DDR_PWR_VAL_MASK);
+
+	/* Set package and DPD pad control */
+	writebits(param->PmcDdrCfg, &regs->ddr_cfg,
+		  (PMC_DDR_CFG_PKG_MASK | PMC_DDR_CFG_IF_MASK |
+		   PMC_DDR_CFG_XM0_RESET_TRI_MASK |
+		   PMC_DDR_CFG_XM0_RESET_DPDIO_MASK));
+
+	/* Turn on MEM IO Power */
+	writebits(param->PmcNoIoPower, &regs->no_iopower,
+		  (PMC_NO_IOPOWER_MEM_MASK | PMC_NO_IOPOWER_MEM_COMP_MASK));
+
+	write32(&regs->reg_short, param->PmcRegShort);
+}
+void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
+{
+	if (l) write32(&clk_rst->clk_enb_l_set, l);
+	if (h) write32(&clk_rst->clk_enb_h_set, h);
+	if (u) write32(&clk_rst->clk_enb_u_set, u);
+	if (v) write32(&clk_rst->clk_enb_v_set, v);
+	if (w) write32(&clk_rst->clk_enb_w_set, w);
+	if (x) write32(&clk_rst->clk_enb_x_set, x);
+
+	/* Give clocks time to stabilize. */
+	sleep(2);
+
+	if (l) write32(&clk_rst->rst_dev_l_clr, l);
+	if (h) write32(&clk_rst->rst_dev_h_clr, h);
+	if (u) write32(&clk_rst->rst_dev_u_clr, u);
+	if (v) write32(&clk_rst->rst_dev_v_clr, v);
+	if (w) write32(&clk_rst->rst_dev_w_clr, w);
+	if (x) write32(&clk_rst->rst_dev_x_clr, x);
+}
+/* Start PLLM for SDRAM. */
+void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
+		 u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source,
+		 u32 same_freq)
+{
+
+	u32 misc1 = ((setup << PLLM_MISC1_SETUP_SHIFT) |
+		     (ph45 << PLLM_MISC1_PD_LSHIFT_PH45_SHIFT) |
+		     (ph90 << PLLM_MISC1_PD_LSHIFT_PH90_SHIFT) |
+		     (ph135 << PLLM_MISC1_PD_LSHIFT_PH135_SHIFT)),
+	    misc2 = ((kvco << PLLM_MISC2_KVCO_SHIFT) |
+		     (kcp << PLLM_MISC2_KCP_SHIFT)),
+	    base;
+
+	if (same_freq)
+		emc_source |= CLK_SOURCE_EMC_MC_EMC_SAME_FREQ;
+	else
+		emc_source &= ~CLK_SOURCE_EMC_MC_EMC_SAME_FREQ;
+
+	/*
+	 * Note PLLM_BASE.PLLM_OUT1_RSTN must be in RESET_ENABLE mode, and
+	 * PLLM_BASE.ENABLE must be in DISABLE state (both are the default
+	 * values after coldboot reset).
+	 */
+
+	write32(&clk_rst->pllm_misc1, misc1);
+	write32(&clk_rst->pllm_misc2, misc2);
+
+	/* PLLM.BASE needs BYPASS=0, different from general init_pll */
+	base = read32(&clk_rst->pllm_base);
+	base &= ~(PLLCMX_BASE_DIVN_MASK | PLLCMX_BASE_DIVM_MASK |
+		  PLLM_BASE_DIVP_MASK | PLL_BASE_BYPASS);
+	base |= ((m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) |
+		 (p << PLL_BASE_DIVP_SHIFT));
+	write32(&clk_rst->pllm_base, base);
+
+	setbits32(&clk_rst->pllm_base, PLL_BASE_ENABLE);
+	/* stable_time is required, before we can start to check lock. */
+	sleep(stable_time);
+
+	while (!(read32(&clk_rst->pllm_base) & PLL_BASE_LOCK)) {
+		sleep(1);
+	}
+	/*
+	 * After PLLM reports being locked, we have to delay 10us before
+	 * enabling PLLM_OUT.
+	 */
+	sleep(10);
+
+	/* Put OUT1 out of reset state (start to output). */
+	setbits32(&clk_rst->pllm_out, PLLM_OUT1_RSTN_RESET_DISABLE);
+
+	/* Enable and start MEM(MC) and EMC. */
+	clock_enable_clear_reset(0, (0x1 << 0) | (0x1 << 25), 0, 0, 0, 0);
+	write32(&clk_rst->clk_src_emc, emc_source);
+	sleep(2);
+}
+
+static void sdram_start_clocks(const sdram_params_t124 *param)
+{
+	u32 is_same_freq = (param->McEmemArbMisc0 &
+			    MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK) ? 1 : 0;
+
+	clock_sdram(param->PllMInputDivider, param->PllMFeedbackDivider,
+		    param->PllMSelectDiv2, param->PllMSetupControl,
+		    param->PllMPDLshiftPh45, param->PllMPDLshiftPh90,
+		    param->PllMPDLshiftPh135, param->PllMKVCO,
+		    param->PllMKCP, param->PllMStableTime,
+		    param->EmcClockSource, is_same_freq);
+}
+
+static void sdram_deassert_clock_enable_signal(const sdram_params_t124 *param,
+					       struct tegra_pmc_regs *regs)
+{
+	clrbits32(&regs->por_dpd_ctrl,
+		  PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK);
+	sleep(param->PmcPorDpdCtrlWait);
+}
+
+static void sdram_deassert_sel_dpd(const sdram_params_t124 *param,
+				   struct tegra_pmc_regs *regs)
+{
+	clrbits32(&regs->por_dpd_ctrl,
+		  (PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK |
+		   PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK));
+	/*
+	 * Note NVIDIA recommended to always do 10us delay here and ignore
+	 * BCT.PmcPorDpdCtrlWait.
+	 * */
+	sleep(10);
+}
+
+static void sdram_set_swizzle(const sdram_params_t124 *param,
+			      struct tegra_emc_regs *regs)
+{
+	write32(&regs->swizzle_rank0_byte_cfg, param->EmcSwizzleRank0ByteCfg);
+	write32(&regs->swizzle_rank0_byte0, param->EmcSwizzleRank0Byte0);
+	write32(&regs->swizzle_rank0_byte1, param->EmcSwizzleRank0Byte1);
+	write32(&regs->swizzle_rank0_byte2, param->EmcSwizzleRank0Byte2);
+	write32(&regs->swizzle_rank0_byte3, param->EmcSwizzleRank0Byte3);
+	write32(&regs->swizzle_rank1_byte_cfg, param->EmcSwizzleRank1ByteCfg);
+	write32(&regs->swizzle_rank1_byte0, param->EmcSwizzleRank1Byte0);
+	write32(&regs->swizzle_rank1_byte1, param->EmcSwizzleRank1Byte1);
+	write32(&regs->swizzle_rank1_byte2, param->EmcSwizzleRank1Byte2);
+	write32(&regs->swizzle_rank1_byte3, param->EmcSwizzleRank1Byte3);
+}
+
+static void sdram_set_pad_controls(const sdram_params_t124 *param,
+				   struct tegra_emc_regs *regs)
+{
+	/* Program the pad controls */
+	write32(&regs->xm2cmdpadctrl, param->EmcXm2CmdPadCtrl);
+	write32(&regs->xm2cmdpadctrl2, param->EmcXm2CmdPadCtrl2);
+	write32(&regs->xm2cmdpadctrl3, param->EmcXm2CmdPadCtrl3);
+	write32(&regs->xm2cmdpadctrl4, param->EmcXm2CmdPadCtrl4);
+	write32(&regs->xm2cmdpadctrl5, param->EmcXm2CmdPadCtrl5);
+
+	write32(&regs->xm2dqspadctrl, param->EmcXm2DqsPadCtrl);
+	write32(&regs->xm2dqspadctrl2, param->EmcXm2DqsPadCtrl2);
+	write32(&regs->xm2dqspadctrl3, param->EmcXm2DqsPadCtrl3);
+	write32(&regs->xm2dqspadctrl4, param->EmcXm2DqsPadCtrl4);
+	write32(&regs->xm2dqspadctrl5, param->EmcXm2DqsPadCtrl5);
+	write32(&regs->xm2dqspadctrl6, param->EmcXm2DqsPadCtrl6);
+
+	write32(&regs->xm2dqpadctrl, param->EmcXm2DqPadCtrl);
+	write32(&regs->xm2dqpadctrl2, param->EmcXm2DqPadCtrl2);
+	write32(&regs->xm2dqpadctrl3, param->EmcXm2DqPadCtrl3);
+
+	write32(&regs->xm2clkpadctrl, param->EmcXm2ClkPadCtrl);
+	write32(&regs->xm2clkpadctrl2, param->EmcXm2ClkPadCtrl2);
+
+	write32(&regs->xm2comppadctrl, param->EmcXm2CompPadCtrl);
+
+	write32(&regs->xm2vttgenpadctrl, param->EmcXm2VttGenPadCtrl);
+	write32(&regs->xm2vttgenpadctrl2, param->EmcXm2VttGenPadCtrl2);
+	write32(&regs->xm2vttgenpadctrl3, param->EmcXm2VttGenPadCtrl3);
+
+	write32(&regs->ctt_term_ctrl, param->EmcCttTermCtrl);
+}
+
+static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs)
+{
+	write32(&regs->timing_control, EMC_TIMING_CONTROL_TIMING_UPDATE);
+}
+
+static void sdram_init_mc(const sdram_params_t124 *param,
+			  struct tegra_mc_regs *regs)
+{
+	/* Initialize MC VPR settings */
+	write32(&regs->display_snap_ring, param->McDisplaySnapRing);
+	write32(&regs->video_protect_bom, param->McVideoProtectBom);
+	write32(&regs->video_protect_bom_adr_hi,
+		param->McVideoProtectBomAdrHi);
+	write32(&regs->video_protect_size_mb, param->McVideoProtectSizeMb);
+	write32(&regs->video_protect_vpr_override,
+		param->McVideoProtectVprOverride);
+	write32(&regs->video_protect_vpr_override1,
+		param->McVideoProtectVprOverride1);
+	write32(&regs->video_protect_gpu_override_0,
+		param->McVideoProtectGpuOverride0);
+	write32(&regs->video_protect_gpu_override_1,
+		param->McVideoProtectGpuOverride1);
+
+	/* Program SDRAM geometry paarameters */
+	write32(&regs->emem_adr_cfg, param->McEmemAdrCfg);
+	write32(&regs->emem_adr_cfg_dev0, param->McEmemAdrCfgDev0);
+	write32(&regs->emem_adr_cfg_dev1, param->McEmemAdrCfgDev1);
+
+	/* Program bank swizzling */
+	write32(&regs->emem_bank_swizzle_cfg0, param->McEmemAdrCfgBankMask0);
+	write32(&regs->emem_bank_swizzle_cfg1, param->McEmemAdrCfgBankMask1);
+	write32(&regs->emem_bank_swizzle_cfg2, param->McEmemAdrCfgBankMask2);
+	write32(&regs->emem_bank_swizzle_cfg3,
+		param->McEmemAdrCfgBankSwizzle3);
+
+	/* Program external memory aperature (base and size) */
+	write32(&regs->emem_cfg, param->McEmemCfg);
+
+	/* Program SEC carveout (base and size) */
+	write32(&regs->sec_carveout_bom, param->McSecCarveoutBom);
+	write32(&regs->sec_carveout_adr_hi, param->McSecCarveoutAdrHi);
+	write32(&regs->sec_carveout_size_mb, param->McSecCarveoutSizeMb);
+
+	/* Program MTS carveout (base and size) */
+	write32(&regs->mts_carveout_bom, param->McMtsCarveoutBom);
+	write32(&regs->mts_carveout_adr_hi, param->McMtsCarveoutAdrHi);
+	write32(&regs->mts_carveout_size_mb, param->McMtsCarveoutSizeMb);
+
+	/* Program the memory arbiter */
+	write32(&regs->emem_arb_cfg, param->McEmemArbCfg);
+	write32(&regs->emem_arb_outstanding_req,
+		param->McEmemArbOutstandingReq);
+	write32(&regs->emem_arb_timing_rcd, param->McEmemArbTimingRcd);
+	write32(&regs->emem_arb_timing_rp, param->McEmemArbTimingRp);
+	write32(&regs->emem_arb_timing_rc, param->McEmemArbTimingRc);
+	write32(&regs->emem_arb_timing_ras, param->McEmemArbTimingRas);
+	write32(&regs->emem_arb_timing_faw, param->McEmemArbTimingFaw);
+	write32(&regs->emem_arb_timing_rrd, param->McEmemArbTimingRrd);
+	write32(&regs->emem_arb_timing_rap2pre, param->McEmemArbTimingRap2Pre);
+	write32(&regs->emem_arb_timing_wap2pre, param->McEmemArbTimingWap2Pre);
+	write32(&regs->emem_arb_timing_r2r, param->McEmemArbTimingR2R);
+	write32(&regs->emem_arb_timing_w2w, param->McEmemArbTimingW2W);
+	write32(&regs->emem_arb_timing_r2w, param->McEmemArbTimingR2W);
+	write32(&regs->emem_arb_timing_w2r, param->McEmemArbTimingW2R);
+	write32(&regs->emem_arb_da_turns, param->McEmemArbDaTurns);
+	write32(&regs->emem_arb_da_covers, param->McEmemArbDaCovers);
+	write32(&regs->emem_arb_misc0, param->McEmemArbMisc0);
+	write32(&regs->emem_arb_misc1, param->McEmemArbMisc1);
+	write32(&regs->emem_arb_ring1_throttle, param->McEmemArbRing1Throttle);
+	write32(&regs->emem_arb_override, param->McEmemArbOverride);
+	write32(&regs->emem_arb_override_1, param->McEmemArbOverride1);
+	write32(&regs->emem_arb_rsv, param->McEmemArbRsv);
+
+	/* Program extra snap levels for display client */
+	write32(&regs->dis_extra_snap_levels, param->McDisExtraSnapLevels);
+
+	/* Trigger MC timing update */
+	write32(&regs->timing_control, MC_TIMING_CONTROL_TIMING_UPDATE);
+
+	/* Program second-level clock enable overrides */
+	write32(&regs->clken_override, param->McClkenOverride);
+
+	/* Program statistics gathering */
+	write32(&regs->stat_control, param->McStatControl);
+}
+
+static void sdram_init_emc(const sdram_params_t124 *param,
+			   struct tegra_emc_regs *regs)
+{
+	/* Program SDRAM geometry parameters */
+	write32(&regs->adr_cfg, param->EmcAdrCfg);
+
+	/* Program second-level clock enable overrides */
+	write32(&regs->clken_override, param->EmcClkenOverride);
+
+	/* Program EMC pad auto calibration */
+	write32(&regs->auto_cal_interval, param->EmcAutoCalInterval);
+	write32(&regs->auto_cal_config2, param->EmcAutoCalConfig2);
+	write32(&regs->auto_cal_config3, param->EmcAutoCalConfig3);
+	write32(&regs->auto_cal_config, param->EmcAutoCalConfig);
+	sleep(param->EmcAutoCalWait);
+}
+
+static void sdram_set_emc_timing(const sdram_params_t124 *param,
+				 struct tegra_emc_regs *regs)
+{
+	/* Program EMC timing configuration */
+	write32(&regs->cfg_2, param->EmcCfg2);
+	write32(&regs->cfg_pipe, param->EmcCfgPipe);
+	write32(&regs->dbg, param->EmcDbg);
+	write32(&regs->cmdq, param->EmcCmdQ);
+	write32(&regs->mc2emcq, param->EmcMc2EmcQ);
+	write32(&regs->mrs_wait_cnt, param->EmcMrsWaitCnt);
+	write32(&regs->mrs_wait_cnt2, param->EmcMrsWaitCnt2);
+	write32(&regs->fbio_cfg5, param->EmcFbioCfg5);
+	write32(&regs->rc, param->EmcRc);
+	write32(&regs->rfc, param->EmcRfc);
+	write32(&regs->rfc_slr, param->EmcRfcSlr);
+	write32(&regs->ras, param->EmcRas);
+	write32(&regs->rp, param->EmcRp);
+	write32(&regs->r2r, param->EmcR2r);
+	write32(&regs->w2w, param->EmcW2w);
+	write32(&regs->r2w, param->EmcR2w);
+	write32(&regs->w2r, param->EmcW2r);
+	write32(&regs->r2p, param->EmcR2p);
+	write32(&regs->w2p, param->EmcW2p);
+	write32(&regs->rd_rcd, param->EmcRdRcd);
+	write32(&regs->wr_rcd, param->EmcWrRcd);
+	write32(&regs->rrd, param->EmcRrd);
+	write32(&regs->rext, param->EmcRext);
+	write32(&regs->wext, param->EmcWext);
+	write32(&regs->wdv, param->EmcWdv);
+	write32(&regs->wdv_mask, param->EmcWdvMask);
+	write32(&regs->quse, param->EmcQUse);
+	write32(&regs->quse_width, param->EmcQuseWidth);
+	write32(&regs->ibdly, param->EmcIbdly);
+	write32(&regs->einput, param->EmcEInput);
+	write32(&regs->einput_duration, param->EmcEInputDuration);
+	write32(&regs->puterm_extra, param->EmcPutermExtra);
+	write32(&regs->puterm_width, param->EmcPutermWidth);
+	write32(&regs->puterm_adj, param->EmcPutermAdj);
+	write32(&regs->cdb_cntl_1, param->EmcCdbCntl1);
+	write32(&regs->cdb_cntl_2, param->EmcCdbCntl2);
+	write32(&regs->cdb_cntl_3, param->EmcCdbCntl3);
+	write32(&regs->qrst, param->EmcQRst);
+	write32(&regs->qsafe, param->EmcQSafe);
+	write32(&regs->rdv, param->EmcRdv);
+	write32(&regs->rdv_mask, param->EmcRdvMask);
+	write32(&regs->qpop, param->EmcQpop);
+	write32(&regs->ctt, param->EmcCtt);
+	write32(&regs->ctt_duration, param->EmcCttDuration);
+	write32(&regs->refresh, param->EmcRefresh);
+	write32(&regs->burst_refresh_num, param->EmcBurstRefreshNum);
+	write32(&regs->pre_refresh_req_cnt, param->EmcPreRefreshReqCnt);
+	write32(&regs->pdex2wr, param->EmcPdEx2Wr);
+	write32(&regs->pdex2rd, param->EmcPdEx2Rd);
+	write32(&regs->pchg2pden, param->EmcPChg2Pden);
+	write32(&regs->act2pden, param->EmcAct2Pden);
+	write32(&regs->ar2pden, param->EmcAr2Pden);
+	write32(&regs->rw2pden, param->EmcRw2Pden);
+	write32(&regs->txsr, param->EmcTxsr);
+	write32(&regs->txsrdll, param->EmcTxsrDll);
+	write32(&regs->tcke, param->EmcTcke);
+	write32(&regs->tckesr, param->EmcTckesr);
+	write32(&regs->tpd, param->EmcTpd);
+	write32(&regs->tfaw, param->EmcTfaw);
+	write32(&regs->trpab, param->EmcTrpab);
+	write32(&regs->tclkstable, param->EmcTClkStable);
+	write32(&regs->tclkstop, param->EmcTClkStop);
+	write32(&regs->trefbw, param->EmcTRefBw);
+	write32(&regs->odt_write, param->EmcOdtWrite);
+	write32(&regs->odt_read, param->EmcOdtRead);
+	write32(&regs->fbio_cfg6, param->EmcFbioCfg6);
+	write32(&regs->cfg_dig_dll, param->EmcCfgDigDll);
+	write32(&regs->cfg_dig_dll_period, param->EmcCfgDigDllPeriod);
+
+	/* Don't write bit 1: addr swizzle lock bit. Written at end of sequence. */
+	write32(&regs->fbio_spare, param->EmcFbioSpare & 0xfffffffd);
+
+	write32(&regs->cfg_rsv, param->EmcCfgRsv);
+	write32(&regs->dll_xform_dqs0, param->EmcDllXformDqs0);
+	write32(&regs->dll_xform_dqs1, param->EmcDllXformDqs1);
+	write32(&regs->dll_xform_dqs2, param->EmcDllXformDqs2);
+	write32(&regs->dll_xform_dqs3, param->EmcDllXformDqs3);
+	write32(&regs->dll_xform_dqs4, param->EmcDllXformDqs4);
+	write32(&regs->dll_xform_dqs5, param->EmcDllXformDqs5);
+	write32(&regs->dll_xform_dqs6, param->EmcDllXformDqs6);
+	write32(&regs->dll_xform_dqs7, param->EmcDllXformDqs7);
+	write32(&regs->dll_xform_dqs8, param->EmcDllXformDqs8);
+	write32(&regs->dll_xform_dqs9, param->EmcDllXformDqs9);
+	write32(&regs->dll_xform_dqs10, param->EmcDllXformDqs10);
+	write32(&regs->dll_xform_dqs11, param->EmcDllXformDqs11);
+	write32(&regs->dll_xform_dqs12, param->EmcDllXformDqs12);
+	write32(&regs->dll_xform_dqs13, param->EmcDllXformDqs13);
+	write32(&regs->dll_xform_dqs14, param->EmcDllXformDqs14);
+	write32(&regs->dll_xform_dqs15, param->EmcDllXformDqs15);
+	write32(&regs->dll_xform_quse0, param->EmcDllXformQUse0);
+	write32(&regs->dll_xform_quse1, param->EmcDllXformQUse1);
+	write32(&regs->dll_xform_quse2, param->EmcDllXformQUse2);
+	write32(&regs->dll_xform_quse3, param->EmcDllXformQUse3);
+	write32(&regs->dll_xform_quse4, param->EmcDllXformQUse4);
+	write32(&regs->dll_xform_quse5, param->EmcDllXformQUse5);
+	write32(&regs->dll_xform_quse6, param->EmcDllXformQUse6);
+	write32(&regs->dll_xform_quse7, param->EmcDllXformQUse7);
+	write32(&regs->dll_xform_quse8, param->EmcDllXformQUse8);
+	write32(&regs->dll_xform_quse9, param->EmcDllXformQUse9);
+	write32(&regs->dll_xform_quse10, param->EmcDllXformQUse10);
+	write32(&regs->dll_xform_quse11, param->EmcDllXformQUse11);
+	write32(&regs->dll_xform_quse12, param->EmcDllXformQUse12);
+	write32(&regs->dll_xform_quse13, param->EmcDllXformQUse13);
+	write32(&regs->dll_xform_quse14, param->EmcDllXformQUse14);
+	write32(&regs->dll_xform_quse15, param->EmcDllXformQUse15);
+	write32(&regs->dll_xform_dq0, param->EmcDllXformDq0);
+	write32(&regs->dll_xform_dq1, param->EmcDllXformDq1);
+	write32(&regs->dll_xform_dq2, param->EmcDllXformDq2);
+	write32(&regs->dll_xform_dq3, param->EmcDllXformDq3);
+	write32(&regs->dll_xform_dq4, param->EmcDllXformDq4);
+	write32(&regs->dll_xform_dq5, param->EmcDllXformDq5);
+	write32(&regs->dll_xform_dq6, param->EmcDllXformDq6);
+	write32(&regs->dll_xform_dq7, param->EmcDllXformDq7);
+	write32(&regs->dll_xform_addr0, param->EmcDllXformAddr0);
+	write32(&regs->dll_xform_addr1, param->EmcDllXformAddr1);
+	write32(&regs->dll_xform_addr2, param->EmcDllXformAddr2);
+	write32(&regs->dll_xform_addr3, param->EmcDllXformAddr3);
+	write32(&regs->dll_xform_addr4, param->EmcDllXformAddr4);
+	write32(&regs->dll_xform_addr5, param->EmcDllXformAddr5);
+	write32(&regs->acpd_control, param->EmcAcpdControl);
+	write32(&regs->dsr_vttgen_drv, param->EmcDsrVttgenDrv);
+	write32(&regs->txdsrvttgen, param->EmcTxdsrvttgen);
+	write32(&regs->bgbias_ctl0, param->EmcBgbiasCtl0);
+
+	/*
+	 * Set pipe bypass enable bits before sending any DRAM commands.
+	 * Note other bits in EMC_CFG must be set AFTER REFCTRL is configured.
+	 */
+	writebits(param->EmcCfg, &regs->cfg,
+		  (EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK |
+		   EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK |
+		   EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK));
+}
+
+static void sdram_patch_bootrom(const sdram_params_t124 *param,
+				struct tegra_mc_regs *regs)
+{
+	if (param->BootRomPatchControl & BOOT_ROM_PATCH_CONTROL_ENABLE_MASK) {
+		uintptr_t addr = ((param->BootRomPatchControl &
+				  BOOT_ROM_PATCH_CONTROL_OFFSET_MASK) >>
+				  BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT);
+		addr = BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS + (addr << 2);
+		write32((u32 *)addr, param->BootRomPatchData);
+		write32(&regs->timing_control, 1);
+	}
+}
+
+static void sdram_set_dpd3(const sdram_params_t124 *param,
+			   struct tegra_pmc_regs *regs)
+{
+	/* Program DPD request */
+	write32(&regs->io_dpd3_req, param->PmcIoDpd3Req);
+	sleep(param->PmcIoDpd3ReqWait);
+}
+
+static void sdram_set_dli_trims(const sdram_params_t124 *param,
+				struct tegra_emc_regs *regs)
+{
+	/* Program DLI trims */
+	write32(&regs->dli_trim_txdqs0, param->EmcDliTrimTxDqs0);
+	write32(&regs->dli_trim_txdqs1, param->EmcDliTrimTxDqs1);
+	write32(&regs->dli_trim_txdqs2, param->EmcDliTrimTxDqs2);
+	write32(&regs->dli_trim_txdqs3, param->EmcDliTrimTxDqs3);
+	write32(&regs->dli_trim_txdqs4, param->EmcDliTrimTxDqs4);
+	write32(&regs->dli_trim_txdqs5, param->EmcDliTrimTxDqs5);
+	write32(&regs->dli_trim_txdqs6, param->EmcDliTrimTxDqs6);
+	write32(&regs->dli_trim_txdqs7, param->EmcDliTrimTxDqs7);
+	write32(&regs->dli_trim_txdqs8, param->EmcDliTrimTxDqs8);
+	write32(&regs->dli_trim_txdqs9, param->EmcDliTrimTxDqs9);
+	write32(&regs->dli_trim_txdqs10, param->EmcDliTrimTxDqs10);
+	write32(&regs->dli_trim_txdqs11, param->EmcDliTrimTxDqs11);
+	write32(&regs->dli_trim_txdqs12, param->EmcDliTrimTxDqs12);
+	write32(&regs->dli_trim_txdqs13, param->EmcDliTrimTxDqs13);
+	write32(&regs->dli_trim_txdqs14, param->EmcDliTrimTxDqs14);
+	write32(&regs->dli_trim_txdqs15, param->EmcDliTrimTxDqs15);
+
+	write32(&regs->ca_training_timing_cntl1,
+		param->EmcCaTrainingTimingCntl1);
+	write32(&regs->ca_training_timing_cntl2,
+		param->EmcCaTrainingTimingCntl2);
+
+	sdram_trigger_emc_timing_update(regs);
+	sleep(param->EmcTimingControlWait);
+}
+
+static void sdram_set_clock_enable_signal(const sdram_params_t124 *param,
+					  struct tegra_emc_regs *regs)
+{
+	volatile u32 dummy = 0;
+	clrbits32(&regs->pin, (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK |
+			       EMC_PIN_CKE_MASK));
+	/*
+	 * Assert dummy read of PIN register to ensure above write to PIN
+	 * register went through. 200 is the recommended value by NVIDIA.
+	 */
+	dummy |= read32(&regs->pin);
+	sleep(200 + param->EmcPinExtraWait);
+
+	/* Deassert reset */
+	setbits32(&regs->pin, EMC_PIN_RESET_INACTIVE);
+	/*
+	 * Assert dummy read of PIN register to ensure above write to PIN
+	 * register went through. 200 is the recommended value by NVIDIA.
+	 */
+	dummy |= read32(&regs->pin);
+	sleep(500 + param->EmcPinExtraWait);
+
+	/* Enable clock enable signal */
+	setbits32(&regs->pin, EMC_PIN_CKE_NORMAL);
+	/*
+	 * Assert dummy read of PIN register to ensure above write to PIN
+	 * register went through. 200 is the recommended value by NVIDIA.
+	 */
+	dummy |= read32(&regs->pin);
+	sleep(param->EmcPinProgramWait);
+
+	if (!dummy) {
+		printf_("Failed to program EMC pin.");
+	}
+
+	/* Send NOP (trigger) */
+	writebits(((1 << EMC_NOP_NOP_CMD_SHIFT) |
+		   (param->EmcDevSelect << EMC_NOP_NOP_DEV_SELECTN_SHIFT)),
+		  &regs->nop,
+		  EMC_NOP_NOP_CMD_MASK | EMC_NOP_NOP_DEV_SELECTN_MASK);
+
+	/* Write mode registers */
+	write32(&regs->emrs2, param->EmcEmrs2);
+	write32(&regs->emrs3, param->EmcEmrs3);
+	write32(&regs->emrs, param->EmcEmrs);
+	write32(&regs->mrs, param->EmcMrs);
+
+	if (param->EmcExtraModeRegWriteEnable) {
+		write32(&regs->mrs, param->EmcMrwExtra);
+	}
+}
+
+static void sdram_init_zq_calibration(const sdram_params_t124 *param,
+				      struct tegra_emc_regs *regs)
+{
+	if ((param->EmcZcalWarmColdBootEnables &
+	     EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK) == 1) {
+		/* Need to initialize ZCAL on coldboot. */
+		write32(&regs->zq_cal, param->EmcZcalInitDev0);
+		sleep(param->EmcZcalInitWait);
+
+		if ((param->EmcDevSelect & 2) == 0) {
+			write32(&regs->zq_cal, param->EmcZcalInitDev1);
+			sleep(param->EmcZcalInitWait);
+		}
+	} else {
+		sleep(param->EmcZcalInitWait);
+	}
+}
+
+static void sdram_set_zq_calibration(const sdram_params_t124 *param,
+				     struct tegra_emc_regs *regs)
+{
+	/* Start periodic ZQ calibration */
+	write32(&regs->zcal_interval, param->EmcZcalInterval);
+	write32(&regs->zcal_wait_cnt, param->EmcZcalWaitCnt);
+	write32(&regs->zcal_mrw_cmd, param->EmcZcalMrwCmd);
+}
+
+static void sdram_set_refresh(const sdram_params_t124 *param,
+			      struct tegra_emc_regs *regs)
+{
+	/* Insert burst refresh */
+	if (param->EmcExtraRefreshNum > 0) {
+		u32 refresh_num = (1 << param->EmcExtraRefreshNum) - 1;
+		writebits((EMC_REF_CMD_REFRESH | EMC_REF_NORMAL_ENABLED |
+			   (refresh_num << EMC_REF_NUM_SHIFT) |
+			   (param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT)),
+			  &regs->ref, (EMC_REF_CMD_MASK | EMC_REF_NORMAL_MASK |
+				       EMC_REF_NUM_MASK |
+				       EMC_REF_DEV_SELECTN_MASK));
+	}
+
+	/* Enable refresh */
+	write32(&regs->refctrl,
+		(param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED));
+
+	write32(&regs->dyn_self_ref_control, param->EmcDynSelfRefControl);
+	write32(&regs->cfg, param->EmcCfg);
+	write32(&regs->sel_dpd_ctrl, param->EmcSelDpdCtrl);
+
+	/* Write addr swizzle lock bit */
+	write32(&regs->fbio_spare, param->EmcFbioSpare);
+
+	/* Re-trigger timing to latch power saving functions */
+	sdram_trigger_emc_timing_update(regs);
+}
+
+static void sdram_enable_arbiter(const sdram_params_t124 *param)
+{
+	/* TODO(hungte) Move values here to standalone header file. */
+	u32 *AHB_ARBITRATION_XBAR_CTRL = (u32*)(0x6000c000 + 0xe0);
+	setbits32(AHB_ARBITRATION_XBAR_CTRL,
+		  param->AhbArbitrationXbarCtrlMemInitDone << 16);
+}
+
+static void sdram_lock_carveouts(const sdram_params_t124 *param,
+				 struct tegra_mc_regs *regs)
+{
+	/* Lock carveouts, and emem_cfg registers */
+	write32(&regs->video_protect_reg_ctrl,
+		param->McVideoProtectWriteAccess);
+	write32(&regs->emem_cfg_access_ctrl,
+		MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED);
+	write32(&regs->sec_carveout_reg_ctrl,
+		param->McSecCarveoutProtectWriteAccess);
+	write32(&regs->mts_carveout_reg_ctrl, param->McMtsCarveoutRegCtrl);
+}
+/* CRC_OSC_CTRL_0 0x50 */
+#define OSC_FREQ_SHIFT			28
+#define OSC_FREQ_MASK			(0xf << OSC_FREQ_SHIFT)
+#define OSC_PREDIV_SHIFT		26
+#define OSC_PREDIV_MASK			(0x3 << OSC_PREDIV_SHIFT)
+#define OSC_XOFS_SHIFT			4
+#define OSC_XOFS_MASK			(0x3F << OSC_XOFS_SHIFT)
+#define OSC_DRIVE_STRENGTH		7
+#define OSC_XOBP			(1 << 1)
+#define OSC_XOE				(1 << 0)
+int clock_get_pll_input_khz(void)
+{
+	u32 osc_ctrl = CLOCK(0x50);
+	u32 osc_bits = (osc_ctrl & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+	u32 pll_ref_div = (osc_ctrl & OSC_PREDIV_MASK) >> OSC_PREDIV_SHIFT;
+	return 12000 >> pll_ref_div;
+}
+
+
+
+
+void sdram_init()
+{
+	const sdram_params_t124 *param=sdram_get_params_t124();
+	struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)PMC_BASE;
+	struct tegra_mc_regs *mc = (struct tegra_mc_regs*)MC_BASE;
+	struct tegra_emc_regs *emc = (struct tegra_emc_regs*)EMC_BASE;
+
+	printf_("Initializing SDRAM of type %d with %dKHz\n",
+		param->MemoryType, clock_get_pll_input_khz() *
+		param->PllMFeedbackDivider / param->PllMInputDivider /
+		(1 + param->PllMSelectDiv2));
+	if (param->MemoryType != MEMORY_TYPE_DDR3)
+		printf_("Unsupported memory type!\n");
+
+	sdram_configure_pmc(param, pmc);
+	sdram_patch(param->EmcBctSpare0, param->EmcBctSpare1);
+
+	sdram_start_clocks(param);
+	sdram_patch(param->EmcBctSpare2, param->EmcBctSpare3);
+
+	sdram_deassert_sel_dpd(param, pmc);
+	sdram_set_swizzle(param, emc);
+	sdram_set_pad_controls(param, emc);
+	sdram_patch(param->EmcBctSpare4, param->EmcBctSpare5);
+
+
+
+	sdram_trigger_emc_timing_update(emc);
+	sdram_init_mc(param, mc);
+	sdram_init_emc(param, emc);
+	sdram_patch(param->EmcBctSpare6, param->EmcBctSpare7);
+
+
+	sdram_set_emc_timing(param, emc);
+	sdram_patch_bootrom(param, mc);
+	sdram_set_dpd3(param, pmc);
+	sdram_set_dli_trims(param, emc);
+	sdram_deassert_clock_enable_signal(param, pmc);
+	sdram_set_clock_enable_signal(param, emc);
+	sdram_init_zq_calibration(param, emc);
+	sdram_patch(param->EmcBctSpare8, param->EmcBctSpare9);
+
+
+	sdram_set_zq_calibration(param, emc);
+	sdram_patch(param->EmcBctSpare10, param->EmcBctSpare11);
+
+	sdram_trigger_emc_timing_update(emc);
+	sdram_set_refresh(param, emc);
+	sdram_enable_arbiter(param);
+	sdram_lock_carveouts(param, mc);
+
+	sdram_lp0_save_params(param);
+}
+
+u32 sdram_get_ram_code(void)
+{
+	struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)PMC_BASE;
+	return ((read32(&pmc->strapping_opt_a) &
+		 PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >>
+		PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT);
+}
+
+
+
--- a/loader/sdram.h
+++ b/loader/sdram.h
@ -0,0 +1,792 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018 balika011
+ * Copyright (c) 2019-2023 CTCaer
+ * Copyright (c) 2024 hydrogenium2020-offical
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _T124_SDRAM_H_
+#define _T124_SDRAM_H_
+
+#include "types.h"
+
+#define MEMORY_TYPE_NONE   0
+#define MEMORY_TYPE_DDR    0
+#define MEMORY_TYPE_LPDDR  0
+#define MEMORY_TYPE_DDR2   0
+#define MEMORY_TYPE_LPDDR2 1
+#define MEMORY_TYPE_DDR3  2
+
+enum {
+	BOOT_ROM_PATCH_CONTROL_ENABLE_MASK = 0x1 << 31,
+	BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT = 0,
+	BOOT_ROM_PATCH_CONTROL_OFFSET_MASK = 0x7FFFFFFF << 0,
+	BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS = 0x70000000,
+
+	EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK = 1 << 0,
+};
+
+/**
+ * Defines the SDRAM parameter structure
+ */
+typedef struct _sdram_params_t124 {
+
+	/* Specifies the type of memory device */
+	u32 MemoryType;
+
+	/* MC/EMC clock source configuration */
+
+	/* Specifies the M value for PllM */
+	u32 PllMInputDivider;
+	/* Specifies the N value for PllM */
+	u32 PllMFeedbackDivider;
+	/* Specifies the time to wait for PLLM to lock (in microseconds) */
+	u32 PllMStableTime;
+	/* Specifies misc. control bits */
+	u32 PllMSetupControl;
+	/* Enables the Div by 2 */
+	u32 PllMSelectDiv2;
+	/* Powers down VCO output Level shifter */
+	u32 PllMPDLshiftPh45;
+	/* Powers down VCO output Level shifter */
+	u32 PllMPDLshiftPh90;
+	/* Powers down VCO output Level shifter */
+	u32 PllMPDLshiftPh135;
+	/* Specifies value for Charge Pump Gain Control */
+	u32 PllMKCP;
+	/* Specifies VCO gain */
+	u32 PllMKVCO;
+	/* Spare BCT param */
+	u32 EmcBctSpare0;
+	/* Spare BCT param */
+	u32 EmcBctSpare1;
+	/* Spare BCT param */
+	u32 EmcBctSpare2;
+	/* Spare BCT param */
+	u32 EmcBctSpare3;
+	/* Spare BCT param */
+	u32 EmcBctSpare4;
+	/* Spare BCT param */
+	u32 EmcBctSpare5;
+	/* Spare BCT param */
+	u32 EmcBctSpare6;
+	/* Spare BCT param */
+	u32 EmcBctSpare7;
+	/* Spare BCT param */
+	u32 EmcBctSpare8;
+	/* Spare BCT param */
+	u32 EmcBctSpare9;
+	/* Spare BCT param */
+	u32 EmcBctSpare10;
+	/* Spare BCT param */
+	u32 EmcBctSpare11;
+	/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
+	u32 EmcClockSource;
+
+	/* Auto-calibration of EMC pads */
+
+	/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
+	u32 EmcAutoCalInterval;
+	/*
+	 * Specifies the value for EMC_AUTO_CAL_CONFIG
+	 * Note: Trigger bits are set by the SDRAM code.
+	 */
+	u32 EmcAutoCalConfig;
+
+	/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
+	u32 EmcAutoCalConfig2;
+
+	/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
+	u32 EmcAutoCalConfig3;
+
+	/*
+	 * Specifies the time for the calibration
+	 * to stabilize (in microseconds)
+	 */
+	u32 EmcAutoCalWait;
+
+	/*
+	 * DRAM size information
+	 * Specifies the value for EMC_ADR_CFG
+	 */
+	u32 EmcAdrCfg;
+
+	/*
+	 * Specifies the time to wait after asserting pin
+	 * CKE (in microseconds)
+	 */
+	u32 EmcPinProgramWait;
+	/* Specifies the extra delay before/after pin RESET/CKE command */
+	u32 EmcPinExtraWait;
+	/*
+	 * Specifies the extra delay after the first writing
+	 * of EMC_TIMING_CONTROL
+	 */
+	u32 EmcTimingControlWait;
+
+	/* Timing parameters required for the SDRAM */
+
+	/* Specifies the value for EMC_RC */
+	u32 EmcRc;
+	/* Specifies the value for EMC_RFC */
+	u32 EmcRfc;
+	/* Specifies the value for EMC_RFC_SLR */
+	u32 EmcRfcSlr;
+	/* Specifies the value for EMC_RAS */
+	u32 EmcRas;
+	/* Specifies the value for EMC_RP */
+	u32 EmcRp;
+	/* Specifies the value for EMC_R2R */
+	u32 EmcR2r;
+	/* Specifies the value for EMC_W2W */
+	u32 EmcW2w;
+	/* Specifies the value for EMC_R2W */
+	u32 EmcR2w;
+	/* Specifies the value for EMC_W2R */
+	u32 EmcW2r;
+	/* Specifies the value for EMC_R2P */
+	u32 EmcR2p;
+	/* Specifies the value for EMC_W2P */
+	u32 EmcW2p;
+	/* Specifies the value for EMC_RD_RCD */
+	u32 EmcRdRcd;
+	/* Specifies the value for EMC_WR_RCD */
+	u32 EmcWrRcd;
+	/* Specifies the value for EMC_RRD */
+	u32 EmcRrd;
+	/* Specifies the value for EMC_REXT */
+	u32 EmcRext;
+	/* Specifies the value for EMC_WEXT */
+	u32 EmcWext;
+	/* Specifies the value for EMC_WDV */
+	u32 EmcWdv;
+	/* Specifies the value for EMC_WDV_MASK */
+	u32 EmcWdvMask;
+	/* Specifies the value for EMC_QUSE */
+	u32 EmcQUse;
+	/* Specifies the value for EMC_QUSE_WIDTH */
+	u32 EmcQuseWidth;
+	/* Specifies the value for EMC_IBDLY */
+	u32 EmcIbdly;
+	/* Specifies the value for EMC_EINPUT */
+	u32 EmcEInput;
+	/* Specifies the value for EMC_EINPUT_DURATION */
+	u32 EmcEInputDuration;
+	/* Specifies the value for EMC_PUTERM_EXTRA */
+	u32 EmcPutermExtra;
+	/* Specifies the value for EMC_PUTERM_WIDTH */
+	u32 EmcPutermWidth;
+	/* Specifies the value for EMC_PUTERM_ADJ */
+	u32 EmcPutermAdj;
+	/* Specifies the value for EMC_CDB_CNTL_1 */
+	u32 EmcCdbCntl1;
+	/* Specifies the value for EMC_CDB_CNTL_2 */
+	u32 EmcCdbCntl2;
+	/* Specifies the value for EMC_CDB_CNTL_3 */
+	u32 EmcCdbCntl3;
+	/* Specifies the value for EMC_QRST */
+	u32 EmcQRst;
+	/* Specifies the value for EMC_QSAFE */
+	u32 EmcQSafe;
+	/* Specifies the value for EMC_RDV */
+	u32 EmcRdv;
+	/* Specifies the value for EMC_RDV_MASK */
+	u32 EmcRdvMask;
+	/* Specifies the value for EMC_QPOP */
+	u32 EmcQpop;
+	/* Specifies the value for EMC_CTT */
+	u32 EmcCtt;
+	/* Specifies the value for EMC_CTT_DURATION */
+	u32 EmcCttDuration;
+	/* Specifies the value for EMC_REFRESH */
+	u32 EmcRefresh;
+	/* Specifies the value for EMC_BURST_REFRESH_NUM */
+	u32 EmcBurstRefreshNum;
+	/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
+	u32 EmcPreRefreshReqCnt;
+	/* Specifies the value for EMC_PDEX2WR */
+	u32 EmcPdEx2Wr;
+	/* Specifies the value for EMC_PDEX2RD */
+	u32 EmcPdEx2Rd;
+	/* Specifies the value for EMC_PCHG2PDEN */
+	u32 EmcPChg2Pden;
+	/* Specifies the value for EMC_ACT2PDEN */
+	u32 EmcAct2Pden;
+	/* Specifies the value for EMC_AR2PDEN */
+	u32 EmcAr2Pden;
+	/* Specifies the value for EMC_RW2PDEN */
+	u32 EmcRw2Pden;
+	/* Specifies the value for EMC_TXSR */
+	u32 EmcTxsr;
+	/* Specifies the value for EMC_TXSRDLL */
+	u32 EmcTxsrDll;
+	/* Specifies the value for EMC_TCKE */
+	u32 EmcTcke;
+	/* Specifies the value for EMC_TCKESR */
+	u32 EmcTckesr;
+	/* Specifies the value for EMC_TPD */
+	u32 EmcTpd;
+	/* Specifies the value for EMC_TFAW */
+	u32 EmcTfaw;
+	/* Specifies the value for EMC_TRPAB */
+	u32 EmcTrpab;
+	/* Specifies the value for EMC_TCLKSTABLE */
+	u32 EmcTClkStable;
+	/* Specifies the value for EMC_TCLKSTOP */
+	u32 EmcTClkStop;
+	/* Specifies the value for EMC_TREFBW */
+	u32 EmcTRefBw;
+
+	/* FBIO configuration values */
+
+	/* Specifies the value for EMC_FBIO_CFG5 */
+	u32 EmcFbioCfg5;
+	/* Specifies the value for EMC_FBIO_CFG6 */
+	u32 EmcFbioCfg6;
+	/* Specifies the value for EMC_FBIO_SPARE */
+	u32 EmcFbioSpare;
+
+	/* Specifies the value for EMC_CFG_RSV */
+	u32 EmcCfgRsv;
+
+	/* MRS command values */
+
+	/* Specifies the value for EMC_MRS */
+	u32 EmcMrs;
+	/* Specifies the MP0 command to initialize mode registers */
+	u32 EmcEmrs;
+	/* Specifies the MP2 command to initialize mode registers */
+	u32 EmcEmrs2;
+	/* Specifies the MP3 command to initialize mode registers */
+	u32 EmcEmrs3;
+	/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
+	u32 EmcMrw1;
+	/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
+	u32 EmcMrw2;
+	/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
+	u32 EmcMrw3;
+	/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
+	u32 EmcMrw4;
+	/*
+	 * Specifies the programming to extra LPDDR2 Mode Register
+	 * at cold boot
+	 */
+	u32 EmcMrwExtra;
+	/*
+	 * Specifies the programming to extra LPDDR2 Mode Register
+	 * at warm boot
+	 */
+	u32 EmcWarmBootMrwExtra;
+	/*
+	 * Specify the enable of extra Mode Register programming at
+	 * warm boot
+	 */
+	u32 EmcWarmBootExtraModeRegWriteEnable;
+	/*
+	 * Specify the enable of extra Mode Register programming at
+	 * cold boot
+	 */
+	u32 EmcExtraModeRegWriteEnable;
+
+	/* Specifies the EMC_MRW reset command value */
+	u32 EmcMrwResetCommand;
+	/* Specifies the EMC Reset wait time (in microseconds) */
+	u32 EmcMrwResetNInitWait;
+	/* Specifies the value for EMC_MRS_WAIT_CNT */
+	u32 EmcMrsWaitCnt;
+	/* Specifies the value for EMC_MRS_WAIT_CNT2 */
+	u32 EmcMrsWaitCnt2;
+
+	/* EMC miscellaneous configurations */
+
+	/* Specifies the value for EMC_CFG */
+	u32 EmcCfg;
+	/* Specifies the value for EMC_CFG_2 */
+	u32 EmcCfg2;
+	/* Specifies the pipe bypass controls */
+	u32 EmcCfgPipe;
+	/* Specifies the value for EMC_DBG */
+	u32 EmcDbg;
+	/* Specifies the value for EMC_CMDQ */
+	u32 EmcCmdQ;
+	/* Specifies the value for EMC_MC2EMCQ */
+	u32 EmcMc2EmcQ;
+	/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
+	u32 EmcDynSelfRefControl;
+
+	/* Specifies the value for MEM_INIT_DONE */
+	u32 AhbArbitrationXbarCtrlMemInitDone;
+
+	/* Specifies the value for EMC_CFG_DIG_DLL */
+	u32 EmcCfgDigDll;
+	/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
+	u32 EmcCfgDigDllPeriod;
+	/* Specifies the value of *DEV_SELECTN of various EMC registers */
+	u32 EmcDevSelect;
+
+	/* Specifies the value for EMC_SEL_DPD_CTRL */
+	u32 EmcSelDpdCtrl;
+
+	/* Pads trimmer delays */
+
+	/* Specifies the value for EMC_DLL_XFORM_DQS0 */
+	u32 EmcDllXformDqs0;
+	/* Specifies the value for EMC_DLL_XFORM_DQS1 */
+	u32 EmcDllXformDqs1;
+	/* Specifies the value for EMC_DLL_XFORM_DQS2 */
+	u32 EmcDllXformDqs2;
+	/* Specifies the value for EMC_DLL_XFORM_DQS3 */
+	u32 EmcDllXformDqs3;
+	/* Specifies the value for EMC_DLL_XFORM_DQS4 */
+	u32 EmcDllXformDqs4;
+	/* Specifies the value for EMC_DLL_XFORM_DQS5 */
+	u32 EmcDllXformDqs5;
+	/* Specifies the value for EMC_DLL_XFORM_DQS6 */
+	u32 EmcDllXformDqs6;
+	/* Specifies the value for EMC_DLL_XFORM_DQS7 */
+	u32 EmcDllXformDqs7;
+	/* Specifies the value for EMC_DLL_XFORM_DQS8 */
+	u32 EmcDllXformDqs8;
+	/* Specifies the value for EMC_DLL_XFORM_DQS9 */
+	u32 EmcDllXformDqs9;
+	/* Specifies the value for EMC_DLL_XFORM_DQS10 */
+	u32 EmcDllXformDqs10;
+	/* Specifies the value for EMC_DLL_XFORM_DQS11 */
+	u32 EmcDllXformDqs11;
+	/* Specifies the value for EMC_DLL_XFORM_DQS12 */
+	u32 EmcDllXformDqs12;
+	/* Specifies the value for EMC_DLL_XFORM_DQS13 */
+	u32 EmcDllXformDqs13;
+	/* Specifies the value for EMC_DLL_XFORM_DQS14 */
+	u32 EmcDllXformDqs14;
+	/* Specifies the value for EMC_DLL_XFORM_DQS15 */
+	u32 EmcDllXformDqs15;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE0 */
+	u32 EmcDllXformQUse0;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE1 */
+	u32 EmcDllXformQUse1;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE2 */
+	u32 EmcDllXformQUse2;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE3 */
+	u32 EmcDllXformQUse3;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE4 */
+	u32 EmcDllXformQUse4;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE5 */
+	u32 EmcDllXformQUse5;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE6 */
+	u32 EmcDllXformQUse6;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE7 */
+	u32 EmcDllXformQUse7;
+	/* Specifies the value for EMC_DLL_XFORM_ADDR0 */
+	u32 EmcDllXformAddr0;
+	/* Specifies the value for EMC_DLL_XFORM_ADDR1 */
+	u32 EmcDllXformAddr1;
+	/* Specifies the value for EMC_DLL_XFORM_ADDR2 */
+	u32 EmcDllXformAddr2;
+	/* Specifies the value for EMC_DLL_XFORM_ADDR3 */
+	u32 EmcDllXformAddr3;
+	/* Specifies the value for EMC_DLL_XFORM_ADDR4 */
+	u32 EmcDllXformAddr4;
+	/* Specifies the value for EMC_DLL_XFORM_ADDR5 */
+	u32 EmcDllXformAddr5;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE8 */
+	u32 EmcDllXformQUse8;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE9 */
+	u32 EmcDllXformQUse9;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE10 */
+	u32 EmcDllXformQUse10;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE11 */
+	u32 EmcDllXformQUse11;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE12 */
+	u32 EmcDllXformQUse12;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE13 */
+	u32 EmcDllXformQUse13;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE14 */
+	u32 EmcDllXformQUse14;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE15 */
+	u32 EmcDllXformQUse15;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS0 */
+	u32 EmcDliTrimTxDqs0;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS1 */
+	u32 EmcDliTrimTxDqs1;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS2 */
+	u32 EmcDliTrimTxDqs2;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS3 */
+	u32 EmcDliTrimTxDqs3;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS4 */
+	u32 EmcDliTrimTxDqs4;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS5 */
+	u32 EmcDliTrimTxDqs5;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS6 */
+	u32 EmcDliTrimTxDqs6;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS7 */
+	u32 EmcDliTrimTxDqs7;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS8 */
+	u32 EmcDliTrimTxDqs8;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS9 */
+	u32 EmcDliTrimTxDqs9;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS10 */
+	u32 EmcDliTrimTxDqs10;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS11 */
+	u32 EmcDliTrimTxDqs11;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS12 */
+	u32 EmcDliTrimTxDqs12;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS13 */
+	u32 EmcDliTrimTxDqs13;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS14 */
+	u32 EmcDliTrimTxDqs14;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS15 */
+	u32 EmcDliTrimTxDqs15;
+	/* Specifies the value for EMC_DLL_XFORM_DQ0 */
+	u32 EmcDllXformDq0;
+	/* Specifies the value for EMC_DLL_XFORM_DQ1 */
+	u32 EmcDllXformDq1;
+	/* Specifies the value for EMC_DLL_XFORM_DQ2 */
+	u32 EmcDllXformDq2;
+	/* Specifies the value for EMC_DLL_XFORM_DQ3 */
+	u32 EmcDllXformDq3;
+	/* Specifies the value for EMC_DLL_XFORM_DQ4 */
+	u32 EmcDllXformDq4;
+	/* Specifies the value for EMC_DLL_XFORM_DQ5 */
+	u32 EmcDllXformDq5;
+	/* Specifies the value for EMC_DLL_XFORM_DQ6 */
+	u32 EmcDllXformDq6;
+	/* Specifies the value for EMC_DLL_XFORM_DQ7 */
+	u32 EmcDllXformDq7;
+
+	/*
+	 * Specifies the delay after asserting CKE pin during a WarmBoot0
+	 * sequence (in microseconds)
+	 */
+	u32 WarmBootWait;
+
+	/* Specifies the value for EMC_CTT_TERM_CTRL */
+	u32 EmcCttTermCtrl;
+
+	/* Specifies the value for EMC_ODT_WRITE */
+	u32 EmcOdtWrite;
+	/* Specifies the value for EMC_ODT_WRITE */
+	u32 EmcOdtRead;
+
+	/* Periodic ZQ calibration */
+
+	/*
+	 * Specifies the value for EMC_ZCAL_INTERVAL
+	 * Value 0 disables ZQ calibration
+	 */
+	u32 EmcZcalInterval;
+	/* Specifies the value for EMC_ZCAL_WAIT_CNT */
+	u32 EmcZcalWaitCnt;
+	/* Specifies the value for EMC_ZCAL_MRW_CMD */
+	u32 EmcZcalMrwCmd;
+
+	/* DRAM initialization sequence flow control */
+
+	/* Specifies the MRS command value for resetting DLL */
+	u32 EmcMrsResetDll;
+	/* Specifies the command for ZQ initialization of device 0 */
+	u32 EmcZcalInitDev0;
+	/* Specifies the command for ZQ initialization of device 1 */
+	u32 EmcZcalInitDev1;
+	/*
+	 * Specifies the wait time after programming a ZQ initialization
+	 * command (in microseconds)
+	 */
+	u32 EmcZcalInitWait;
+	/*
+	 * Specifies the enable for ZQ calibration at cold boot [bit 0]
+	 * and warm boot [bit 1]
+	 */
+	u32 EmcZcalWarmColdBootEnables;
+
+	/*
+	 * Specifies the MRW command to LPDDR2 for ZQ calibration
+	 * on warmboot
+	 */
+	/* Is issued to both devices separately */
+	u32 EmcMrwLpddr2ZcalWarmBoot;
+	/*
+	 * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
+	 * Is issued to both devices separately
+	 */
+	u32 EmcZqCalDdr3WarmBoot;
+	/*
+	 * Specifies the wait time for ZQ calibration on warmboot
+	 * (in microseconds)
+	 */
+	u32 EmcZcalWarmBootWait;
+	/*
+	 * Specifies the enable for DRAM Mode Register programming
+	 * at warm boot
+	 */
+	u32 EmcMrsWarmBootEnable;
+	/*
+	 * Specifies the wait time after sending an MRS DLL reset command
+	 * in microseconds)
+	 */
+	u32 EmcMrsResetDllWait;
+	/* Specifies the extra MRS command to initialize mode registers */
+	u32 EmcMrsExtra;
+	/* Specifies the extra MRS command at warm boot */
+	u32 EmcWarmBootMrsExtra;
+	/* Specifies the EMRS command to enable the DDR2 DLL */
+	u32 EmcEmrsDdr2DllEnable;
+	/* Specifies the MRS command to reset the DDR2 DLL */
+	u32 EmcMrsDdr2DllReset;
+	/* Specifies the EMRS command to set OCD calibration */
+	u32 EmcEmrsDdr2OcdCalib;
+	/*
+	 * Specifies the wait between initializing DDR and setting OCD
+	 * calibration (in microseconds)
+	 */
+	u32 EmcDdr2Wait;
+	/* Specifies the value for EMC_CLKEN_OVERRIDE */
+	u32 EmcClkenOverride;
+	/* Specifies the value for MC_DIS_EXTRA_SNAP_LEVELS */
+	u32 McDisExtraSnapLevels;
+	/*
+	 * Specifies LOG2 of the extra refresh numbers after booting
+	 * Program 0 to disable
+	 */
+	u32 EmcExtraRefreshNum;
+	/* Specifies the master override for all EMC clocks */
+	u32 EmcClkenOverrideAllWarmBoot;
+	/* Specifies the master override for all MC clocks */
+	u32 McClkenOverrideAllWarmBoot;
+	/* Specifies digital dll period, choosing between 4 to 64 ms */
+	u32 EmcCfgDigDllPeriodWarmBoot;
+
+	/* Pad controls */
+
+	/* Specifies the value for PMC_VDDP_SEL */
+	u32 PmcVddpSel;
+	/* Specifies the wait time after programming PMC_VDDP_SEL */
+	u32 PmcVddpSelWait;
+	/* Specifies the value for PMC_DDR_PWR */
+	u32 PmcDdrPwr;
+	/* Specifies the value for PMC_DDR_CFG */
+	u32 PmcDdrCfg;
+	/* Specifies the value for PMC_IO_DPD3_REQ */
+	u32 PmcIoDpd3Req;
+	/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
+	u32 PmcIoDpd3ReqWait;
+	/* Specifies the value for PMC_REG_SHORT */
+	u32 PmcRegShort;
+	/* Specifies the value for PMC_NO_IOPOWER */
+	u32 PmcNoIoPower;
+	/* Specifies the wait time after programming PMC_POR_DPD_CTRL */
+	u32 PmcPorDpdCtrlWait;
+	/* Specifies the value for EMC_XM2CMDPADCTRL */
+	u32 EmcXm2CmdPadCtrl;
+	/* Specifies the value for EMC_XM2CMDPADCTRL2 */
+	u32 EmcXm2CmdPadCtrl2;
+	/* Specifies the value for EMC_XM2CMDPADCTRL3 */
+	u32 EmcXm2CmdPadCtrl3;
+	/* Specifies the value for EMC_XM2CMDPADCTRL4 */
+	u32 EmcXm2CmdPadCtrl4;
+	/* Specifies the value for EMC_XM2CMDPADCTRL5 */
+	u32 EmcXm2CmdPadCtrl5;
+	/* Specifies the value for EMC_XM2DQSPADCTRL */
+	u32 EmcXm2DqsPadCtrl;
+	/* Specifies the value for EMC_XM2DQSPADCTRL2 */
+	u32 EmcXm2DqsPadCtrl2;
+	/* Specifies the value for EMC_XM2DQSPADCTRL3 */
+	u32 EmcXm2DqsPadCtrl3;
+	/* Specifies the value for EMC_XM2DQSPADCTRL4 */
+	u32 EmcXm2DqsPadCtrl4;
+	/* Specifies the value for EMC_XM2DQSPADCTRL5 */
+	u32 EmcXm2DqsPadCtrl5;
+	/* Specifies the value for EMC_XM2DQSPADCTRL6 */
+	u32 EmcXm2DqsPadCtrl6;
+	/* Specifies the value for EMC_XM2DQPADCTRL */
+	u32 EmcXm2DqPadCtrl;
+	/* Specifies the value for EMC_XM2DQPADCTRL2 */
+	u32 EmcXm2DqPadCtrl2;
+	/* Specifies the value for EMC_XM2DQPADCTRL3 */
+	u32 EmcXm2DqPadCtrl3;
+	/* Specifies the value for EMC_XM2CLKPADCTRL */
+	u32 EmcXm2ClkPadCtrl;
+	/* Specifies the value for EMC_XM2CLKPADCTRL2 */
+	u32 EmcXm2ClkPadCtrl2;
+	/* Specifies the value for EMC_XM2COMPPADCTRL */
+	u32 EmcXm2CompPadCtrl;
+	/* Specifies the value for EMC_XM2VTTGENPADCTRL */
+	u32 EmcXm2VttGenPadCtrl;
+	/* Specifies the value for EMC_XM2VTTGENPADCTRL2 */
+	u32 EmcXm2VttGenPadCtrl2;
+	/* Specifies the value for EMC_XM2VTTGENPADCTRL3 */
+	u32 EmcXm2VttGenPadCtrl3;
+	/* Specifies the value for EMC_ACPD_CONTROL */
+	u32 EmcAcpdControl;
+
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */
+	u32 EmcSwizzleRank0ByteCfg;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
+	u32 EmcSwizzleRank0Byte0;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
+	u32 EmcSwizzleRank0Byte1;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
+	u32 EmcSwizzleRank0Byte2;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
+	u32 EmcSwizzleRank0Byte3;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */
+	u32 EmcSwizzleRank1ByteCfg;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
+	u32 EmcSwizzleRank1Byte0;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
+	u32 EmcSwizzleRank1Byte1;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
+	u32 EmcSwizzleRank1Byte2;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
+	u32 EmcSwizzleRank1Byte3;
+
+	/* Specifies the value for EMC_DSR_VTTGEN_DRV */
+	u32 EmcDsrVttgenDrv;
+
+	/* Specifies the value for EMC_TXDSRVTTGEN */
+	u32 EmcTxdsrvttgen;
+	/* Specifies the value for EMC_BGBIAS_CTL */
+	u32 EmcBgbiasCtl0;
+
+	/* DRAM size information */
+
+	/* Specifies the value for MC_EMEM_ADR_CFG */
+	u32 McEmemAdrCfg;
+	/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
+	u32 McEmemAdrCfgDev0;
+	/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
+	u32 McEmemAdrCfgDev1;
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */
+	u32 McEmemAdrCfgBankMask0;
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
+	u32 McEmemAdrCfgBankMask1;
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
+	u32 McEmemAdrCfgBankMask2;
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG3 */
+	u32 McEmemAdrCfgBankSwizzle3;
+
+	/*
+	 * Specifies the value for MC_EMEM_CFG which holds the external memory
+	 * size (in KBytes)
+	 */
+	u32 McEmemCfg;
+
+	/* MC arbitration configuration */
+
+	/* Specifies the value for MC_EMEM_ARB_CFG */
+	u32 McEmemArbCfg;
+	/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
+	u32 McEmemArbOutstandingReq;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
+	u32 McEmemArbTimingRcd;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
+	u32 McEmemArbTimingRp;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
+	u32 McEmemArbTimingRc;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
+	u32 McEmemArbTimingRas;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
+	u32 McEmemArbTimingFaw;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
+	u32 McEmemArbTimingRrd;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
+	u32 McEmemArbTimingRap2Pre;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
+	u32 McEmemArbTimingWap2Pre;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
+	u32 McEmemArbTimingR2R;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
+	u32 McEmemArbTimingW2W;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
+	u32 McEmemArbTimingR2W;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
+	u32 McEmemArbTimingW2R;
+	/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
+	u32 McEmemArbDaTurns;
+	/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
+	u32 McEmemArbDaCovers;
+	/* Specifies the value for MC_EMEM_ARB_MISC0 */
+	u32 McEmemArbMisc0;
+	/* Specifies the value for MC_EMEM_ARB_MISC1 */
+	u32 McEmemArbMisc1;
+	/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
+	u32 McEmemArbRing1Throttle;
+	/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
+	u32 McEmemArbOverride;
+	/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
+	u32 McEmemArbOverride1;
+	/* Specifies the value for MC_EMEM_ARB_RSV */
+	u32 McEmemArbRsv;
+
+	/* Specifies the value for MC_CLKEN_OVERRIDE */
+	u32 McClkenOverride;
+
+	/* Specifies the value for MC_STAT_CONTROL */
+	u32 McStatControl;
+	/* Specifies the value for MC_DISPLAY_SNAP_RING */
+	u32 McDisplaySnapRing;
+	/* Specifies the value for MC_VIDEO_PROTECT_BOM */
+	u32 McVideoProtectBom;
+	/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
+	u32 McVideoProtectBomAdrHi;
+	/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
+	u32 McVideoProtectSizeMb;
+	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
+	u32 McVideoProtectVprOverride;
+	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
+	u32 McVideoProtectVprOverride1;
+	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
+	u32 McVideoProtectGpuOverride0;
+	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
+	u32 McVideoProtectGpuOverride1;
+	/* Specifies the value for MC_SEC_CARVEOUT_BOM */
+	u32 McSecCarveoutBom;
+	/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
+	u32 McSecCarveoutAdrHi;
+	/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
+	u32 McSecCarveoutSizeMb;
+	/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */
+	u32 McVideoProtectWriteAccess;
+	/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */
+	u32 McSecCarveoutProtectWriteAccess;
+
+	/* Specifies enable for CA training */
+	u32 EmcCaTrainingEnable;
+	/* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL1 */
+	u32 EmcCaTrainingTimingCntl1;
+	/* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL2 */
+	u32 EmcCaTrainingTimingCntl2;
+	/* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */
+	u32 SwizzleRankByteEncode;
+	/* Specifies enable and offset for patched boot ROM write */
+	u32 BootRomPatchControl;
+	/* Specifies data for patched boot ROM write */
+	u32 BootRomPatchData;
+	/* Specifies the value for MC_MTS_CARVEOUT_BOM */
+	u32 McMtsCarveoutBom;
+	/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
+	u32 McMtsCarveoutAdrHi;
+	/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
+	u32 McMtsCarveoutSizeMb;
+	/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
+	u32 McMtsCarveoutRegCtrl;
+
+	/* End of generated code by warmboot_code_gen */
+}sdram_params_t124;
+
+
+void sdram_init();
+void * sdram_get_params_t124();
+
+#endif
--- a/loader/sdram_config_h5tc4g63afr-rda-792mhz.inl
+++ b/loader/sdram_config_h5tc4g63afr-rda-792mhz.inl
@ -0,0 +1,334 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2020-2022 CTCaer
+ * Copyright (c) 2024 hydrogenium2020-offical
+ * 
+ * This program is free software, you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY, without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+//In T210 this value is 1896
+#define DRAM_CFG_T124_SIZE 1236
+
+static const sdram_params_t124 dram_cfg_4gb_h5tc4g63afr_rda_792mhz = {
+    .MemoryType                               = MEMORY_TYPE_DDR3,
+    .PllMInputDivider                         = 0x00000001,
+    .PllMFeedbackDivider                      = 0x00000042,
+    .PllMStableTime                           = 0x0000012c,
+    .PllMSetupControl                         = 0x00000000,
+    .PllMSelectDiv2                           = 0x00000000,
+    .PllMPDLshiftPh45                         = 0x00000001,
+    .PllMPDLshiftPh90                         = 0x00000001,
+    .PllMPDLshiftPh135                        = 0x00000001,
+    .PllMKCP                                  = 0x00000000,
+    .PllMKVCO                                 = 0x00000000,
+    .EmcBctSpare0                             = 0x00000000,
+    .EmcBctSpare1                             = 0x00000000,
+    .EmcBctSpare2                             = 0x00000000,
+    .EmcBctSpare3                             = 0x00000000,
+    .EmcBctSpare4                             = 0x00000000,
+    .EmcBctSpare5                             = 0x00000000,
+    .EmcBctSpare6                             = 0x00000000,
+    .EmcBctSpare7                             = 0x00000000,
+    .EmcBctSpare8                             = 0x00000000,
+    .EmcBctSpare9                             = 0x00000000,
+    .EmcBctSpare10                            = 0x00000000,
+    .EmcBctSpare11                            = 0x00000000,
+    .EmcClockSource                           = 0x80000000,
+    .EmcAutoCalInterval                       = 0x001fffff,
+    .EmcAutoCalConfig                         = 0xa1430000,
+    .EmcAutoCalConfig2                        = 0x00000000,
+    .EmcAutoCalConfig3                        = 0x00000000,
+    .EmcAutoCalWait                           = 0x00000190,
+    .EmcAdrCfg                                = 0x00000000,
+    .EmcPinProgramWait                        = 0x00000001,
+    .EmcPinExtraWait                          = 0x00000000,
+    .EmcTimingControlWait                     = 0x00000000,
+    .EmcRc                                    = 0x00000025,
+    .EmcRfc                                   = 0x000000cd,
+    .EmcRfcSlr                                = 0x00000000,
+    .EmcRas                                   = 0x00000019,
+    .EmcRp                                    = 0x0000000a,
+    .EmcR2r                                   = 0x00000000,
+    .EmcW2w                                   = 0x00000000,
+    .EmcR2w                                   = 0x00000007,
+    .EmcW2r                                   = 0x0000000d,
+    .EmcR2p                                   = 0x00000004,
+    .EmcW2p                                   = 0x00000013,
+    .EmcRdRcd                                 = 0x0000000a,
+    .EmcWrRcd                                 = 0x0000000a,
+    .EmcRrd                                   = 0x00000003,
+    .EmcRext                                  = 0x00000002,
+    .EmcWext                                  = 0x00000000,
+    .EmcWdv                                   = 0x00000006,
+    .EmcWdvMask                               = 0x00000006,
+    .EmcQUse                                  = 0x0000000b,
+    .EmcQuseWidth                             = 0x00000002,
+    .EmcIbdly                                 = 0x00000000,
+    .EmcEInput                                = 0x00000003,
+    .EmcEInputDuration                        = 0x0000000c,
+    .EmcPutermExtra                           = 0x00090000,
+    .EmcPutermWidth                           = 0x00000004,
+    .EmcPutermAdj                             = 0x00000000,
+    .EmcCdbCntl1                              = 0x00000000,
+    .EmcCdbCntl2                              = 0x00000000,
+    .EmcCdbCntl3                              = 0x00000000,
+    .EmcQRst                                  = 0x00000002,
+    .EmcQSafe                                 = 0x00000012,
+    .EmcRdv                                   = 0x00000017,
+    .EmcRdvMask                               = 0x00000019,
+    .EmcQpop                                  = 0x0000000f,
+    .EmcCtt                                   = 0x00000000,
+    .EmcCttDuration                           = 0x00000004,
+    .EmcRefresh                               = 0x000017eb,
+    .EmcBurstRefreshNum                       = 0x00000000,
+    .EmcPreRefreshReqCnt                      = 0x000005fa,
+    .EmcPdEx2Wr                               = 0x00000003,
+    .EmcPdEx2Rd                               = 0x00000003,
+    .EmcPChg2Pden                             = 0x00000001,
+    .EmcAct2Pden                              = 0x00000000,
+    .EmcAr2Pden                               = 0x000000c7,
+    .EmcRw2Pden                               = 0x00000018,
+    .EmcTxsr                                  = 0x000000d7,
+    .EmcTxsrDll                               = 0x00000200,
+    .EmcTcke                                  = 0x00000005,
+    .EmcTckesr                                = 0x00000006,
+    .EmcTpd                                   = 0x00000005,
+    .EmcTfaw                                  = 0x0000001d,
+    .EmcTrpab                                 = 0x00000000,
+    .EmcTClkStable                            = 0x00000008,
+    .EmcTClkStop                              = 0x00000008,
+    .EmcTRefBw                                = 0x0000182c,
+    .EmcFbioCfg5                              = 0x1049b898,
+    .EmcFbioCfg6                              = 0x00000002,
+    .EmcFbioSpare                             = 0x00000000,
+    .EmcCfgRsv                                = 0xff00ff00,
+    .EmcMrs                                   = 0x80001d71,
+    .EmcEmrs                                  = 0x80100002,
+    .EmcEmrs2                                 = 0x80200018,
+    .EmcEmrs3                                 = 0x80300000,
+    .EmcMrw1                                  = 0x00000000,
+    .EmcMrw2                                  = 0x00000000,
+    .EmcMrw3                                  = 0x00000000,
+    .EmcMrw4                                  = 0x00000000,
+    .EmcMrwExtra                              = 0x00000000,
+    .EmcWarmBootMrwExtra                      = 0x00000000,
+    .EmcWarmBootExtraModeRegWriteEnable       = 0x00000000,
+    .EmcExtraModeRegWriteEnable               = 0x00000000,
+    .EmcMrwResetCommand                       = 0x00000000,
+    .EmcMrwResetNInitWait                     = 0x00000000,
+    .EmcMrsWaitCnt                            = 0x00f7000e,
+    .EmcMrsWaitCnt2                           = 0x00f7000e,
+    .EmcCfg                                   = 0x73300000,
+    .EmcCfg2                                  = 0x0000089d,
+    .EmcCfgPipe                               = 0x000040a0,
+    .EmcDbg                                   = 0x01000c00,
+    .EmcCmdQ                                  = 0x10004408,
+    .EmcMc2EmcQ                               = 0x06000404,
+    .EmcDynSelfRefControl                     = 0x80003025,
+    .AhbArbitrationXbarCtrlMemInitDone        = 0x00000001,
+    .EmcCfgDigDll                             = 0xe00701b1,
+    .EmcCfgDigDllPeriod                       = 0x00008000,
+    .EmcDevSelect                             = 0x00000002,
+    .EmcSelDpdCtrl                            = 0x00040000,
+    .EmcDllXformDqs0                          = 0x00000008,
+    .EmcDllXformDqs1                          = 0x00000008,
+    .EmcDllXformDqs2                          = 0x00000008,
+    .EmcDllXformDqs3                          = 0x00000008,
+    .EmcDllXformDqs4                          = 0x00000008,
+    .EmcDllXformDqs5                          = 0x00000008,
+    .EmcDllXformDqs6                          = 0x00000008,
+    .EmcDllXformDqs7                          = 0x00000008,
+    .EmcDllXformDqs8                          = 0x00000008,
+    .EmcDllXformDqs9                          = 0x00000008,
+    .EmcDllXformDqs10                         = 0x00000008,
+    .EmcDllXformDqs11                         = 0x00000008,
+    .EmcDllXformDqs12                         = 0x00000008,
+    .EmcDllXformDqs13                         = 0x00000008,
+    .EmcDllXformDqs14                         = 0x00000008,
+    .EmcDllXformDqs15                         = 0x00000008,
+    .EmcDllXformQUse0                         = 0x00000000,
+    .EmcDllXformQUse1                         = 0x00000000,
+    .EmcDllXformQUse2                         = 0x00000000,
+    .EmcDllXformQUse3                         = 0x00000000,
+    .EmcDllXformQUse4                         = 0x00000000,
+    .EmcDllXformQUse5                         = 0x00000000,
+    .EmcDllXformQUse6                         = 0x00000000,
+    .EmcDllXformQUse7                         = 0x00000000,
+    .EmcDllXformAddr0                         = 0x0000400e,
+    .EmcDllXformAddr1                         = 0x0000400e,
+    .EmcDllXformAddr2                         = 0x00000000,
+    .EmcDllXformAddr3                         = 0x0000400e,
+    .EmcDllXformAddr4                         = 0x0000400e,
+    .EmcDllXformAddr5                         = 0x00000000,
+    .EmcDllXformQUse8                         = 0x00000000,
+    .EmcDllXformQUse9                         = 0x00000000,
+    .EmcDllXformQUse10                        = 0x00000000,
+    .EmcDllXformQUse11                        = 0x00000000,
+    .EmcDllXformQUse12                        = 0x00000000,
+    .EmcDllXformQUse13                        = 0x00000000,
+    .EmcDllXformQUse14                        = 0x00000000,
+    .EmcDllXformQUse15                        = 0x00000000,
+    .EmcDliTrimTxDqs0                         = 0x00000000,
+    .EmcDliTrimTxDqs1                         = 0x00000000,
+    .EmcDliTrimTxDqs2                         = 0x00000000,
+    .EmcDliTrimTxDqs3                         = 0x00000000,
+    .EmcDliTrimTxDqs4                         = 0x00000000,
+    .EmcDliTrimTxDqs5                         = 0x00000000,
+    .EmcDliTrimTxDqs6                         = 0x00000000,
+    .EmcDliTrimTxDqs7                         = 0x00000000,
+    .EmcDliTrimTxDqs8                         = 0x00000000,
+    .EmcDliTrimTxDqs9                         = 0x00000000,
+    .EmcDliTrimTxDqs10                        = 0x00000000,
+    .EmcDliTrimTxDqs11                        = 0x00000000,
+    .EmcDliTrimTxDqs12                        = 0x00000000,
+    .EmcDliTrimTxDqs13                        = 0x00000000,
+    .EmcDliTrimTxDqs14                        = 0x00000000,
+    .EmcDliTrimTxDqs15                        = 0x00000000,
+    .EmcDllXformDq0                           = 0x0000000d,
+    .EmcDllXformDq1                           = 0x0000000d,
+    .EmcDllXformDq2                           = 0x0000000d,
+    .EmcDllXformDq3                           = 0x0000000d,
+    .EmcDllXformDq4                           = 0x0000000d,
+    .EmcDllXformDq5                           = 0x0000000d,
+    .EmcDllXformDq6                           = 0x0000000d,
+    .EmcDllXformDq7                           = 0x0000000d,
+    .WarmBootWait                             = 0x00000002,
+    .EmcCttTermCtrl                           = 0x00000802,
+    .EmcOdtWrite                              = 0x00000000,
+    .EmcOdtRead                               = 0x00000000,
+    .EmcZcalInterval                          = 0x00020000,
+    .EmcZcalWaitCnt                           = 0x00000042,
+    .EmcZcalMrwCmd                            = 0x80000000,
+    .EmcMrsResetDll                           = 0x00000000,
+    .EmcZcalInitDev0                          = 0x80000011,
+    .EmcZcalInitDev1                          = 0x00000000,
+    .EmcZcalInitWait                          = 0x00000001,
+    .EmcZcalWarmColdBootEnables               = 0x00000003,
+    .EmcMrwLpddr2ZcalWarmBoot                 = 0x040a00ab,
+    .EmcZqCalDdr3WarmBoot                     = 0x00000000,
+    .EmcZcalWarmBootWait                      = 0x00000001,
+    .EmcMrsWarmBootEnable                     = 0x00000001,
+    .EmcMrsResetDllWait                       = 0x00000000,
+    .EmcMrsExtra                              = 0x80001d71,
+    .EmcWarmBootMrsExtra                      = 0x80100002,
+    .EmcEmrsDdr2DllEnable                     = 0x00000000,
+    .EmcMrsDdr2DllReset                       = 0x00000000,
+    .EmcEmrsDdr2OcdCalib                      = 0x00000000,
+    .EmcDdr2Wait                              = 0x00000000,
+    .EmcClkenOverride                         = 0x00000000,
+    .McDisExtraSnapLevels                     = 0x00000000,
+    .EmcExtraRefreshNum                       = 0x00000002,
+    .EmcClkenOverrideAllWarmBoot              = 0x00000000,
+    .McClkenOverrideAllWarmBoot               = 0x00000000,
+    .EmcCfgDigDllPeriodWarmBoot               = 0x00000003,
+    .PmcVddpSel                               = 0x00000002,
+    .PmcVddpSelWait                           = 0x00000002,
+    .PmcDdrPwr                                = 0x00000003,
+    .PmcDdrCfg                                = 0x00002002,
+    .PmcIoDpd3Req                             = 0x4ffeaf67,
+    .PmcIoDpd3ReqWait                         = 0x00000000,
+    .PmcRegShort                              = 0x00000000,
+    .PmcNoIoPower                             = 0x00000000,
+    .PmcPorDpdCtrlWait                        = 0x00000000,
+    .EmcXm2CmdPadCtrl                         = 0x100002a0,
+    .EmcXm2CmdPadCtrl2                        = 0x770c0000,
+    .EmcXm2CmdPadCtrl3                        = 0x050c0000,
+    .EmcXm2CmdPadCtrl4                        = 0x00000000,
+    .EmcXm2CmdPadCtrl5                        = 0x00111111,
+    .EmcXm2DqsPadCtrl                         = 0x770c1414,
+    .EmcXm2DqsPadCtrl2                        = 0x0020013d,
+    .EmcXm2DqsPadCtrl3                        = 0x61861820,
+    .EmcXm2DqsPadCtrl4                        = 0x00514514,
+    .EmcXm2DqsPadCtrl5                        = 0x00514514,
+    .EmcXm2DqsPadCtrl6                        = 0x61861800,
+    .EmcXm2DqPadCtrl                          = 0x770c2990,
+    .EmcXm2DqPadCtrl2                         = 0x00000000,
+    .EmcXm2DqPadCtrl3                         = 0x00000000,
+    .EmcXm2ClkPadCtrl                         = 0x77ffc085,
+    .EmcXm2ClkPadCtrl2                        = 0x00000505,
+    .EmcXm2CompPadCtrl                        = 0x81f1f108,
+    .EmcXm2VttGenPadCtrl                      = 0x07070004,
+    .EmcXm2VttGenPadCtrl2                     = 0x00000000,
+    .EmcXm2VttGenPadCtrl3                     = 0x017fffff,
+    .EmcAcpdControl                           = 0x00000000,
+    .EmcSwizzleRank0ByteCfg                   = 0x00003210,
+    .EmcSwizzleRank0Byte0                     = 0x76543210,
+    .EmcSwizzleRank0Byte1                     = 0x76543210,
+    .EmcSwizzleRank0Byte2                     = 0x76543210,
+    .EmcSwizzleRank0Byte3                     = 0x76543210,
+    .EmcSwizzleRank1ByteCfg                   = 0x00003210,
+    .EmcSwizzleRank1Byte0                     = 0x76543210,
+    .EmcSwizzleRank1Byte1                     = 0x76543210,
+    .EmcSwizzleRank1Byte2                     = 0x76543210,
+    .EmcSwizzleRank1Byte3                     = 0x76543210,
+    .EmcDsrVttgenDrv                          = 0x0505003f,
+    .EmcTxdsrvttgen                           = 0x00000000,
+    .EmcBgbiasCtl0                            = 0x00000000,
+    .McEmemAdrCfg                             = 0x00000000,
+    .McEmemAdrCfgDev0                         = 0x00080303,
+    .McEmemAdrCfgDev1                         = 0x00080303,
+    .McEmemAdrCfgBankMask0                    = 0x00001248,
+    .McEmemAdrCfgBankMask1                    = 0x00002490,
+    .McEmemAdrCfgBankMask2                    = 0x00000920,
+    .McEmemAdrCfgBankSwizzle3                 = 0x00000001,
+    .McEmemCfg                                = 0x00000800,
+    .McEmemArbCfg                             = 0x0e00000b,
+    .McEmemArbOutstandingReq                  = 0x80000040,
+    .McEmemArbTimingRcd                       = 0x00000004,
+    .McEmemArbTimingRp                        = 0x00000005,
+    .McEmemArbTimingRc                        = 0x00000013,
+    .McEmemArbTimingRas                       = 0x0000000c,
+    .McEmemArbTimingFaw                       = 0x0000000f,
+    .McEmemArbTimingRrd                       = 0x00000002,
+    .McEmemArbTimingRap2Pre                   = 0x00000003,
+    .McEmemArbTimingWap2Pre                   = 0x0000000c,
+    .McEmemArbTimingR2R                       = 0x00000002,
+    .McEmemArbTimingW2W                       = 0x00000002,
+    .McEmemArbTimingR2W                       = 0x00000005,
+    .McEmemArbTimingW2R                       = 0x00000008,
+    .McEmemArbDaTurns                         = 0x08050202,
+    .McEmemArbDaCovers                        = 0x00170e13,
+    .McEmemArbMisc0                           = 0x736c2414,
+    .McEmemArbMisc1                           = 0x70000f02,
+    .McEmemArbRing1Throttle                   = 0x001f0000,
+    .McEmemArbOverride                        = 0x10000000,
+    .McEmemArbOverride1                       = 0x00000000,
+    .McEmemArbRsv                             = 0xff00ff00,
+    .McClkenOverride                          = 0x00000000,
+    .McStatControl                            = 0x00000000,
+    .McDisplaySnapRing                        = 0x00000003,
+    .McVideoProtectBom                        = 0xfff00000,
+    .McVideoProtectBomAdrHi                   = 0x00000000,
+    .McVideoProtectSizeMb                     = 0x00000000,
+    .McVideoProtectVprOverride                = 0xe4bac743,
+    .McVideoProtectVprOverride1               = 0x00000013,
+    .McVideoProtectGpuOverride0               = 0x00000000,
+    .McVideoProtectGpuOverride1               = 0x00000000,
+    .McSecCarveoutBom                         = 0xfff00000,
+    .McSecCarveoutAdrHi                       = 0x00000000,
+    .McSecCarveoutSizeMb                      = 0x00000000,
+    .McVideoProtectWriteAccess                = 0x00000000,
+    .McSecCarveoutProtectWriteAccess          = 0x00000000,
+    .EmcCaTrainingEnable                      = 0x00000000,
+    .EmcCaTrainingTimingCntl1                 = 0x1f7df7df,
+    .EmcCaTrainingTimingCntl2                 = 0x0000001f,
+    .SwizzleRankByteEncode                    = 0x00000000,
+    .BootRomPatchControl                      = 0x00000000,
+    .BootRomPatchData                         = 0x00000000,
+    .McMtsCarveoutBom                         = 0xfff00000,
+    .McMtsCarveoutAdrHi                       = 0x00000000,
+    .McMtsCarveoutSizeMb                      = 0x00000000,
+    .McMtsCarveoutRegCtrl                     = 0x00000000,
+
+};
+
+
--- a/loader/sdram_lp0.c
+++ b/loader/sdram_lp0.c
@ -0,0 +1,631 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+#include "sdram.h"
+#include "sdram_lp0.h"
+#include "pmc_lp0.h"
+#include "clock_lp0.h"
+#include "types.h"
+#include "t124.h"
+#include "printf.h"
+/*
+ * This function reads SDRAM parameters (and a few CLK_RST register values) from
+ * the common BCT format and writes them into PMC scratch registers (where the
+ * BootROM expects them on LP0 resume). Since those store the same values in a
+ * different format, we follow a "translation table" taken from Nvidia's U-Boot
+ * implementation to shift bits into the right position.
+ *
+ * Contrary to U-Boot, we transform the same macros directly into hardcoded
+ * assignments (without any pesky function calls or volatile qualifiers) to give
+ * the compiler as much room for optimization as possible. For that reason, we
+ * that PMC scratch register accesses should not have side effects and can be
+ * arbitrarily reordered. For the few accesses that do have side-effects, the
+ * code must contain explicit memory barriers.
+ */
+
+/*
+ * Sync primitives
+ */
+
+
+void sdram_lp0_save_params(const sdram_params_t124 *sdram)
+{
+	struct tegra_pmc_regs * pmc = (void *)PMC_BASE;
+	struct clk_rst_ctlr * clk_rst = (void *)CLOCK_BASE;
+
+#define pack(src, src_bits, dst, dst_bits) { \
+	_Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \
+		(0 ? dst_bits), "byte range flipped (must be MSB:LSB)"); \
+	_Static_assert((1 ? src_bits) - (0 ? src_bits) == (1 ? dst_bits) - \
+		(0 ? dst_bits), "src and dst byte range lengths differ"); \
+	u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \
+	dst &= ~(mask << (0 ? dst_bits)); \
+	dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \
+}
+
+#define s(param, src_bits, pmcreg, dst_bits) \
+	pack(sdram->param, src_bits, pmc->pmcreg, dst_bits)
+
+#define m(clkreg, src_bits, pmcreg, dst_bits) \
+	pack(clk_rst->clkreg, src_bits, pmc->pmcreg, dst_bits)
+
+#define c(value, pmcreg, dst_bits) \
+	pack(value, (1 ? dst_bits) - (0 ? dst_bits) : 0, pmc->pmcreg, dst_bits)
+
+	s(EmcClockSource, 7:0, scratch6, 15:8);
+	s(EmcClockSource, 31:29, scratch6, 18:16);
+	s(EmcClockSource, 26:26, scratch6, 19:19);
+	s(EmcOdtWrite, 5:0, scratch6, 25:20);
+	s(EmcOdtWrite, 11:8, scratch6, 29:26);
+	s(EmcOdtWrite, 30:30, scratch6, 30:30);
+	s(EmcOdtWrite, 31:31, scratch6, 31:31);
+	s(EmcXm2DqPadCtrl2, 18:16, scratch7, 22:20);
+	s(EmcXm2DqPadCtrl2, 22:20, scratch7, 25:23);
+	s(EmcXm2DqPadCtrl2, 26:24, scratch7, 28:26);
+	s(EmcXm2DqPadCtrl2, 30:28, scratch7, 31:29);
+	s(EmcXm2DqPadCtrl3, 18:16, scratch8, 22:20);
+	s(EmcXm2DqPadCtrl3, 22:20, scratch8, 25:23);
+	s(EmcXm2DqPadCtrl3, 26:24, scratch8, 28:26);
+	s(EmcXm2DqPadCtrl3, 30:28, scratch8, 31:29);
+	s(EmcTxsrDll, 11:0, scratch9, 31:20);
+	c(0, scratch10, 31:0);
+	s(EmcDsrVttgenDrv, 5:0, scratch10, 25:20);
+	s(EmcDsrVttgenDrv, 18:16, scratch10, 28:26);
+	s(EmcDsrVttgenDrv, 26:24, scratch10, 31:29);
+	s(EmcFbioSpare, 31:24, scratch11, 7:0);
+	s(EmcFbioSpare, 23:16, scratch11, 15:8);
+	s(EmcFbioSpare, 15:8, scratch11, 23:16);
+	s(EmcFbioSpare, 7:0, scratch11, 31:24);
+	s(EmcCfgRsv, 31:0, scratch12, 31:0);
+	s(EmcCdbCntl2, 31:0, scratch13, 31:0);
+	s(McEmemArbDaTurns, 31:0, scratch14, 31:0);
+	s(EmcCfgDigDll, 0:0, scratch17, 0:0);
+	s(EmcCfgDigDll, 25:2, scratch17, 24:1);
+	s(EmcCfgDigDll, 31:27, scratch17, 29:25);
+	s(EmcCdbCntl1, 29:0, scratch18, 29:0);
+	s(McEmemArbMisc0, 14:0, scratch19, 14:0);
+	s(McEmemArbMisc0, 30:16, scratch19, 29:15);
+	s(EmcXm2DqsPadCtrl, 4:0, scratch22, 4:0);
+	s(EmcXm2DqsPadCtrl, 12:8, scratch22, 9:5);
+	s(EmcXm2DqsPadCtrl, 31:14, scratch22, 27:10);
+	s(EmcRrd, 3:0, scratch22, 31:28);
+	s(EmcXm2DqPadCtrl, 31:4, scratch23, 27:0);
+	s(EmcRext, 3:0, scratch23, 31:28);
+	s(EmcXm2CompPadCtrl, 16:0, scratch24, 16:0);
+	s(EmcXm2CompPadCtrl, 24:20, scratch24, 21:17);
+	s(EmcXm2CompPadCtrl, 27:27, scratch24, 22:22);
+	s(EmcXm2CompPadCtrl, 31:28, scratch24, 26:23);
+	s(EmcR2w, 4:0, scratch24, 31:27);
+	s(EmcCfg, 9:1, scratch25, 8:0);
+	s(EmcCfg, 26:16, scratch25, 19:9);
+	s(EmcCfg, 31:28, scratch25, 23:20);
+	s(EmcXm2VttGenPadCtrl, 0:0, scratch25, 24:24);
+	s(EmcXm2VttGenPadCtrl, 2:2, scratch25, 25:25);
+	s(EmcXm2VttGenPadCtrl, 18:16, scratch25, 28:26);
+	s(EmcXm2VttGenPadCtrl, 26:24, scratch25, 31:29);
+	s(EmcZcalInterval, 23:10, scratch26, 13:0);
+	s(EmcZcalInterval, 9:0, scratch26, 23:14);
+	s(EmcSelDpdCtrl, 5:2, scratch26, 27:24);
+	s(EmcSelDpdCtrl, 8:8, scratch26, 28:28);
+	s(EmcSelDpdCtrl, 18:16, scratch26, 31:29);
+	s(EmcXm2VttGenPadCtrl3, 22:0, scratch27, 22:0);
+	s(EmcXm2VttGenPadCtrl3, 24:24, scratch27, 23:23);
+	s(EmcSwizzleRank0ByteCfg, 1:0, scratch27, 25:24);
+	s(EmcSwizzleRank0ByteCfg, 5:4, scratch27, 27:26);
+	s(EmcSwizzleRank0ByteCfg, 9:8, scratch27, 29:28);
+	s(EmcSwizzleRank0ByteCfg, 13:12, scratch27, 31:30);
+	s(EmcXm2ClkPadCtrl2, 5:0, scratch28, 5:0);
+	s(EmcXm2ClkPadCtrl2, 13:8, scratch28, 11:6);
+	s(EmcXm2ClkPadCtrl2, 20:16, scratch28, 16:12);
+	s(EmcXm2ClkPadCtrl2, 23:23, scratch28, 17:17);
+	s(EmcXm2ClkPadCtrl2, 28:24, scratch28, 22:18);
+	s(EmcXm2ClkPadCtrl2, 31:31, scratch28, 23:23);
+	s(EmcSwizzleRank1ByteCfg, 1:0, scratch28, 25:24);
+	s(EmcSwizzleRank1ByteCfg, 5:4, scratch28, 27:26);
+	s(EmcSwizzleRank1ByteCfg, 9:8, scratch28, 29:28);
+	s(EmcSwizzleRank1ByteCfg, 13:12, scratch28, 31:30);
+	s(McEmemArbDaCovers, 23:0, scratch29, 23:0);
+	s(McEmemArbRsv, 7:0, scratch29, 31:24);
+	s(EmcAutoCalConfig, 4:0, scratch30, 4:0);
+	s(EmcAutoCalConfig, 12:8, scratch30, 9:5);
+	s(EmcAutoCalConfig, 18:16, scratch30, 12:10);
+	s(EmcAutoCalConfig, 25:20, scratch30, 18:13);
+	s(EmcAutoCalConfig, 31:28, scratch30, 22:19);
+	s(EmcRfc, 8:0, scratch30, 31:23);
+	s(EmcXm2DqsPadCtrl2, 21:0, scratch31, 21:0);
+	s(EmcXm2DqsPadCtrl2, 24:24, scratch31, 22:22);
+	s(EmcAr2Pden, 8:0, scratch31, 31:23);
+	s(EmcXm2ClkPadCtrl, 0:0, scratch32, 0:0);
+	s(EmcXm2ClkPadCtrl, 4:2, scratch32, 3:1);
+	s(EmcXm2ClkPadCtrl, 7:7, scratch32, 4:4);
+	s(EmcXm2ClkPadCtrl, 31:14, scratch32, 22:5);
+	s(EmcRfcSlr, 8:0, scratch32, 31:23);
+	s(EmcXm2DqsPadCtrl3, 0:0, scratch33, 0:0);
+	s(EmcXm2DqsPadCtrl3, 5:5, scratch33, 1:1);
+	s(EmcXm2DqsPadCtrl3, 12:8, scratch33, 6:2);
+	s(EmcXm2DqsPadCtrl3, 18:14, scratch33, 11:7);
+	s(EmcXm2DqsPadCtrl3, 24:20, scratch33, 16:12);
+	s(EmcXm2DqsPadCtrl3, 30:26, scratch33, 21:17);
+	s(EmcTxsr, 9:0, scratch33, 31:22);
+	s(McEmemArbCfg, 8:0, scratch40, 8:0);
+	s(McEmemArbCfg, 20:16, scratch40, 13:9);
+	s(McEmemArbCfg, 27:24, scratch40, 17:14);
+	s(McEmemArbCfg, 31:28, scratch40, 21:18);
+	s(EmcMc2EmcQ, 2:0, scratch40, 24:22);
+	s(EmcMc2EmcQ, 10:8, scratch40, 27:25);
+	s(EmcMc2EmcQ, 27:24, scratch40, 31:28);
+	s(EmcAutoCalInterval, 20:0, scratch42, 20:0);
+	s(McEmemArbOutstandingReq, 8:0, scratch42, 29:21);
+	s(McEmemArbOutstandingReq, 31:30, scratch42, 31:30);
+	s(EmcMrsWaitCnt2, 9:0, scratch44, 9:0);
+	s(EmcMrsWaitCnt2, 25:16, scratch44, 19:10);
+	s(EmcTxdsrvttgen, 11:0, scratch44, 31:20);
+	s(EmcMrsWaitCnt, 9:0, scratch45, 9:0);
+	s(EmcMrsWaitCnt, 25:16, scratch45, 19:10);
+	s(EmcCfgPipe, 1:0, scratch45, 21:20);
+	s(EmcCfgPipe, 9:4, scratch45, 27:22);
+	s(EmcCfgPipe, 15:12, scratch45, 31:28);
+	s(EmcXm2DqsPadCtrl4, 22:18, scratch46, 4:0);
+	s(EmcXm2DqsPadCtrl4, 16:12, scratch46, 9:5);
+	s(EmcXm2DqsPadCtrl4, 10:6, scratch46, 14:10);
+	s(EmcXm2DqsPadCtrl4, 4:0, scratch46, 19:15);
+	s(EmcZcalWaitCnt, 9:0, scratch46, 29:20);
+	s(EmcXm2DqsPadCtrl5, 22:18, scratch47, 4:0);
+	s(EmcXm2DqsPadCtrl5, 16:12, scratch47, 9:5);
+	s(EmcXm2DqsPadCtrl5, 10:6, scratch47, 14:10);
+	s(EmcXm2DqsPadCtrl5, 4:0, scratch47, 19:15);
+	s(EmcXm2VttGenPadCtrl2, 5:0, scratch47, 25:20);
+	s(EmcXm2VttGenPadCtrl2, 31:28, scratch47, 29:26);
+	s(EmcXm2DqsPadCtrl6, 12:8, scratch48, 4:0);
+	s(EmcXm2DqsPadCtrl6, 18:14, scratch48, 9:5);
+	s(EmcXm2DqsPadCtrl6, 24:20, scratch48, 14:10);
+	s(EmcXm2DqsPadCtrl6, 30:26, scratch48, 19:15);
+	s(EmcAutoCalConfig3, 4:0, scratch48, 24:20);
+	s(EmcAutoCalConfig3, 12:8, scratch48, 29:25);
+	s(EmcFbioCfg5, 1:0, scratch48, 31:30);
+	s(EmcDllXformQUse8, 4:0, scratch50, 4:0);
+	s(EmcDllXformQUse8, 22:8, scratch50, 19:5);
+	s(McEmemArbRing1Throttle, 4:0, scratch50, 24:20);
+	s(McEmemArbRing1Throttle, 20:16, scratch50, 29:25);
+	s(EmcFbioCfg5, 3:2, scratch50, 31:30);
+	s(EmcDllXformQUse9, 4:0, scratch51, 4:0);
+	s(EmcDllXformQUse9, 22:8, scratch51, 19:5);
+	s(EmcCttTermCtrl, 2:0, scratch51, 22:20);
+	s(EmcCttTermCtrl, 12:8, scratch51, 27:23);
+	s(EmcCttTermCtrl, 31:31, scratch51, 28:28);
+	s(EmcFbioCfg6, 2:0, scratch51, 31:29);
+	s(EmcDllXformQUse10, 4:0, scratch56, 4:0);
+	s(EmcDllXformQUse10, 22:8, scratch56, 19:5);
+	s(EmcXm2CmdPadCtrl, 10:3, scratch56, 27:20);
+	s(EmcXm2CmdPadCtrl, 28:28, scratch56, 28:28);
+	s(EmcPutermAdj, 1:0, scratch56, 30:29);
+	s(EmcPutermAdj, 7:7, scratch56, 31:31);
+	s(EmcDllXformQUse11, 4:0, scratch57, 4:0);
+	s(EmcDllXformQUse11, 22:8, scratch57, 19:5);
+	s(EmcWdv, 3:0, scratch57, 31:28);
+	s(EmcDllXformQUse12, 4:0, scratch58, 4:0);
+	s(EmcDllXformQUse12, 22:8, scratch58, 19:5);
+	s(EmcBurstRefreshNum, 3:0, scratch58, 31:28);
+	s(EmcDllXformQUse13, 4:0, scratch59, 4:0);
+	s(EmcDllXformQUse13, 22:8, scratch59, 19:5);
+	s(EmcWext, 3:0, scratch59, 31:28);
+	s(EmcDllXformQUse14, 4:0, scratch60, 4:0);
+	s(EmcDllXformQUse14, 22:8, scratch60, 19:5);
+	s(EmcClkenOverride, 3:1, scratch60, 30:28);
+	s(EmcClkenOverride, 6:6, scratch60, 31:31);
+	s(EmcDllXformQUse15, 4:0, scratch61, 4:0);
+	s(EmcDllXformQUse15, 22:8, scratch61, 19:5);
+	s(EmcR2r, 3:0, scratch61, 31:28);
+	s(EmcDllXformDq4, 4:0, scratch62, 4:0);
+	s(EmcDllXformDq4, 22:8, scratch62, 19:5);
+	s(EmcRc, 6:0, scratch62, 26:20);
+	s(EmcW2r, 4:0, scratch62, 31:27);
+	s(EmcDllXformDq5, 4:0, scratch63, 4:0);
+	s(EmcDllXformDq5, 22:8, scratch63, 19:5);
+	s(EmcTfaw, 6:0, scratch63, 26:20);
+	s(EmcR2p, 4:0, scratch63, 31:27);
+	s(EmcDllXformDq6, 4:0, scratch64, 4:0);
+	s(EmcDllXformDq6, 22:8, scratch64, 19:5);
+	s(EmcDliTrimTxDqs0, 6:0, scratch64, 26:20);
+	s(EmcQSafe, 4:0, scratch64, 31:27);
+	s(EmcDllXformDq7, 4:0, scratch65, 4:0);
+	s(EmcDllXformDq7, 22:8, scratch65, 19:5);
+	s(EmcDliTrimTxDqs1, 6:0, scratch65, 26:20);
+	s(EmcTClkStable, 4:0, scratch65, 31:27);
+	s(EmcAutoCalConfig2, 4:0, scratch66, 4:0);
+	s(EmcAutoCalConfig2, 12:8, scratch66, 9:5);
+	s(EmcAutoCalConfig2, 20:16, scratch66, 14:10);
+	s(EmcAutoCalConfig2, 28:24, scratch66, 19:15);
+	s(EmcDliTrimTxDqs2, 6:0, scratch66, 26:20);
+	s(EmcTClkStop, 4:0, scratch66, 31:27);
+	s(McEmemArbMisc1, 1:0, scratch67, 1:0);
+	s(McEmemArbMisc1, 12:4, scratch67, 10:2);
+	s(McEmemArbMisc1, 25:21, scratch67, 15:11);
+	s(McEmemArbMisc1, 31:28, scratch67, 19:16);
+	s(EmcDliTrimTxDqs3, 6:0, scratch67, 26:20);
+	s(EmcEInputDuration, 4:0, scratch67, 31:27);
+	s(EmcZcalMrwCmd, 7:0, scratch68, 7:0);
+	s(EmcZcalMrwCmd, 23:16, scratch68, 15:8);
+	s(EmcZcalMrwCmd, 31:30, scratch68, 17:16);
+	s(EmcTRefBw, 13:0, scratch68, 31:18);
+	s(EmcXm2CmdPadCtrl2, 31:14, scratch69, 17:0);
+	s(EmcDliTrimTxDqs4, 6:0, scratch69, 24:18);
+	s(EmcDliTrimTxDqs5, 6:0, scratch69, 31:25);
+	s(EmcXm2CmdPadCtrl3, 31:14, scratch70, 17:0);
+	s(EmcDliTrimTxDqs6, 6:0, scratch70, 24:18);
+	s(EmcDliTrimTxDqs7, 6:0, scratch70, 31:25);
+	s(EmcXm2CmdPadCtrl5, 2:0, scratch71, 2:0);
+	s(EmcXm2CmdPadCtrl5, 6:4, scratch71, 5:3);
+	s(EmcXm2CmdPadCtrl5, 10:8, scratch71, 8:6);
+	s(EmcXm2CmdPadCtrl5, 14:12, scratch71, 11:9);
+	s(EmcXm2CmdPadCtrl5, 18:16, scratch71, 14:12);
+	s(EmcXm2CmdPadCtrl5, 22:20, scratch71, 17:15);
+	s(EmcDliTrimTxDqs8, 6:0, scratch71, 24:18);
+	s(EmcDliTrimTxDqs9, 6:0, scratch71, 31:25);
+	s(EmcCdbCntl3, 17:0, scratch72, 17:0);
+	s(EmcDliTrimTxDqs10, 6:0, scratch72, 24:18);
+	s(EmcDliTrimTxDqs11, 6:0, scratch72, 31:25);
+	s(EmcSwizzleRank0Byte0, 2:0, scratch73, 2:0);
+	s(EmcSwizzleRank0Byte0, 6:4, scratch73, 5:3);
+	s(EmcSwizzleRank0Byte0, 10:8, scratch73, 8:6);
+	s(EmcSwizzleRank0Byte0, 14:12, scratch73, 11:9);
+	s(EmcSwizzleRank0Byte0, 18:16, scratch73, 14:12);
+	s(EmcSwizzleRank0Byte0, 22:20, scratch73, 17:15);
+	s(EmcDliTrimTxDqs12, 6:0, scratch73, 24:18);
+	s(EmcDliTrimTxDqs13, 6:0, scratch73, 31:25);
+	s(EmcSwizzleRank0Byte1, 2:0, scratch74, 2:0);
+	s(EmcSwizzleRank0Byte1, 6:4, scratch74, 5:3);
+	s(EmcSwizzleRank0Byte1, 10:8, scratch74, 8:6);
+	s(EmcSwizzleRank0Byte1, 14:12, scratch74, 11:9);
+	s(EmcSwizzleRank0Byte1, 18:16, scratch74, 14:12);
+	s(EmcSwizzleRank0Byte1, 22:20, scratch74, 17:15);
+	s(EmcDliTrimTxDqs14, 6:0, scratch74, 24:18);
+	s(EmcDliTrimTxDqs15, 6:0, scratch74, 31:25);
+	s(EmcSwizzleRank0Byte2, 2:0, scratch75, 2:0);
+	s(EmcSwizzleRank0Byte2, 6:4, scratch75, 5:3);
+	s(EmcSwizzleRank0Byte2, 10:8, scratch75, 8:6);
+	s(EmcSwizzleRank0Byte2, 14:12, scratch75, 11:9);
+	s(EmcSwizzleRank0Byte2, 18:16, scratch75, 14:12);
+	s(EmcSwizzleRank0Byte2, 22:20, scratch75, 17:15);
+	s(McEmemArbTimingRp, 6:0, scratch75, 24:18);
+	s(McEmemArbTimingRc, 6:0, scratch75, 31:25);
+	s(EmcSwizzleRank0Byte3, 2:0, scratch76, 2:0);
+	s(EmcSwizzleRank0Byte3, 6:4, scratch76, 5:3);
+	s(EmcSwizzleRank0Byte3, 10:8, scratch76, 8:6);
+	s(EmcSwizzleRank0Byte3, 14:12, scratch76, 11:9);
+	s(EmcSwizzleRank0Byte3, 18:16, scratch76, 14:12);
+	s(EmcSwizzleRank0Byte3, 22:20, scratch76, 17:15);
+	s(McEmemArbTimingFaw, 6:0, scratch76, 24:18);
+	s(McEmemArbTimingWap2Pre, 6:0, scratch76, 31:25);
+	s(EmcSwizzleRank1Byte0, 2:0, scratch77, 2:0);
+	s(EmcSwizzleRank1Byte0, 6:4, scratch77, 5:3);
+	s(EmcSwizzleRank1Byte0, 10:8, scratch77, 8:6);
+	s(EmcSwizzleRank1Byte0, 14:12, scratch77, 11:9);
+	s(EmcSwizzleRank1Byte0, 18:16, scratch77, 14:12);
+	s(EmcSwizzleRank1Byte0, 22:20, scratch77, 17:15);
+	s(EmcRas, 5:0, scratch77, 23:18);
+	s(EmcRp, 5:0, scratch77, 29:24);
+	s(EmcCfg2, 9:8, scratch77, 31:30);
+	s(EmcSwizzleRank1Byte1, 2:0, scratch78, 2:0);
+	s(EmcSwizzleRank1Byte1, 6:4, scratch78, 5:3);
+	s(EmcSwizzleRank1Byte1, 10:8, scratch78, 8:6);
+	s(EmcSwizzleRank1Byte1, 14:12, scratch78, 11:9);
+	s(EmcSwizzleRank1Byte1, 18:16, scratch78, 14:12);
+	s(EmcSwizzleRank1Byte1, 22:20, scratch78, 17:15);
+	s(EmcW2p, 5:0, scratch78, 23:18);
+	s(EmcRdRcd, 5:0, scratch78, 29:24);
+	s(EmcCfg2, 27:26, scratch78, 31:30);
+	s(EmcSwizzleRank1Byte2, 2:0, scratch79, 2:0);
+	s(EmcSwizzleRank1Byte2, 6:4, scratch79, 5:3);
+	s(EmcSwizzleRank1Byte2, 10:8, scratch79, 8:6);
+	s(EmcSwizzleRank1Byte2, 14:12, scratch79, 11:9);
+	s(EmcSwizzleRank1Byte2, 18:16, scratch79, 14:12);
+	s(EmcSwizzleRank1Byte2, 22:20, scratch79, 17:15);
+	s(EmcWrRcd, 5:0, scratch79, 23:18);
+	s(EmcQUse, 5:0, scratch79, 29:24);
+	s(EmcFbioCfg5, 4:4, scratch79, 31:31);
+	s(EmcSwizzleRank1Byte3, 2:0, scratch80, 2:0);
+	s(EmcSwizzleRank1Byte3, 6:4, scratch80, 5:3);
+	s(EmcSwizzleRank1Byte3, 10:8, scratch80, 8:6);
+	s(EmcSwizzleRank1Byte3, 14:12, scratch80, 11:9);
+	s(EmcSwizzleRank1Byte3, 18:16, scratch80, 14:12);
+	s(EmcSwizzleRank1Byte3, 22:20, scratch80, 17:15);
+	s(EmcQRst, 5:0, scratch80, 23:18);
+	s(EmcRdv, 5:0, scratch80, 29:24);
+	s(EmcFbioCfg5, 6:5, scratch80, 31:30);
+	s(EmcDynSelfRefControl, 15:0, scratch81, 15:0);
+	s(EmcDynSelfRefControl, 31:31, scratch81, 16:16);
+	s(EmcPdEx2Wr, 5:0, scratch81, 22:17);
+	s(EmcPdEx2Rd, 5:0, scratch81, 28:23);
+	s(EmcRefresh, 5:0, scratch82, 5:0);
+	s(EmcRefresh, 15:6, scratch82, 15:6);
+	s(EmcCmdQ, 4:0, scratch82, 20:16);
+	s(EmcCmdQ, 10:8, scratch82, 23:21);
+	s(EmcCmdQ, 14:12, scratch82, 26:24);
+	s(EmcCmdQ, 28:24, scratch82, 31:27);
+	s(EmcAcpdControl, 15:0, scratch83, 15:0);
+	s(EmcCfgDigDllPeriod, 15:0, scratch83, 31:16);
+	s(EmcDllXformDqs0, 4:0, scratch84, 4:0);
+	s(EmcDllXformDqs0, 22:12, scratch84, 15:5);
+	s(EmcDllXformDqs1, 4:0, scratch84, 20:16);
+	s(EmcDllXformDqs1, 22:12, scratch84, 31:21);
+	s(EmcDllXformDqs2, 4:0, scratch85, 4:0);
+	s(EmcDllXformDqs2, 22:12, scratch85, 15:5);
+	s(EmcDllXformDqs3, 4:0, scratch85, 20:16);
+	s(EmcDllXformDqs3, 22:12, scratch85, 31:21);
+	s(EmcDllXformDqs4, 4:0, scratch86, 4:0);
+	s(EmcDllXformDqs4, 22:12, scratch86, 15:5);
+	s(EmcDllXformDqs5, 4:0, scratch86, 20:16);
+	s(EmcDllXformDqs5, 22:12, scratch86, 31:21);
+	s(EmcDllXformDqs6, 4:0, scratch87, 4:0);
+	s(EmcDllXformDqs6, 22:12, scratch87, 15:5);
+	s(EmcDllXformDqs7, 4:0, scratch87, 20:16);
+	s(EmcDllXformDqs7, 22:12, scratch87, 31:21);
+	s(EmcDllXformDqs8, 4:0, scratch88, 4:0);
+	s(EmcDllXformDqs8, 22:12, scratch88, 15:5);
+	s(EmcDllXformDqs9, 4:0, scratch88, 20:16);
+	s(EmcDllXformDqs9, 22:12, scratch88, 31:21);
+	s(EmcDllXformDqs10, 4:0, scratch89, 4:0);
+	s(EmcDllXformDqs10, 22:12, scratch89, 15:5);
+	s(EmcDllXformDqs11, 4:0, scratch89, 20:16);
+	s(EmcDllXformDqs11, 22:12, scratch89, 31:21);
+	s(EmcDllXformDqs12, 4:0, scratch90, 4:0);
+	s(EmcDllXformDqs12, 22:12, scratch90, 15:5);
+	s(EmcDllXformDqs13, 4:0, scratch90, 20:16);
+	s(EmcDllXformDqs13, 22:12, scratch90, 31:21);
+	s(EmcDllXformDqs14, 4:0, scratch91, 4:0);
+	s(EmcDllXformDqs14, 22:12, scratch91, 15:5);
+	s(EmcDllXformDqs15, 4:0, scratch91, 20:16);
+	s(EmcDllXformDqs15, 22:12, scratch91, 31:21);
+	s(EmcDllXformQUse0, 4:0, scratch92, 4:0);
+	s(EmcDllXformQUse0, 22:12, scratch92, 15:5);
+	s(EmcDllXformQUse1, 4:0, scratch92, 20:16);
+	s(EmcDllXformQUse1, 22:12, scratch92, 31:21);
+	s(EmcDllXformQUse2, 4:0, scratch93, 4:0);
+	s(EmcDllXformQUse2, 22:12, scratch93, 15:5);
+	s(EmcDllXformQUse3, 4:0, scratch93, 20:16);
+	s(EmcDllXformQUse3, 22:12, scratch93, 31:21);
+	s(EmcDllXformQUse4, 4:0, scratch94, 4:0);
+	s(EmcDllXformQUse4, 22:12, scratch94, 15:5);
+	s(EmcDllXformQUse5, 4:0, scratch94, 20:16);
+	s(EmcDllXformQUse5, 22:12, scratch94, 31:21);
+	s(EmcDllXformQUse6, 4:0, scratch95, 4:0);
+	s(EmcDllXformQUse6, 22:12, scratch95, 15:5);
+	s(EmcDllXformQUse7, 4:0, scratch95, 20:16);
+	s(EmcDllXformQUse7, 22:12, scratch95, 31:21);
+	s(EmcDllXformDq0, 4:0, scratch96, 4:0);
+	s(EmcDllXformDq0, 22:12, scratch96, 15:5);
+	s(EmcDllXformDq1, 4:0, scratch96, 20:16);
+	s(EmcDllXformDq1, 22:12, scratch96, 31:21);
+	s(EmcDllXformDq2, 4:0, scratch97, 4:0);
+	s(EmcDllXformDq2, 22:12, scratch97, 15:5);
+	s(EmcDllXformDq3, 4:0, scratch97, 20:16);
+	s(EmcDllXformDq3, 22:12, scratch97, 31:21);
+	s(EmcPreRefreshReqCnt, 15:0, scratch98, 15:0);
+	s(EmcDllXformAddr0, 4:0, scratch98, 20:16);
+	s(EmcDllXformAddr0, 22:12, scratch98, 31:21);
+	s(EmcDllXformAddr1, 4:0, scratch99, 4:0);
+	s(EmcDllXformAddr1, 22:12, scratch99, 15:5);
+	s(EmcDllXformAddr2, 4:0, scratch99, 20:16);
+	s(EmcDllXformAddr2, 22:12, scratch99, 31:21);
+	s(EmcDllXformAddr3, 4:0, scratch100, 4:0);
+	s(EmcDllXformAddr3, 22:12, scratch100, 15:5);
+	s(EmcDllXformAddr4, 4:0, scratch100, 20:16);
+	s(EmcDllXformAddr4, 22:12, scratch100, 31:21);
+	s(EmcDllXformAddr5, 4:0, scratch101, 4:0);
+	s(EmcDllXformAddr5, 22:12, scratch101, 15:5);
+	s(EmcPChg2Pden, 5:0, scratch102, 5:0);
+	s(EmcAct2Pden, 5:0, scratch102, 11:6);
+	s(EmcRw2Pden, 5:0, scratch102, 17:12);
+	s(EmcTcke, 5:0, scratch102, 23:18);
+	s(EmcTrpab, 5:0, scratch102, 29:24);
+	s(EmcFbioCfg5, 8:7, scratch102, 31:30);
+	s(EmcCtt, 5:0, scratch103, 5:0);
+	s(EmcEInput, 5:0, scratch103, 11:6);
+	s(EmcPutermExtra, 21:16, scratch103, 17:12);
+	s(EmcTckesr, 5:0, scratch103, 23:18);
+	s(EmcTpd, 5:0, scratch103, 29:24);
+	s(EmcFbioCfg5, 10:9, scratch103, 31:30);
+	s(EmcRdvMask, 5:0, scratch104, 5:0);
+	s(EmcXm2CmdPadCtrl4, 0:0, scratch104, 6:6);
+	s(EmcXm2CmdPadCtrl4, 2:2, scratch104, 7:7);
+	s(EmcXm2CmdPadCtrl4, 4:4, scratch104, 8:8);
+	s(EmcXm2CmdPadCtrl4, 6:6, scratch104, 9:9);
+	s(EmcXm2CmdPadCtrl4, 8:8, scratch104, 10:10);
+	s(EmcXm2CmdPadCtrl4, 10:10, scratch104, 11:11);
+	s(EmcQpop, 5:0, scratch104, 17:12);
+	s(McEmemArbTimingRcd, 5:0, scratch104, 23:18);
+	s(McEmemArbTimingRas, 5:0, scratch104, 29:24);
+	s(EmcFbioCfg5, 12:11, scratch104, 31:30);
+	s(McEmemArbTimingRap2Pre, 5:0, scratch105, 5:0);
+	s(McEmemArbTimingR2W, 5:0, scratch105, 11:6);
+	s(McEmemArbTimingW2R, 5:0, scratch105, 17:12);
+	s(EmcIbdly, 4:0, scratch105, 22:18);
+	s(McEmemArbTimingR2R, 4:0, scratch105, 27:23);
+	s(EmcW2w, 3:0, scratch105, 31:28);
+	s(McEmemArbTimingW2W, 4:0, scratch106, 4:0);
+	s(McEmemArbOverride, 27:27, scratch106, 5:5);
+	s(McEmemArbOverride, 26:26, scratch106, 6:6);
+	s(McEmemArbOverride, 16:16, scratch106, 7:7);
+	s(McEmemArbOverride, 10:10, scratch106, 8:8);
+	s(McEmemArbOverride, 4:4, scratch106, 9:9);
+	s(EmcWdvMask, 3:0, scratch106, 13:10);
+	s(EmcCttDuration, 3:0, scratch106, 17:14);
+	s(EmcQuseWidth, 3:0, scratch106, 21:18);
+	s(EmcPutermWidth, 3:0, scratch106, 25:22);
+	s(EmcBgbiasCtl0, 3:0, scratch106, 29:26);
+	s(EmcFbioCfg5, 25:24, scratch106, 31:30);
+	s(McEmemArbTimingRrd, 3:0, scratch107, 3:0);
+	s(EmcFbioCfg5, 23:20, scratch107, 10:7);
+	s(EmcFbioCfg5, 15:13, scratch107, 13:11);
+	s(EmcCfg2, 5:3, scratch107, 16:14);
+	s(EmcFbioCfg5, 26:26, scratch107, 17:17);
+	s(EmcFbioCfg5, 28:28, scratch107, 18:18);
+	s(EmcCfg2, 2:0, scratch107, 21:19);
+	s(EmcCfg2, 7:6, scratch107, 23:22);
+	s(EmcCfg2, 15:10, scratch107, 29:24);
+	s(EmcCfg2, 23:22, scratch107, 31:30);
+	s(EmcCfg2, 25:24, scratch108, 1:0);
+	s(EmcCfg2, 31:28, scratch108, 5:2);
+	s(BootRomPatchData, 31:0, scratch15, 31:0);
+	s(BootRomPatchControl, 31:0, scratch16, 31:0);
+	s(EmcDevSelect, 1:0, scratch17, 31:30);
+	s(EmcZcalWarmColdBootEnables, 1:0, scratch18, 31:30);
+	s(EmcCfgDigDllPeriodWarmBoot, 1:0, scratch19, 31:30);
+	s(EmcWarmBootExtraModeRegWriteEnable, 0:0, scratch46, 30:30);
+	s(McClkenOverrideAllWarmBoot, 0:0, scratch46, 31:31);
+	s(EmcClkenOverrideAllWarmBoot, 0:0, scratch47, 30:30);
+	s(EmcMrsWarmBootEnable, 0:0, scratch47, 31:31);
+	s(EmcTimingControlWait, 7:0, scratch57, 27:20);
+	s(EmcZcalWarmBootWait, 7:0, scratch58, 27:20);
+	s(EmcAutoCalWait, 7:0, scratch59, 27:20);
+	s(WarmBootWait, 7:0, scratch60, 27:20);
+	s(EmcPinProgramWait, 7:0, scratch61, 27:20);
+	s(AhbArbitrationXbarCtrlMemInitDone, 0:0, scratch79, 30:30);
+	s(EmcExtraRefreshNum, 2:0, scratch81, 31:29);
+	s(SwizzleRankByteEncode, 15:0, scratch101, 31:16);
+	s(MemoryType, 2:0, scratch107, 6:4);
+
+	switch (sdram->MemoryType) {
+	case MEMORY_TYPE_LPDDR2:
+		s(EmcMrwLpddr2ZcalWarmBoot, 23:16, scratch5, 7:0);
+		s(EmcMrwLpddr2ZcalWarmBoot, 7:0, scratch5, 15:8);
+		s(EmcWarmBootMrwExtra, 23:16, scratch5, 23:16);
+		s(EmcWarmBootMrwExtra, 7:0, scratch5, 31:24);
+		s(EmcMrwLpddr2ZcalWarmBoot, 31:30, scratch6, 1:0);
+		s(EmcWarmBootMrwExtra, 31:30, scratch6, 3:2);
+		s(EmcMrwLpddr2ZcalWarmBoot, 27:26, scratch6, 5:4);
+		s(EmcWarmBootMrwExtra, 27:26, scratch6, 7:6);
+		s(EmcMrw1, 7:0, scratch7, 7:0);
+		s(EmcMrw1, 23:16, scratch7, 15:8);
+		s(EmcMrw1, 27:26, scratch7, 17:16);
+		s(EmcMrw1, 31:30, scratch7, 19:18);
+		s(EmcMrw2, 7:0, scratch8, 7:0);
+		s(EmcMrw2, 23:16, scratch8, 15:8);
+		s(EmcMrw2, 27:26, scratch8, 17:16);
+		s(EmcMrw2, 31:30, scratch8, 19:18);
+		s(EmcMrw3, 7:0, scratch9, 7:0);
+		s(EmcMrw3, 23:16, scratch9, 15:8);
+		s(EmcMrw3, 27:26, scratch9, 17:16);
+		s(EmcMrw3, 31:30, scratch9, 19:18);
+		s(EmcMrw4, 7:0, scratch10, 7:0);
+		s(EmcMrw4, 23:16, scratch10, 15:8);
+		s(EmcMrw4, 27:26, scratch10, 17:16);
+		s(EmcMrw4, 31:30, scratch10, 19:18);
+		break;
+	case MEMORY_TYPE_DDR3:
+		s(EmcMrs, 13:0, scratch5, 13:0);
+		s(EmcEmrs, 13:0, scratch5, 27:14);
+		s(EmcMrs, 21:20, scratch5, 29:28);
+		s(EmcMrs, 31:30, scratch5, 31:30);
+		s(EmcEmrs2, 13:0, scratch7, 13:0);
+		s(EmcEmrs, 21:20, scratch7, 15:14);
+		s(EmcEmrs, 31:30, scratch7, 17:16);
+		s(EmcEmrs2, 21:20, scratch7, 19:18);
+		s(EmcEmrs3, 13:0, scratch8, 13:0);
+		s(EmcEmrs2, 31:30, scratch8, 15:14);
+		s(EmcEmrs3, 21:20, scratch8, 17:16);
+		s(EmcEmrs3, 31:30, scratch8, 19:18);
+		s(EmcWarmBootMrsExtra, 13:0, scratch9, 13:0);
+		s(EmcWarmBootMrsExtra, 31:30, scratch9, 15:14);
+		s(EmcWarmBootMrsExtra, 21:20, scratch9, 17:16);
+		s(EmcZqCalDdr3WarmBoot, 31:30, scratch9, 19:18);
+		s(EmcMrs, 27:26, scratch10, 1:0);
+		s(EmcEmrs, 27:26, scratch10, 3:2);
+		s(EmcEmrs2, 27:26, scratch10, 5:4);
+		s(EmcEmrs3, 27:26, scratch10, 7:6);
+		s(EmcWarmBootMrsExtra, 27:27, scratch10, 8:8);
+		s(EmcWarmBootMrsExtra, 26:26, scratch10, 9:9);
+		s(EmcZqCalDdr3WarmBoot, 0:0, scratch10, 10:10);
+		s(EmcZqCalDdr3WarmBoot, 4:4, scratch10, 11:11);
+		c(0, scratch116, 31:0);
+		c(0, scratch117, 31:0);
+		break;
+	default:
+		printf_("ERROR: %s() unrecognized MemoryType %d!\n",__func__,sdram->MemoryType);
+	}
+
+	s(McVideoProtectGpuOverride0, 31:0, secure_scratch8, 31:0);
+	s(McVideoProtectVprOverride, 3:0, secure_scratch9, 3:0);
+	s(McVideoProtectVprOverride, 11:6, secure_scratch9, 9:4);
+	s(McVideoProtectVprOverride, 23:14, secure_scratch9, 19:10);
+	s(McVideoProtectVprOverride, 26:26, secure_scratch9, 20:20);
+	s(McVideoProtectVprOverride, 31:29, secure_scratch9, 23:21);
+	s(EmcFbioCfg5, 19:16, secure_scratch9, 27:24);
+	s(McDisplaySnapRing, 1:0, secure_scratch9, 29:28);
+	s(McDisplaySnapRing, 31:31, secure_scratch9, 30:30);
+	s(EmcAdrCfg, 0:0, secure_scratch9, 31:31);
+	s(McVideoProtectGpuOverride1, 15:0, secure_scratch10, 15:0);
+	s(McEmemAdrCfgBankMask0, 15:0, secure_scratch10, 31:16);
+	s(McEmemAdrCfgBankMask1, 15:0, secure_scratch11, 15:0);
+	s(McEmemAdrCfgBankMask2, 15:0, secure_scratch11, 31:16);
+	s(McEmemCfg, 13:0, secure_scratch12, 13:0);
+	s(McEmemCfg, 31:31, secure_scratch12, 14:14);
+	s(McVideoProtectBom, 31:20, secure_scratch12, 26:15);
+	s(McVideoProtectVprOverride1, 1:0, secure_scratch12, 28:27);
+	s(McVideoProtectVprOverride1, 4:4, secure_scratch12, 29:29);
+	s(McVideoProtectBomAdrHi, 1:0, secure_scratch12, 31:30);
+	s(McVideoProtectSizeMb, 11:0, secure_scratch13, 11:0);
+	s(McSecCarveoutBom, 31:20, secure_scratch13, 23:12);
+	s(McEmemAdrCfgBankSwizzle3, 2:0, secure_scratch13, 26:24);
+	s(McVideoProtectWriteAccess, 1:0, secure_scratch13, 28:27);
+	s(McSecCarveoutAdrHi, 1:0, secure_scratch13, 30:29);
+	s(McEmemAdrCfg, 0:0, secure_scratch13, 31:31);
+	s(McSecCarveoutSizeMb, 11:0, secure_scratch14, 11:0);
+	s(McMtsCarveoutBom, 31:20, secure_scratch14, 23:12);
+	s(McMtsCarveoutAdrHi, 1:0, secure_scratch14, 25:24);
+	s(McSecCarveoutProtectWriteAccess, 0:0, secure_scratch14, 26:26);
+	s(McMtsCarveoutRegCtrl, 0:0, secure_scratch14, 27:27);
+	s(McMtsCarveoutSizeMb, 11:0, secure_scratch15, 11:0);
+	s(McEmemAdrCfgDev0, 2:0, secure_scratch15, 14:12);
+	s(McEmemAdrCfgDev0, 9:8, secure_scratch15, 16:15);
+	s(McEmemAdrCfgDev0, 19:16, secure_scratch15, 20:17);
+	s(McEmemAdrCfgDev1, 2:0, secure_scratch15, 23:21);
+	s(McEmemAdrCfgDev1, 9:8, secure_scratch15, 25:24);
+	s(McEmemAdrCfgDev1, 19:16, secure_scratch15, 29:26);
+
+	/* Make sure all writes complete before we lock the secure_scratchs. */
+	//dmb(); FIX:dmd command doesn't support in thumb mode
+	c(0x1555555, sec_disable2, 25:0);
+	c(0xff, sec_disable, 19:12);
+
+	c(0, scratch2, 31:0);
+	m(pllm_base, 15:0, scratch2, 15:0);
+	m(pllm_base, 20:20, scratch2, 16:16);
+	m(pllm_misc2, 2:0, scratch2, 19:17);
+	c(0, scratch35, 31:0);
+	m(pllm_misc1, 23:0, scratch35, 23:0);
+	m(pllm_misc1, 30:28, scratch35, 30:28);
+	c(0, scratch3, 31:0);
+	s(PllMInputDivider, 7:0, scratch3, 7:0);
+	c(0x3e, scratch3, 15:8);
+	c(0, scratch3, 19:16);
+	s(PllMKVCO, 0:0, scratch3, 20:20);
+	s(PllMKCP, 1:0, scratch3, 22:21);
+	c(0, scratch36, 31:0);
+	s(PllMSetupControl, 23:0, scratch36, 23:0);
+	c(0, scratch4, 31:0);
+	s(PllMStableTime, 9:0, scratch4, 9:0);
+	s(PllMStableTime, 9:0, scratch4, 19:10);
+
+	s(PllMSelectDiv2, 0:0, pllm_wb0_override2, 27:27);
+	s(PllMKVCO, 0:0, pllm_wb0_override2, 26:26);
+	s(PllMKCP, 1:0, pllm_wb0_override2, 25:24);
+	s(PllMSetupControl, 23:0, pllm_wb0_override2, 23:0);
+	s(PllMFeedbackDivider, 7:0, pllm_wb0_override_freq, 15:8);
+	s(PllMInputDivider, 7:0, pllm_wb0_override_freq, 7:0);
+
+	/* Need to ensure override params are written before we activate it. */
+	//dmb(); FIX:dmb convert to Thumb command
+	c(3, pllp_wb0_override, 12:11);
+}
--- a/loader/sdram_lp0.h
+++ b/loader/sdram_lp0.h
@ -0,0 +1,437 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+/**
+ * Defines the SDRAM parameter structure.
+ *
+ * Note that PLLM is used by EMC. The field names are in camel case to ease
+ * directly converting BCT config files (*.cfg) into C structure.
+ */
+
+#ifndef _T124_SDRAM_LP0_
+#define _T124_SDRAM_LP0_
+
+#include <stddef.h>
+#include <stdint.h>
+#include "types.h"
+
+void sdram_lp0_save_params(const sdram_params_t124 *sdram);
+
+// Memory Controller registers we need/care about
+struct tegra_mc_regs {
+	u32 rsvd_0x0[4];			/* 0x00 */
+	u32 smmu_config;			/* 0x10 */
+	u32 smmu_tlb_config;		/* 0x14 */
+	u32 smmu_ptc_config;		/* 0x18 */
+	u32 smmu_ptb_asid;			/* 0x1c */
+	u32 smmu_ptb_data;			/* 0x20 */
+	u32 rsvd_0x24[3];			/* 0x24 */
+	u32 smmu_tlb_flush;		/* 0x30 */
+	u32 smmu_ptc_flush;		/* 0x34 */
+	u32 rsvd_0x38[6];			/* 0x38 */
+	u32 emem_cfg;			/* 0x50 */
+	u32 emem_adr_cfg;			/* 0x54 */
+	u32 emem_adr_cfg_dev0;		/* 0x58 */
+	u32 emem_adr_cfg_dev1;		/* 0x5c */
+	u32 rsvd_0x60[1];			/* 0x60 */
+	u32 emem_adr_cfg_bank_mask_0;	/* 0x64 */
+	u32 emem_adr_cfg_bank_mask_1;	/* 0x68 */
+	u32 emem_adr_cfg_bank_mask_2;	/* 0x6c */
+	u32 rsvd_0x70[8];			/* 0x70 */
+	u32 emem_arb_cfg;			/* 0x90 */
+	u32 emem_arb_outstanding_req;	/* 0x94 */
+	u32 emem_arb_timing_rcd;		/* 0x98 */
+	u32 emem_arb_timing_rp;		/* 0x9c */
+	u32 emem_arb_timing_rc;		/* 0xa0 */
+	u32 emem_arb_timing_ras;		/* 0xa4 */
+	u32 emem_arb_timing_faw;		/* 0xa8 */
+	u32 emem_arb_timing_rrd;		/* 0xac */
+	u32 emem_arb_timing_rap2pre;	/* 0xb0 */
+	u32 emem_arb_timing_wap2pre;	/* 0xb4 */
+	u32 emem_arb_timing_r2r;		/* 0xb8 */
+	u32 emem_arb_timing_w2w;		/* 0xbc */
+	u32 emem_arb_timing_r2w;		/* 0xc0 */
+	u32 emem_arb_timing_w2r;		/* 0xc4 */
+	u32 rsvd_0xc8[2];			/* 0xc8 */
+	u32 emem_arb_da_turns;		/* 0xd0 */
+	u32 emem_arb_da_covers;		/* 0xd4 */
+	u32 emem_arb_misc0;		/* 0xd8 */
+	u32 emem_arb_misc1;		/* 0xdc */
+	u32 emem_arb_ring1_throttle;	/* 0xe0 */
+	u32 emem_arb_ring3_throttle;	/* 0xe4 */
+	u32 emem_arb_override;		/* 0xe8 */
+	u32 emem_arb_rsv;			/* 0xec */
+	u32 rsvd_0xf0[1];			/* 0xf0 */
+	u32 clken_override;		/* 0xf4 */
+	u32 timing_control_dbg;		/* 0xf8 */
+	u32 timing_control;		/* 0xfc */
+	u32 stat_control;			/* 0x100 */
+	u32 rsvd_0x104[65];		/* 0x104 */
+	u32 emem_arb_isochronous_0;	/* 0x208 */
+	u32 emem_arb_isochronous_1;	/* 0x20c */
+	u32 emem_arb_isochronous_2;	/* 0x210 */
+	u32 rsvd_0x214[38];		/* 0x214 */
+	u32 dis_extra_snap_levels;		/* 0x2ac */
+	u32 rsvd_0x2b0[90];		/* 0x2b0 */
+	u32 video_protect_vpr_override;	/* 0x418 */
+	u32 rsvd_0x41c[93];		/* 0x41c */
+	u32 video_protect_vpr_override1;	/* 0x590 */
+	u32 rsvd_0x594[29];		/* 0x594 */
+	u32 display_snap_ring;		/* 0x608 */
+	u32 rsvd_0x60c[15];		/* 0x60c */
+	u32 video_protect_bom;		/* 0x648 */
+	u32 video_protect_size_mb;		/* 0x64c */
+	u32 video_protect_reg_ctrl;	/* 0x650 */
+	u32 rsvd_0x654[4];			/* 0x654 */
+	u32 emem_cfg_access_ctrl;		/* 0x664 */
+	u32 rsvd_0x668[2];			/* 0x668 */
+	u32 sec_carveout_bom;		/* 0x670 */
+	u32 sec_carveout_size_mb;		/* 0x674 */
+	u32 sec_carveout_reg_ctrl;		/* 0x678 */
+	u32 rsvd_0x67c[187];		/* 0x67c */
+	u32 emem_arb_override_1;		/* 0x968 */
+	u32 rsvd_0x96c[3];			/* 0x96c */
+	u32 video_protect_bom_adr_hi;	/* 0x978 */
+	u32 rsvd_0x97c[2];			/* 0x97c */
+	u32 video_protect_gpu_override_0;	/* 0x984 */
+	u32 video_protect_gpu_override_1;	/* 0x988 */
+	u32 rsvd_0x98c[5];			/* 0x98c */
+	u32 mts_carveout_bom;		/* 0x9a0 */
+	u32 mts_carveout_size_mb;		/* 0x9a4 */
+	u32 mts_carveout_adr_hi;		/* 0x9a8 */
+	u32 mts_carveout_reg_ctrl;		/* 0x9ac */
+	u32 rsvd_0x9b0[4];			/* 0x9b0 */
+	u32 emem_bank_swizzle_cfg0;	/* 0x9c0 */
+	u32 emem_bank_swizzle_cfg1;	/* 0x9c4 */
+	u32 emem_bank_swizzle_cfg2;	/* 0x9c8 */
+	u32 emem_bank_swizzle_cfg3;	/* 0x9cc */
+	u32 rsvd_0x9d0[1];			/* 0x9d0 */
+	u32 sec_carveout_adr_hi;		/* 0x9d4 */
+};
+
+enum {
+	MC_EMEM_CFG_SIZE_MB_SHIFT = 0,
+	MC_EMEM_CFG_SIZE_MB_MASK = 0x3fff,
+
+	MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27,
+	MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27,
+
+	MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED = 1,
+
+	MC_TIMING_CONTROL_TIMING_UPDATE = 1,
+};
+
+struct tegra_emc_regs {
+	u32 intstatus;		/* 0x0 */
+	u32 intmask;		/* 0x4 */
+	u32 dbg;			/* 0x8 */
+	u32 cfg;			/* 0xc */
+	u32 adr_cfg;		/* 0x10 */
+	u32 rsvd_0x14[3];		/* 0x14 */
+
+	u32 refctrl;		/* 0x20 */
+	u32 pin;			/* 0x24 */
+	u32 timing_control;	/* 0x28 */
+	u32 rc;			/* 0x2c */
+	u32 rfc;			/* 0x30 */
+	u32 ras;			/* 0x34 */
+	u32 rp;			/* 0x38 */
+	u32 r2w;			/* 0x3c */
+	u32 w2r;			/* 0x40 */
+	u32 r2p;			/* 0x44 */
+	u32 w2p;			/* 0x48 */
+	u32 rd_rcd;		/* 0x4c */
+	u32 wr_rcd;		/* 0x50 */
+	u32 rrd;			/* 0x54 */
+	u32 rext;			/* 0x58 */
+	u32 wdv;			/* 0x5c */
+	u32 quse;			/* 0x60 */
+	u32 qrst;			/* 0x64 */
+	u32 qsafe;			/* 0x68 */
+	u32 rdv;			/* 0x6c */
+	u32 refresh;		/* 0x70 */
+	u32 burst_refresh_num;	/* 0x74 */
+	u32 pdex2wr;		/* 0x78 */
+	u32 pdex2rd;		/* 0x7c */
+	u32 pchg2pden;		/* 0x80 */
+	u32 act2pden;		/* 0x84 */
+	u32 ar2pden;		/* 0x88 */
+	u32 rw2pden;		/* 0x8c */
+	u32 txsr;			/* 0x90 */
+	u32 tcke;			/* 0x94 */
+	u32 tfaw;			/* 0x98 */
+	u32 trpab;			/* 0x9c */
+	u32 tclkstable;		/* 0xa0 */
+	u32 tclkstop;		/* 0xa4 */
+	u32 trefbw;		/* 0xa8 */
+	u32 rsvd_0xac[1];		/* 0xac */
+	u32 odt_write;		/* 0xb0 */
+	u32 odt_read;		/* 0xb4 */
+	u32 wext;			/* 0xb8 */
+	u32 ctt;			/* 0xbc */
+	u32 rfc_slr;		/* 0xc0 */
+	u32 mrs_wait_cnt2;		/* 0xc4 */
+	u32 mrs_wait_cnt;		/* 0xc8 */
+	u32 mrs;			/* 0xcc */
+	u32 emrs;			/* 0xd0 */
+	u32 ref;			/* 0xd4 */
+	u32 pre;			/* 0xd8 */
+	u32 nop;			/* 0xdc */
+	u32 self_ref;		/* 0xe0 */
+	u32 dpd;			/* 0xe4 */
+	u32 mrw;			/* 0xe8 */
+	u32 mrr;			/* 0xec */
+	u32 cmdq;			/* 0xf0 */
+	u32 mc2emcq;		/* 0xf4 */
+	u32 xm2dqspadctrl3;	/* 0xf8 */
+	u32 rsvd_0xfc[1];		/* 0xfc */
+	u32 fbio_spare;		/* 0x100 */
+	u32 fbio_cfg5;		/* 0x104 */
+	u32 fbio_wrptr_eq_2;	/* 0x108 */
+	u32 rsvd_0x10c[2];		/* 0x10c */
+
+	u32 fbio_cfg6;		/* 0x114 */
+	u32 rsvd_0x118[2];		/* 0x118 */
+
+	u32 cfg_rsv;		/* 0x120 */
+	u32 acpd_control;		/* 0x124 */
+	u32 rsvd_0x128[1];		/* 0x128 */
+	u32 emrs2;			/* 0x12c */
+	u32 emrs3;			/* 0x130 */
+	u32 mrw2;			/* 0x134 */
+	u32 mrw3;			/* 0x138 */
+	u32 mrw4;			/* 0x13c */
+	u32 clken_override;	/* 0x140 */
+	u32 r2r;			/* 0x144 */
+	u32 w2w;			/* 0x148 */
+	u32 einput;		/* 0x14c */
+	u32 einput_duration;	/* 0x150 */
+	u32 puterm_extra;		/* 0x154 */
+	u32 tckesr;		/* 0x158 */
+	u32 tpd;			/* 0x15c */
+	u32 rsvd_0x160[81];		/* 0x160 */
+
+	u32 auto_cal_config;	/* 0x2a4 */
+	u32 auto_cal_interval;	/* 0x2a8 */
+	u32 auto_cal_status;	/* 0x2ac */
+	u32 req_ctrl;		/* 0x2b0 */
+	u32 status;		/* 0x2b4 */
+	u32 cfg_2;			/* 0x2b8 */
+	u32 cfg_dig_dll;		/* 0x2bc */
+	u32 cfg_dig_dll_period;	/* 0x2c0 */
+	u32 rsvd_0x2c4[1];		/* 0x2c4 */
+	u32 dig_dll_status;	/* 0x2c8 */
+	u32 rdv_mask;		/* 0x2cc */
+	u32 wdv_mask;		/* 0x2d0 */
+	u32 rsvd_0x2d4[1];		/* 0x2d4 */
+	u32 ctt_duration;		/* 0x2d8 */
+	u32 ctt_term_ctrl;		/* 0x2dc */
+	u32 zcal_interval;		/* 0x2e0 */
+	u32 zcal_wait_cnt;		/* 0x2e4 */
+	u32 zcal_mrw_cmd;		/* 0x2e8 */
+	u32 zq_cal;		/* 0x2ec */
+	u32 xm2cmdpadctrl;		/* 0x2f0 */
+	u32 xm2cmdpadctrl2;	/* 0x2f4 */
+	u32 xm2dqspadctrl;		/* 0x2f8 */
+	u32 xm2dqspadctrl2;	/* 0x2fc */
+	u32 xm2dqpadctrl;		/* 0x300 */
+	u32 xm2dqpadctrl2;		/* 0x304 */
+	u32 xm2clkpadctrl;		/* 0x308 */
+	u32 xm2comppadctrl;	/* 0x30c */
+	u32 xm2vttgenpadctrl;	/* 0x310 */
+	u32 xm2vttgenpadctrl2;	/* 0x314 */
+	u32 xm2vttgenpadctrl3;	/* 0x318 */
+	u32 emcpaden;		/* 0x31c */
+	u32 xm2dqspadctrl4;	/* 0x320 */
+	u32 scratch0;		/* 0x324 */
+	u32 dll_xform_dqs0;	/* 0x328 */
+	u32 dll_xform_dqs1;	/* 0x32c */
+	u32 dll_xform_dqs2;	/* 0x330 */
+	u32 dll_xform_dqs3;	/* 0x334 */
+	u32 dll_xform_dqs4;	/* 0x338 */
+	u32 dll_xform_dqs5;	/* 0x33c */
+	u32 dll_xform_dqs6;	/* 0x340 */
+	u32 dll_xform_dqs7;	/* 0x344 */
+	u32 dll_xform_quse0;	/* 0x348 */
+	u32 dll_xform_quse1;	/* 0x34c */
+	u32 dll_xform_quse2;	/* 0x350 */
+	u32 dll_xform_quse3;	/* 0x354 */
+	u32 dll_xform_quse4;	/* 0x358 */
+	u32 dll_xform_quse5;	/* 0x35c */
+	u32 dll_xform_quse6;	/* 0x360 */
+	u32 dll_xform_quse7;	/* 0x364 */
+	u32 dll_xform_dq0;		/* 0x368 */
+	u32 dll_xform_dq1;		/* 0x36c */
+	u32 dll_xform_dq2;		/* 0x370 */
+	u32 dll_xform_dq3;		/* 0x374 */
+	u32 dli_rx_trim0;		/* 0x378 */
+	u32 dli_rx_trim1;		/* 0x37c */
+	u32 dli_rx_trim2;		/* 0x380 */
+	u32 dli_rx_trim3;		/* 0x384 */
+	u32 dli_rx_trim4;		/* 0x388 */
+	u32 dli_rx_trim5;		/* 0x38c */
+	u32 dli_rx_trim6;		/* 0x390 */
+	u32 dli_rx_trim7;		/* 0x394 */
+	u32 dli_tx_trim0;		/* 0x398 */
+	u32 dli_tx_trim1;		/* 0x39c */
+	u32 dli_tx_trim2;		/* 0x3a0 */
+	u32 dli_tx_trim3;		/* 0x3a4 */
+	u32 dli_trim_txdqs0;	/* 0x3a8 */
+	u32 dli_trim_txdqs1;	/* 0x3ac */
+	u32 dli_trim_txdqs2;	/* 0x3b0 */
+	u32 dli_trim_txdqs3;	/* 0x3b4 */
+	u32 dli_trim_txdqs4;	/* 0x3b8 */
+	u32 dli_trim_txdqs5;	/* 0x3bc */
+	u32 dli_trim_txdqs6;	/* 0x3c0 */
+	u32 dli_trim_txdqs7;	/* 0x3c4 */
+	u32 rsvd_0x3c8[1];		/* 0x3c8 */
+	u32 stall_then_exe_after_clkchange;	/* 0x3cc */
+	u32 rsvd_0x3d0[1];		/* 0x3d0 */
+	u32 auto_cal_clk_status;	/* 0x3d4 */
+	u32 sel_dpd_ctrl;		/* 0x3d8 */
+	u32 pre_refresh_req_cnt;	/* 0x3dc */
+	u32 dyn_self_ref_control;	/* 0x3e0 */
+	u32 txsrdll;		/* 0x3e4 */
+	u32 ccfifo_addr;		/* 0x3e8 */
+	u32 ccfifo_data;		/* 0x3ec */
+	u32 ccfifo_status;		/* 0x3f0 */
+	u32 cdb_cntl_1;		/* 0x3f4 */
+	u32 cdb_cntl_2;		/* 0x3f8 */
+	u32 xm2clkpadctrl2;	/* 0x3fc */
+	u32 swizzle_rank0_byte_cfg;	/* 0x400 */
+	u32 swizzle_rank0_byte0;	/* 0x404 */
+	u32 swizzle_rank0_byte1;	/* 0x408 */
+	u32 swizzle_rank0_byte2;	/* 0x40c */
+	u32 swizzle_rank0_byte3;	/* 0x410 */
+	u32 swizzle_rank1_byte_cfg;	/* 0x414 */
+	u32 swizzle_rank1_byte0;	/* 0x418 */
+	u32 swizzle_rank1_byte1;	/* 0x41c */
+	u32 swizzle_rank1_byte2;	/* 0x420 */
+	u32 swizzle_rank1_byte3;	/* 0x424 */
+	u32 ca_training_start;	/* 0x428 */
+	u32 ca_training_busy;	/* 0x42c */
+	u32 ca_training_cfg;	/* 0x430 */
+	u32 ca_training_timing_cntl1;	/* 0x434 */
+	u32 ca_training_timing_cntl2;	/* 0x438 */
+	u32 ca_training_ca_lead_in;	/* 0x43c */
+	u32 ca_training_ca;	/* 0x440 */
+	u32 ca_training_ca_lead_out;	/* 0x444 */
+	u32 ca_training_result1;	/* 0x448 */
+	u32 ca_training_result2;	/* 0x44c */
+	u32 ca_training_result3;	/* 0x450 */
+	u32 ca_training_result4;	/* 0x454 */
+	u32 auto_cal_config2;	/* 0x458 */
+	u32 auto_cal_config3;	/* 0x45c */
+	u32 auto_cal_status2;	/* 0x460 */
+	u32 xm2cmdpadctrl3;	/* 0x464 */
+	u32 ibdly;			/* 0x468 */
+	u32 dll_xform_addr0;	/* 0x46c */
+	u32 dll_xform_addr1;	/* 0x470 */
+	u32 dll_xform_addr2;	/* 0x474 */
+	u32 dli_addr_trim;		/* 0x478 */
+	u32 dsr_vttgen_drv;	/* 0x47c */
+	u32 txdsrvttgen;		/* 0x480 */
+	u32 xm2cmdpadctrl4;	/* 0x484 */
+	u32 xm2cmdpadctrl5;	/* 0x488 */
+	u32 rsvd_0x48c[5];		/* 0x48c */
+
+	u32 dll_xform_dqs8;	/* 0x4a0 */
+	u32 dll_xform_dqs9;	/* 0x4a4 */
+	u32 dll_xform_dqs10;	/* 0x4a8 */
+	u32 dll_xform_dqs11;	/* 0x4ac */
+	u32 dll_xform_dqs12;	/* 0x4b0 */
+	u32 dll_xform_dqs13;	/* 0x4b4 */
+	u32 dll_xform_dqs14;	/* 0x4b8 */
+	u32 dll_xform_dqs15;	/* 0x4bc */
+	u32 dll_xform_quse8;	/* 0x4c0 */
+	u32 dll_xform_quse9;	/* 0x4c4 */
+	u32 dll_xform_quse10;	/* 0x4c8 */
+	u32 dll_xform_quse11;	/* 0x4cc */
+	u32 dll_xform_quse12;	/* 0x4d0 */
+	u32 dll_xform_quse13;	/* 0x4d4 */
+	u32 dll_xform_quse14;	/* 0x4d8 */
+	u32 dll_xform_quse15;	/* 0x4dc */
+	u32 dll_xform_dq4;		/* 0x4e0 */
+	u32 dll_xform_dq5;		/* 0x4e4 */
+	u32 dll_xform_dq6;		/* 0x4e8 */
+	u32 dll_xform_dq7;		/* 0x4ec */
+	u32 rsvd_0x4f0[12];		/* 0x4f0 */
+
+	u32 dli_trim_txdqs8;	/* 0x520 */
+	u32 dli_trim_txdqs9;	/* 0x524 */
+	u32 dli_trim_txdqs10;	/* 0x528 */
+	u32 dli_trim_txdqs11;	/* 0x52c */
+	u32 dli_trim_txdqs12;	/* 0x530 */
+	u32 dli_trim_txdqs13;	/* 0x534 */
+	u32 dli_trim_txdqs14;	/* 0x538 */
+	u32 dli_trim_txdqs15;	/* 0x53c */
+	u32 cdb_cntl_3;		/* 0x540 */
+	u32 xm2dqspadctrl5;	/* 0x544 */
+	u32 xm2dqspadctrl6;	/* 0x548 */
+	u32 xm2dqpadctrl3;		/* 0x54c */
+	u32 dll_xform_addr3;	/* 0x550 */
+	u32 dll_xform_addr4;	/* 0x554 */
+	u32 dll_xform_addr5;	/* 0x558 */
+	u32 rsvd_0x55c[1];		/* 0x55c */
+	u32 cfg_pipe;		/* 0x560 */
+	u32 qpop;			/* 0x564 */
+	u32 quse_width;		/* 0x568 */
+	u32 puterm_width;		/* 0x56c */
+	u32 bgbias_ctl0;		/* 0x570 */
+	u32 puterm_adj;		/* 0x574 */
+} __packed;
+
+
+enum {
+	EMC_PIN_RESET_MASK = 1 << 8,
+	EMC_PIN_RESET_ACTIVE = 0 << 8,
+	EMC_PIN_RESET_INACTIVE = 1 << 8,
+	EMC_PIN_DQM_MASK = 1 << 4,
+	EMC_PIN_DQM_NORMAL = 0 << 4,
+	EMC_PIN_DQM_INACTIVE = 1 << 4,
+	EMC_PIN_CKE_MASK = 1 << 0,
+	EMC_PIN_CKE_POWERDOWN = 0 << 0,
+	EMC_PIN_CKE_NORMAL = 1 << 0,
+
+	EMC_REF_CMD_MASK = 1 << 0,
+	EMC_REF_CMD_REFRESH = 1 << 0,
+	EMC_REF_NORMAL_MASK = 1 << 1,
+	EMC_REF_NORMAL_INIT = 0 << 1,
+	EMC_REF_NORMAL_ENABLED = 1 << 1,
+	EMC_REF_NUM_SHIFT = 8,
+	EMC_REF_NUM_MASK = 0xFF << EMC_REF_NUM_SHIFT,
+	EMC_REF_DEV_SELECTN_SHIFT = 30,
+	EMC_REF_DEV_SELECTN_MASK = 3 << EMC_REF_DEV_SELECTN_SHIFT,
+
+	EMC_REFCTRL_REF_VALID_MASK = 1 << 31,
+	EMC_REFCTRL_REF_VALID_DISABLED = 0 << 31,
+	EMC_REFCTRL_REF_VALID_ENABLED = 1 << 31,
+
+	EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK = 1 << 1,
+	EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK = 1 << 2,
+	EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK = 1 << 3,
+
+	EMC_NOP_NOP_CMD_SHIFT = 0,
+	EMC_NOP_NOP_CMD_MASK = 1 << EMC_NOP_NOP_CMD_SHIFT,
+	EMC_NOP_NOP_DEV_SELECTN_SHIFT = 30,
+	EMC_NOP_NOP_DEV_SELECTN_MASK = 3 << EMC_NOP_NOP_DEV_SELECTN_SHIFT,
+
+	EMC_TIMING_CONTROL_TIMING_UPDATE = 1,
+};
+
+#endif /* __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ */
+
+
+
+
--- a/loader/t124.h
+++ b/loader/t124.h
@ -24,12 +24,18 @@
 #define PMC_BASE 0x7000E400 //2k e400-ebff length
 #define CLOCK_BASE 0x60006000
 #define TIMER0_BASE 0x60005000
-#define MC_BASE 0x70018000
+#define MC_BASE 0x70019000
 #define SYSCTR0_BASE     0x700F0000
 #define APB_MISC_BASE 0x70000000
 #define PINMUX_AUX_BASE 0x70003000
 #define I2C_BASE         0x7000C000
 #define UART_BASE 0x70006000
+#define EMC_BASE 0x7001B000
+#define SYSREG_BASE 0x6000C000
+#define BPMP_CACHE_BASE  0x50040000
+#define IRAM_BASE        0x40000000
+
+#define DRAM_START     0x80000000

 #define MMIO_REG32(base, off) *(vu32 *)((base) + (off))

@ -44,11 +50,17 @@
 #define PINMUX_AUX(off)         MMIO_REG32(PINMUX_AUX_BASE, off)
 #define I2C(off)                MMIO_REG32(I2C_BASE, off)
 #define UART(off)               MMIO_REG32(UART_BASE, off)
+#define EMC(off)                MMIO_REG32(EMC_BASE, off)
+#define SYSREG(off)             MMIO_REG32(SYSREG_BASE, off)
+#define BPMP_CACHE_CTRL(off)    MMIO_REG32(BPMP_CACHE_BASE, off)

 //PMC
 #define APBDEV_PMC_CRYPTO_OP 0xF4
 #define SYSCTR0_CNTFID0 0x20

+//System registers
+//#define AHB_ARBITRATION_XBAR_CTRL            0xE0
+
 //GPIO
 #define APB_MISC_PP_PINMUX_GLOBAL 0x40

--- a/loader/types.h
+++ b/loader/types.h
@ -33,6 +33,34 @@ typedef volatile u64 vu64;
 typedef u32 size_t;
 typedef u32 uintptr_t;

+/* Sizes */
+#define SZ_1K   0x400
+#define SZ_2K   0x800
+#define SZ_4K   0x1000
+#define SZ_8K   0x2000
+#define SZ_16K  0x4000
+#define SZ_32K  0x8000
+#define SZ_64K  0x10000
+#define SZ_128K 0x20000
+#define SZ_256K 0x40000
+#define SZ_512K 0x80000
+#define SZ_1M   0x100000
+#define SZ_2M   0x200000
+#define SZ_4M   0x400000
+#define SZ_8M   0x800000
+#define SZ_16M  0x1000000
+#define SZ_32M  0x2000000
+#define SZ_64M  0x4000000
+#define SZ_128M 0x8000000
+#define SZ_256M 0x10000000
+#define SZ_512M 0x20000000
+#define SZ_1G   0x40000000
+#define SZ_2G   0x80000000
+#define SZ_PAGE SZ_4K
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))
+
 #define BIT(n) (1U << (n))
 #define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))
+#define ALIGN_DOWN(x, a) ((x) & ~((a) - 1))
 #endif