EljakimHerrewijnen/gardenia
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refactor:Clean up all code of clocks and registers.

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We need to rewrite the code from coreboot or uboot's porting for Tegra T124.Instead of simply learning the init process from hekate.(Many heakte codes are only in Tegra T210)
This commit is contained in:
hydrogenium2020 2024-01-21 16:39:28 +08:00
parent a84c7a7f9d
commit b5d514cfac
12 changed files with 13 additions and 126 deletions
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2
.gitignore vendored
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@ -1,3 +1,5 @@
.vs .vs
.vscode .vscode
build/* build/*
*.bin
prebuilt/*

45
loader/clock.c
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@ -20,19 +20,7 @@
#include "pmc.h" #include "pmc.h"
#include "printf.h" #include "printf.h"
#include "util.h" #include "util.h"
static clk_rst_t _clock_cl_dvfs = { 0x35C, 0x364, 0, 0x1B, 0, 0 }; #include "types.h"
//I2C default parameters - TLOW: 4, THIGH: 2, DEBOUNCE: 0, FM_DIV: 26.
static const clk_rst_t _clock_i2c[] = {
{ CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 12, 0, 19 }, //20.4MHz -> 100KHz
{ CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2, 22, 0, 4 }, //81.6MHz -> 400KHz
{ 0, 0, 0, 0, 0, 4 }, //81.6MHz -> 400KHz
{ 0, 0, 0, 0, 0, 19 }, //20.4MHz -> 100KHz
{ CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 15, 0, 4 }, //81.6MHz -> 400KHz
{ 0, 0, 0, 0, 0, 19 } //20.4MHz -> 100KHz
};
void clock_enable(const clk_rst_t *clk) void clock_enable(const clk_rst_t *clk)
{ {
@ -80,36 +68,5 @@ void clock_disable(const clk_rst_t *clk)
void config_oscillators() void config_oscillators()
{ {
CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 0; // Clear 3-2bit and set CLK_M_DIVISOR to 1.the 3-2bit is divisor.
SYSCTR0(SYSCTR0_CNTFID0) = 12000000; // Set counter frequency. 12Mhz
//This register is for 1 microsecond. bit7-0->DIVISOR bit15-8->DIVIDEND.So we need 1/12
TIMER0(TIMERUS_USEC_CFG) = 0x0B; // For 12MHz clk_m. 1/12 -> 0x00/0x0b
CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x80000071; // Set OSC to 12MHz and drive strength.
PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81) | 0xE; // Set LP0 OSC drive strength.
PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF) | PMC_OSC_EDPD_OVER_OSC_CTRL_OVER;
PMC(APBDEV_PMC_CNTRL2) = (PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF) | PMC_CNTRL2_HOLD_CKE_LOW_EN;
//Not impl in T124?Only in T210 and newer
//PMC(APB_MISC_GP_ASDBGREG) = (PMC(APB_MISC_GP_ASDBGREG) & 0xFCFFFFFF) | (2 << 24); // CFG2TMC_RAM_SVOP_PDP.
CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x00; // Set HCLK div to 1 and PCLK div to 1.
//CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF; // PLLMB disable.
PMC(APBDEV_PMC_TSC_MULT) = (PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000) | 0x16E0; // 0x249F = 12000000 * (16 / 32.768 kHz).
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set BPMP/SCLK div to 1.
CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set BPMP/SCLK source to Run and PLLP_OUT2 (204MHz).
CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; // Enable SUPER_SDIV to 1.
CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3.
} }
void clock_enable_cl_dvfs(){
clock_enable(&_clock_cl_dvfs);
}
void clock_enable_i2c(u32 idx)
{
clock_enable(&_clock_i2c[idx]);
}

20
loader/clock.h
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@ -27,26 +27,8 @@ typedef struct _clk_rst_t
u8 clk_div; u8 clk_div;
} clk_rst_t; } clk_rst_t;
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19c #define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0 0x19c
#define CLK_RST_CONTROLLER_CLK_ENB_H_SET 0x328
#define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284
#define CLK_RST_CONTROLLER_RST_DEV_H_SET 0x308
#define CLK_RST_CONTROLLER_SPARE_REG0 0x55c
#define CLK_RST_CONTROLLER_OSC_CTRL 0x50
#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30
#define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400
#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY 0x28
#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER 0x2c
//I2C
#define CLK_RST_CONTROLLER_RST_DEVICES_L 0x4
#define CLK_RST_CONTROLLER_RST_DEVICES_H 0x8
#define CLK_RST_CONTROLLER_RST_DEVICES_U 0xC
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 0x198
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H 0x14
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 0x124
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 0x128
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L 0x10
void clock_enable(const clk_rst_t *clk); void clock_enable(const clk_rst_t *clk);
void clock_disable(const clk_rst_t *clk); void clock_disable(const clk_rst_t *clk);
void clock_enable_cl_dvfs(); void clock_enable_cl_dvfs();

4
loader/gpio.c
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@ -18,7 +18,5 @@
#include "i2c.h" #include "i2c.h"
#include "pinmux.h" #include "pinmux.h"
void config_gpios(){ void config_gpios(){
APB_MISC(APB_MISC_PP_PINMUX_GLOBAL) = 0;
pinmux_config_i2c(I2C_1);
pinmux_config_i2c(I2C_5);
} }

17
loader/main.c
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@ -66,23 +66,18 @@ void config_hw(){
fuse_disable_program(); fuse_disable_program();
printf_("[x] fuse program disabled\n"); printf_("[x] fuse program disabled\n");
// Initialize counters, CLKM, BPMP(also called AVP in T124/T132) and other clocks based on 38.4MHz oscillator.
config_oscillators();
mc_enable(); mc_enable();
printf_("[x] mc setup\n"); printf_("[x] mc setup\n");
// Initialize counters, CLKM, BPMP(also called AVP in T124/T132) and other clocks based on 38.4MHz oscillator.
config_oscillators();
printf_("[x] Oscillators setup at 12Mhz\n");
printf_("\tCLK_M:12Mhz\n");
printf_("\tCLK_S:32.768khz\n");
printf_("\tSystem CLK:127.5Mhz\n");
printf_("\tHCLK: 127.5Mhz\n");
printf_("\tPCLK: 31.875Mhz\n");
config_gpios(); config_gpios();
printf_("[x] GPIO setup\n"); printf_("[x] GPIO setup\n");
clock_enable_cl_dvfs(); //clock_enable_cl_dvfs();
printf_("[x] DVFS setup\n"); //printf_("[x] DVFS setup\n");
//FIXME I2C Doesn't work!!! //FIXME I2C Doesn't work!!!
printf_("Fixme.I2C doesn't work"); printf_("Fixme.I2C doesn't work");

22
loader/mc.c
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@ -20,29 +20,7 @@
#include "util.h" #include "util.h"
#include "mc.h" #include "mc.h"
void mc_disable_ahb_redirect()
{
MC(MC_IRAM_BOM) = 0xFFFFF000;
MC(MC_IRAM_TOM) = 0;
//Disable IRAM_CFG_WRITE_ACCESS (sticky).
//MC(MC_IRAM_REG_CTRL) = MC(MC_IRAM_REG_CTRL) & 0xFFFFFFFE | 1;
CLOCK(0x3A4) &= 0xFFF7FFFF;
}
void mc_enable() void mc_enable()
{ {
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF | 0x40000000;
//Enable MIPI CAL clock.
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFDFFFFFF | 0x2000000;
//Enable MC clock.
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFFFFFFFE | 1;
//Enable EMC DLL clock.
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) & 0xFFFFBFFF | 0x4000;
CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x2000001; //Clear EMC and MC reset.
//#ifdef CONFIG_ENABLE_AHB_REDIRECT
mc_disable_ahb_redirect();
//mc_enable_ahb_redirect();
//#endif
} }

4
loader/mc.h
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@ -14,7 +14,5 @@
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>. * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#define MC_IRAM_BOM 0x65c
#define MC_IRAM_TOM 0x660
#define MC_LATENCY_ALLOWANCE_A9AVP 0x3a4
void mc_enable(); void mc_enable();

5
loader/pinmux.c
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@ -16,8 +16,3 @@
*/ */
#include "t124.h" #include "t124.h"
#include "pinmux.h" #include "pinmux.h"
void pinmux_config_i2c(u32 idx)
{
PINMUX_AUX(PINMUX_AUX_X_I2C_SCL(idx)) = 0x40;
PINMUX_AUX(PINMUX_AUX_X_I2C_SDA(idx)) = 0x40;
}

4
loader/pinmux.h
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@ -16,6 +16,4 @@
*/ */
void pinmux_config_i2c(u32 idx); void pinmux_config_i2c(u32 idx);
/*! 0:GEN1, 1:GEN2, 2:GEN3, 3:CAM, 4:PWR */
#define PINMUX_AUX_X_I2C_SCL(x) (0xBC + 8 * (x))
#define PINMUX_AUX_X_I2C_SDA(x) (0xC0 + 8 * (x))

6
loader/pmc.h
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@ -15,9 +15,3 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>. * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#include "types.h" #include "types.h"
#define APBDEV_PMC_OSC_EDPD_OVER 0x1a4
#define APBDEV_PMC_CNTRL2 0x440
#define APBDEV_PMC_TSC_MULT 0x2B4
#define PMC_OSC_EDPD_OVER_OSC_CTRL_OVER BIT(22)
#define PMC_CNTRL2_HOLD_CKE_LOW_EN BIT(12)

2
loader/power.h
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@ -17,7 +17,5 @@
#ifndef _T124_POWER_H_ #ifndef _T124_POWER_H_
#define _T124_POWER_H_ #define _T124_POWER_H_
#define TPS65913_I2C_ADDR 0xB0
#define PMU_EEPROM_I2C_ADDR 0xAA
#endif #endif

8
loader/se.h
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@ -18,12 +18,4 @@
#ifndef _T124_SE_H_ #ifndef _T124_SE_H_
#define _T124_SE_H_ #define _T124_SE_H_
#define SE_KEYTABLE_REG_OFFSET 0x31c
#define SE_KEYTABLE_SLOT_SHIFT 7
#define SE_KEYTABLE_SLOT(x) (x << SE_KEYTABLE_SLOT_SHIFT)
#define SE_KEYTABLE_QUAD_SHIFT 2
#define SE_KEY_TABLE_ACCESS_REG_OFFSET 0x284
#define SE_INT_STATUS_REG_OFFSET 0x010
#define SE_KEYTABLE_DATA0_REG_OFFSET 0x320
#endif #endif