2018-03-26 23:04:16 +00:00
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/*
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2024-01-14 08:20:28 +00:00
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* Copyright (c) 2024 hydrogenium2020-offical
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2018-03-26 23:04:16 +00:00
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* Copyright (c) 2018 naehrwert
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2024-02-11 06:51:13 +00:00
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* Copyright (c) 2020 CTCaer
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2018-03-26 23:04:16 +00:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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2024-02-11 06:51:13 +00:00
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#ifndef _T124_PMC_H_
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#define _T124_PMC_H_
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2018-03-14 23:26:19 +00:00
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#include "types.h"
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2024-01-31 08:40:19 +00:00
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#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4
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2024-02-11 06:51:13 +00:00
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//SDRAM
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#define APBDEV_PMC_VDDP_SEL 0x1CC
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#define APBDEV_PMC_DDR_PWR 0xE8
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#define APBDEV_PMC_NO_IOPOWER 0x44
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#define APBDEV_PMC_REG_SHORT 0x2CC
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#define APBDEV_PMC_DDR_CFG 0x1D0
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#define APBDEV_PMC_POR_DPD_CTRL 0x264
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#define APBDEV_PMC_IO_DPD3_REQ 0x45c
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2024-01-31 08:40:19 +00:00
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enum {
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PMC_XOFS_SHIFT = 1,
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PMC_XOFS_MASK = 0x3f << PMC_XOFS_SHIFT
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2024-02-11 06:51:13 +00:00
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};
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enum {
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PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK = 1 << 0,
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PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK = 1 << 1,
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PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK = 1 << 31,
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};
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enum {
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PMC_DDR_CFG_PKG_MASK = 1 << 0,
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PMC_DDR_CFG_IF_MASK = 1 << 1,
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PMC_DDR_CFG_XM0_RESET_TRI_MASK = 1 << 12,
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PMC_DDR_CFG_XM0_RESET_DPDIO_MASK = 1 << 13,
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};
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enum {
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PMC_DDR_PWR_EMMC_MASK = 1 << 1,
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PMC_DDR_PWR_VAL_MASK = 1 << 0,
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};
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enum {
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PMC_NO_IOPOWER_MEM_MASK = 1 << 7,
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PMC_NO_IOPOWER_MEM_COMP_MASK = 1 << 16,
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};
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#endif
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