94 lines
2.8 KiB
Python
94 lines
2.8 KiB
Python
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# Define constants for the base addresses
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BASE_ADDRESSES = {
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'IROM_BASE': 0x100000,
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'IRAM_BASE': 0x40000000,
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'HOST1X_BASE': 0x50000000,
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'BPMP_CACHE_BASE': 0x50040000,
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'MSELECT_BASE': 0x50060000,
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'DPAUX1_BASE': 0x54040000,
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'TSEC2_BASE': 0x54100000,
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'DISPLAY_A_BASE': 0x54200000,
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'DISPLAY_B_BASE': 0x54240000,
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'DSI_BASE': 0x54300000,
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'VIC_BASE': 0x54340000,
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'NVJPG_BASE': 0x54380000,
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'NVDEC_BASE': 0x54480000,
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'NVENC_BASE': 0x544C0000,
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'TSEC_BASE': 0x54500000,
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'SOR1_BASE': 0x54580000,
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'GPU_BASE': 0x57000000,
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'GPU_USER_BASE': 0x58000000,
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'RES_SEMAPH_BASE': 0x60001000,
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'ARB_SEMAPH_BASE': 0x60002000,
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'ARBPRI_BASE': 0x60003000,
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'ICTLR_BASE': 0x60004000,
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'TMR_BASE': 0x60005000,
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'CLOCK_BASE': 0x60006000,
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'FLOW_CTLR_BASE': 0x60007000,
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'AHBDMA_BASE': 0x60008000,
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'SYSREG_BASE': 0x6000C000,
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'SB_BASE': 0x6000C000 + 0x200,
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'ACTMON_BASE': 0x6000C800,
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'GPIO_BASE': 0x6000D000,
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'EXCP_VEC_BASE': 0x6000F000,
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'IPATCH_BASE': 0x6001DC00,
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'APBDMA_BASE': 0x60020000,
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'VGPIO_BASE': 0x60024000,
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'APB_MISC_BASE': 0x70000000,
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'PINMUX_AUX_BASE': 0x70003000,
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'UART_BASE': 0x70006000,
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'PWM_BASE': 0x7000A000,
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'I2C_BASE': 0x7000C000,
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'RTC_BASE': 0x7000E000,
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'PMC_BASE': 0x7000E400,
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'FUSE_BASE': 0x7000F800,
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'KFUSE_BASE': 0x7000FC00,
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'SE_BASE': 0x70012000,
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'TSENSOR_BASE': 0x70014000,
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'ATOMICS_BASE': 0x70016000,
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'MC_BASE': 0x70019000,
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'EMC_BASE': 0x7001B000,
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'EMC0_BASE': 0x7001E000,
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'EMC1_BASE': 0x7001F000,
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'XUSB_HOST_BASE': 0x70090000,
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'XUSB_PADCTL_BASE': 0x7009F000,
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'XUSB_DEV_BASE': 0x700D0000,
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'SDMMC_BASE': 0x700B0000,
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'SOC_THERM_BASE': 0x700E2000,
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'MIPI_CAL_BASE': 0x700E3000,
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'SYSCTR0_BASE': 0x700F0000,
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'SYSCTR1_BASE': 0x70100000,
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'CL_DVFS_BASE': 0x70110000,
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'APE_BASE': 0x702C0000,
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'AHUB_BASE': 0x702D0000,
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'AXBAR_BASE': 0x702D0800,
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'I2S_BASE': 0x702D1000,
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'ADMA_BASE': 0x702E2000,
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'SE2_BASE': 0x70412000,
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'SE_PKA1_BASE': 0x70420000,
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'TZRAM_BASE': 0x7C010000,
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'TZRAM_SIZE': 0x10000,
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'TZRAM_T210B01_SIZE': 0x3C000,
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'USB_BASE': 0x7D000000,
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'USB_OTG_BASE': 0x7D000000,
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'USB1_BASE': 0x7D004000,
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'EMEM_BASE': 0x80000000,
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}
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APB_MISC_GP_HIDREV = 0x804
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# Function to get MMIO register
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def mmio_reg32(base, offset):
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return base + offset
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# Example usage
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# HOST1X = lambda offset: mmio_reg32(BASE_ADDRESSES['HOST1X_BASE'], offset)
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# BPMP_CACHE_CTRL = lambda offset: mmio_reg32(BASE_ADDRESSES['BPMP_CACHE_BASE'], offset)
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# MSELECT = lambda offset: mmio_reg32(BASE_ADDRESSES['MSELECT_BASE'], offset)
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# DPAUX1 = lambda offset: mmio_reg32(BASE_ADDRESSES['DPAUX1_BASE'], offset)
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# TSEC2 = lambda offset: mmio_reg32(BASE_ADDRESSES['TSEC2_BASE'], offset)
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# # Example access
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# print(hex(HOST1X(0x100))) # Example usage of the HOST1X register
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