70 lines
1.9 KiB
Python
70 lines
1.9 KiB
Python
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#!/usr/bin/env python3
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#
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# Cross Platform and Multi Architecture Advanced Binary Emulation Framework
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#
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from functools import cached_property
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from unicorn import Uc, UC_ARCH_RISCV, UC_MODE_RISCV32
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from capstone import Cs
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from keystone import Ks
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from qiling.arch.arch import QlArch
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from qiling.arch.register import QlRegisterManager
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from qiling.arch import riscv_const
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from qiling.arch.riscv_const import *
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from qiling.const import QL_ARCH, QL_ENDIAN
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from qiling.exception import QlErrorNotImplemented
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class QlArchRISCV(QlArch):
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type = QL_ARCH.RISCV
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bits = 32
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@cached_property
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def uc(self) -> Uc:
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return Uc(UC_ARCH_RISCV, UC_MODE_RISCV32)
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@cached_property
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def regs(self) -> QlRegisterManager:
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regs_map = dict(
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**riscv_const.reg_map,
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**riscv_const.reg_csr_map,
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**riscv_const.reg_float_map,
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)
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pc_reg = 'pc'
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sp_reg = 'sp'
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return QlRegisterManager(self.uc, regs_map, pc_reg, sp_reg)
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@property
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def endian(self) -> QL_ENDIAN:
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return QL_ENDIAN.EL
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@cached_property
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def disassembler(self) -> Cs:
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try:
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from capstone import CS_ARCH_RISCV, CS_MODE_RISCV32, CS_MODE_RISCVC
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except ImportError:
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raise QlErrorNotImplemented("Capstone does not yet support riscv, upgrade to capstone 5.0")
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else:
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return Cs(CS_ARCH_RISCV, CS_MODE_RISCV32 + CS_MODE_RISCVC)
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@cached_property
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def assembler(self) -> Ks:
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raise QlErrorNotImplemented("Keystone does not yet support riscv")
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def enable_float(self):
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self.regs.mstatus = self.regs.mstatus | MSTATUS.FS_DIRTY
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def init_context(self):
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self.regs.pc = 0x08000000
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def unicorn_exception_handler(self, ql, intno):
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if intno == 2:
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ql.log.warning(f'[{hex(self.regs.arch_pc)}] Illegal instruction')
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else:
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raise QlErrorNotImplemented(f'Unhandled interrupt number ({intno})')
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