100 lines
4.0 KiB
C
100 lines
4.0 KiB
C
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#ifndef _T124_RCM_H_
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#define _T124_RCM_H_
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#define JETSON_TK1_VID 0x0955
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#define JETSON_TK1_PID 0x7140
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#define SHIELD_TK1_VID 0x0955
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#define SHIELD_TK1_PID 0x7f40
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#define IROM_BEGIN 0x00100000
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#define IROM_END 0x0010FFFF
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#define IROM_LEN 0x00010000
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#define IRAM_BEGIN 0x40000000
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#define IRAM_END 0x4003FFFF
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#define IRAM_LEN 0x00040000
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#define BOOTROM_DO_BCT_BOOT 0x00100624
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#define BOOTROM_EP1_IN_WRITE_IMM 0x001065C0
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#define BOOTROM_EP1_OUT_READ_IMM 0x00106612
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#define BOOTROM_USB_BUF_1 0x40004000
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#define BOOTROM_USB_BUF_2 0x40008000
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#define BOOTROM_PAYLOAD_ENTRY 0x4000E000
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#define BOOTROM_SMASH_TARGET 0x4000DCD8
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#define BOOTROM_STACK_GAP_LEN 0x30C
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#define BOOTROM_SMASH_LEN (BOOTROM_SMASH_TARGET - BOOTROM_USB_BUF_2) // 0x5CD8
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#define VARS_LEN 0x10
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#define INTERMEZZO_LEN 0x100
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#define INTERMEZZO_REL_ADD ( BOOTROM_PAYLOAD_ENTRY - INTERMEZZO_LEN ) // 0x4000DF00
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#define OFFSET_INTERMEZZO_START 0x0
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#define OFFSET_PAYLOAD_START ( INTERMEZZO_LEN )
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#define OFFSET_MEMCPY_RET_ADD ( BOOTROM_SMASH_LEN - BOOTROM_STACK_GAP_LEN - 0x4 ) // 0x59C8 ( 0x30C Bytes copied from the stack before entry )
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#define OFFSET_PAYLOAD_BEF_LENVAR ( OFFSET_MEMCPY_RET_ADD - 0x4 )
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#define OFFSET_PAYLOAD_AFT_LENVAR ( OFFSET_MEMCPY_RET_ADD - 0x8 )
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#define OFFSET_PAYLOAD_THUMB_MODE ( OFFSET_MEMCPY_RET_ADD - 0xC )
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#define OFFSET_PAYLOAD_CONT ( OFFSET_MEMCPY_RET_ADD + 0x4 )
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#define IRAM_ADD_INTERMEZZO_START ( BOOTROM_PAYLOAD_ENTRY + OFFSET_INTERMEZZO_START )
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#define IRAM_ADD_PAYLOAD_START ( BOOTROM_PAYLOAD_ENTRY + OFFSET_PAYLOAD_START )
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#define IRAM_ADD_PAYLOAD_BEF_LENVAR ( BOOTROM_PAYLOAD_ENTRY + OFFSET_PAYLOAD_BEF_LENVAR )
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#define IRAM_ADD_PAYLOAD_AFT_LENVAR ( BOOTROM_PAYLOAD_ENTRY + OFFSET_PAYLOAD_AFT_LENVAR )
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#define IRAM_ADD_PAYLOAD_THUMB_MODE ( BOOTROM_PAYLOAD_ENTRY + OFFSET_PAYLOAD_THUMB_MODE )
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#define IRAM_ADD_PAYLOAD_CONT ( BOOTROM_PAYLOAD_ENTRY + OFFSET_PAYLOAD_CONT )
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#define RCM_EP1_IN 0x81
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#define RCM_EP1_OUT 0x01
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#define RCM_CHIP_ID_LEN 0x10
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#define RCM_CMD_LEN 0x32274
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#define RCM_CMD_MAX_USEFUL_LEN 0x31000 // Ensures Header + Payload + Padding doesn't complete RCM CMD and buffer 2 is used for getstatus.
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#define RCM_CMD_HEADER_LEN 0x284
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#define RCM_CMD_BUF_INTERMEZZO_START ( RCM_CMD_HEADER_LEN + OFFSET_INTERMEZZO_START )
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#define RCM_CMD_BUF_PAYLOAD_START ( RCM_CMD_HEADER_LEN + OFFSET_PAYLOAD_START )
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#define RCM_CMD_BUF_MEMCPY_RET_ADD ( RCM_CMD_HEADER_LEN + OFFSET_MEMCPY_RET_ADD )
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#define RCM_CMD_BUF_PAYLOAD_BEF_LENVAR ( RCM_CMD_HEADER_LEN + OFFSET_PAYLOAD_BEF_LENVAR )
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#define RCM_CMD_BUF_PAYLOAD_AFT_LENVAR ( RCM_CMD_HEADER_LEN + OFFSET_PAYLOAD_AFT_LENVAR )
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#define RCM_CMD_BUF_PAYLOAD_THUMB_MODE ( RCM_CMD_HEADER_LEN + OFFSET_PAYLOAD_THUMB_MODE )
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#define RCM_CMD_BUF_PAYLOAD_CONT ( RCM_CMD_HEADER_LEN + OFFSET_PAYLOAD_CONT )
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#define MAX_PAYLOAD_BEF_SIZE ( OFFSET_PAYLOAD_THUMB_MODE - OFFSET_PAYLOAD_START ) // 22716 Bytes
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#define MAX_PAYLOAD_AFT_SIZE ( RCM_CMD_MAX_USEFUL_LEN - RCM_CMD_BUF_PAYLOAD_CONT ) // 177072 Bytes
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#define MAX_PAYLOAD_FILE_SIZE ( MAX_PAYLOAD_BEF_SIZE + MAX_PAYLOAD_AFT_SIZE ) // 199788 Bytes
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#define SECURE_BOOT_BASE 0x6000C200
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#define SB_CSR_0 0x0
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#define SB_PIROM_START_0 0x4
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#define SB_PFCFG_0 0x8
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#define JTAG_ON 0x00000080
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#define APB_BASE 0x70000000
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#define APB_MISC_PP_CONFIG_CTL_0 0x24
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#define APB_MISC_PP_CONFIG_CTL_0_JTAG 0x40
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#define APB_MISC_PP_CONFIG_CTL_0_TBE 0x80
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#define FLOW_CTLR_BASE 0x60007000
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#define FLOW_CTLR_HALT_COP_EVENTS_0 0x4
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#define FLOW_CTLR_HALT_COP_FLOW_MODE_WAITEVENT (1 << 30)
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#define FLOW_CTLR_HALT_COP_JTAG (1 << 28)
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#define PMC_BASE 0x7000e400
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#define PMC_CNTRL 0x000
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#define PMC_CNTRL_MAIN_RST (1 << 4)
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#define PMC_SCRATCH0 0x050
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#define PMC_SCRATCH0_MODE_RCM (1 << 1)
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#define FUSE_BASE 0x7000F900
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#define FUSE_LEN 0x300
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#endif
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