118 lines
3.2 KiB
Python
118 lines
3.2 KiB
Python
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#!/usr/bin/env python3
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#
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# Cross Platform and Multi Architecture Advanced Binary Emulation Framework
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#
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from functools import cached_property, lru_cache
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from unicorn import Uc, UC_ARCH_ARM, UC_MODE_ARM, UC_MODE_THUMB, UC_MODE_BIG_ENDIAN
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from capstone import Cs, CS_ARCH_ARM, CS_MODE_ARM, CS_MODE_THUMB, CS_MODE_BIG_ENDIAN
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from keystone import Ks, KS_ARCH_ARM, KS_MODE_ARM, KS_MODE_THUMB, KS_MODE_BIG_ENDIAN
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from qiling import Qiling
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from qiling.arch.arch import QlArch
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from qiling.arch import arm_const
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from qiling.arch.register import QlRegisterManager
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from qiling.const import QL_ARCH, QL_ENDIAN
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class QlArchARM(QlArch):
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type = QL_ARCH.ARM
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bits = 32
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def __init__(self, ql: Qiling, endian: QL_ENDIAN, thumb: bool):
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super().__init__(ql)
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self._init_endian = endian
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self._init_thumb = thumb
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self.arm_get_tls_addr = 0xFFFF0FE0
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@cached_property
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def uc(self) -> Uc:
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mode = UC_MODE_ARM
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if self._init_endian == QL_ENDIAN.EB:
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mode += UC_MODE_BIG_ENDIAN
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if self._init_thumb:
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mode += UC_MODE_THUMB
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return Uc(UC_ARCH_ARM, mode)
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@cached_property
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def regs(self) -> QlRegisterManager:
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regs_map = dict(
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**arm_const.reg_map,
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**arm_const.reg_vfp,
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**arm_const.reg_map_q,
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**arm_const.reg_map_s
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)
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pc_reg = 'pc'
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sp_reg = 'sp'
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return QlRegisterManager(self.uc, regs_map, pc_reg, sp_reg)
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@property
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def is_thumb(self) -> bool:
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return bool(self.regs.cpsr & (1 << 5))
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@property
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def endian(self) -> QL_ENDIAN:
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return QL_ENDIAN.EB if self.regs.cpsr & (1 << 9) else QL_ENDIAN.EL
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@property
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def effective_pc(self) -> int:
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"""Get effective PC value, taking Thumb mode into account.
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"""
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# append 1 to pc if in thumb mode, or 0 otherwise
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return self.regs.pc | int(self.is_thumb)
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@lru_cache(maxsize=4)
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def __cached_disasm(self, mode: int) -> Cs:
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return Cs(CS_ARCH_ARM, mode)
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@property
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def disassembler(self) -> Cs:
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# note: since endianess and thumb mode might change during execution, we cannot
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# cache the disassembler instance directly; rather we pick the appropriate cached
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# instance
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mode = CS_MODE_ARM
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if self.endian == QL_ENDIAN.EB:
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mode += CS_MODE_BIG_ENDIAN
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if self.is_thumb:
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mode += CS_MODE_THUMB
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return self.__cached_disasm(mode)
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@lru_cache(maxsize=4)
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def __cached_asm(self, mode: int) -> Ks:
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return Ks(KS_ARCH_ARM, mode)
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@property
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def assembler(self) -> Ks:
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# note: since endianess and thumb mode might change during execution, we cannot
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# cache the assembler instance directly; rather we pick the appropriate cached
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# instance
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mode = KS_MODE_ARM
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if self.endian == QL_ENDIAN.EB:
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mode += KS_MODE_BIG_ENDIAN
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if self.is_thumb:
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mode += KS_MODE_THUMB
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return self.__cached_asm(mode)
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def enable_vfp(self) -> None:
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# set full access to cp10 and cp11
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self.regs.c1_c0_2 = self.regs.c1_c0_2 | (0b11 << 20) | (0b11 << 22)
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self.regs.fpexc = (1 << 30)
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