3009 lines
77 KiB
Python
3009 lines
77 KiB
Python
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from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM
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# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.py]
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ARM64_SFT_INVALID = 0
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ARM64_SFT_LSL = 1
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ARM64_SFT_MSL = 2
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ARM64_SFT_LSR = 3
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ARM64_SFT_ASR = 4
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ARM64_SFT_ROR = 5
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ARM64_EXT_INVALID = 0
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ARM64_EXT_UXTB = 1
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ARM64_EXT_UXTH = 2
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ARM64_EXT_UXTW = 3
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ARM64_EXT_UXTX = 4
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ARM64_EXT_SXTB = 5
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ARM64_EXT_SXTH = 6
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ARM64_EXT_SXTW = 7
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ARM64_EXT_SXTX = 8
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ARM64_CC_INVALID = 0
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ARM64_CC_EQ = 1
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ARM64_CC_NE = 2
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ARM64_CC_HS = 3
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ARM64_CC_LO = 4
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ARM64_CC_MI = 5
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ARM64_CC_PL = 6
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ARM64_CC_VS = 7
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ARM64_CC_VC = 8
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ARM64_CC_HI = 9
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ARM64_CC_LS = 10
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ARM64_CC_GE = 11
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ARM64_CC_LT = 12
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ARM64_CC_GT = 13
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ARM64_CC_LE = 14
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ARM64_CC_AL = 15
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ARM64_CC_NV = 16
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ARM64_SYSREG_INVALID = 0
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ARM64_SYSREG_ACCDATA_EL1 = 0xC685
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ARM64_SYSREG_ACTLR_EL1 = 0xC081
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ARM64_SYSREG_ACTLR_EL2 = 0xE081
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ARM64_SYSREG_ACTLR_EL3 = 0xF081
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ARM64_SYSREG_AFSR0_EL1 = 0xC288
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ARM64_SYSREG_AFSR0_EL12 = 0xEA88
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ARM64_SYSREG_AFSR0_EL2 = 0xE288
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ARM64_SYSREG_AFSR0_EL3 = 0xF288
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ARM64_SYSREG_AFSR1_EL1 = 0xC289
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ARM64_SYSREG_AFSR1_EL12 = 0xEA89
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ARM64_SYSREG_AFSR1_EL2 = 0xE289
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ARM64_SYSREG_AFSR1_EL3 = 0xF289
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ARM64_SYSREG_AIDR_EL1 = 0xC807
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ARM64_SYSREG_AMAIR_EL1 = 0xC518
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ARM64_SYSREG_AMAIR_EL12 = 0xED18
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ARM64_SYSREG_AMAIR_EL2 = 0xE518
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ARM64_SYSREG_AMAIR_EL3 = 0xF518
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ARM64_SYSREG_AMCFGR_EL0 = 0xDE91
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ARM64_SYSREG_AMCGCR_EL0 = 0xDE92
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ARM64_SYSREG_AMCNTENCLR0_EL0 = 0xDE94
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ARM64_SYSREG_AMCNTENCLR1_EL0 = 0xDE98
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ARM64_SYSREG_AMCNTENSET0_EL0 = 0xDE95
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ARM64_SYSREG_AMCNTENSET1_EL0 = 0xDE99
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ARM64_SYSREG_AMCR_EL0 = 0xDE90
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ARM64_SYSREG_AMEVCNTR00_EL0 = 0xDEA0
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ARM64_SYSREG_AMEVCNTR01_EL0 = 0xDEA1
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ARM64_SYSREG_AMEVCNTR02_EL0 = 0xDEA2
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ARM64_SYSREG_AMEVCNTR03_EL0 = 0xDEA3
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ARM64_SYSREG_AMEVCNTR10_EL0 = 0xDEE0
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ARM64_SYSREG_AMEVCNTR110_EL0 = 0xDEEA
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ARM64_SYSREG_AMEVCNTR111_EL0 = 0xDEEB
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ARM64_SYSREG_AMEVCNTR112_EL0 = 0xDEEC
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ARM64_SYSREG_AMEVCNTR113_EL0 = 0xDEED
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ARM64_SYSREG_AMEVCNTR114_EL0 = 0xDEEE
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ARM64_SYSREG_AMEVCNTR115_EL0 = 0xDEEF
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ARM64_SYSREG_AMEVCNTR11_EL0 = 0xDEE1
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ARM64_SYSREG_AMEVCNTR12_EL0 = 0xDEE2
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ARM64_SYSREG_AMEVCNTR13_EL0 = 0xDEE3
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ARM64_SYSREG_AMEVCNTR14_EL0 = 0xDEE4
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ARM64_SYSREG_AMEVCNTR15_EL0 = 0xDEE5
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ARM64_SYSREG_AMEVCNTR16_EL0 = 0xDEE6
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ARM64_SYSREG_AMEVCNTR17_EL0 = 0xDEE7
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ARM64_SYSREG_AMEVCNTR18_EL0 = 0xDEE8
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ARM64_SYSREG_AMEVCNTR19_EL0 = 0xDEE9
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ARM64_SYSREG_AMEVCNTVOFF00_EL2 = 0xE6C0
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ARM64_SYSREG_AMEVCNTVOFF010_EL2 = 0xE6CA
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ARM64_SYSREG_AMEVCNTVOFF011_EL2 = 0xE6CB
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ARM64_SYSREG_AMEVCNTVOFF012_EL2 = 0xE6CC
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ARM64_SYSREG_AMEVCNTVOFF013_EL2 = 0xE6CD
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ARM64_SYSREG_AMEVCNTVOFF014_EL2 = 0xE6CE
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ARM64_SYSREG_AMEVCNTVOFF015_EL2 = 0xE6CF
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ARM64_SYSREG_AMEVCNTVOFF01_EL2 = 0xE6C1
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ARM64_SYSREG_AMEVCNTVOFF02_EL2 = 0xE6C2
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ARM64_SYSREG_AMEVCNTVOFF03_EL2 = 0xE6C3
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ARM64_SYSREG_AMEVCNTVOFF04_EL2 = 0xE6C4
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ARM64_SYSREG_AMEVCNTVOFF05_EL2 = 0xE6C5
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ARM64_SYSREG_AMEVCNTVOFF06_EL2 = 0xE6C6
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ARM64_SYSREG_AMEVCNTVOFF07_EL2 = 0xE6C7
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ARM64_SYSREG_AMEVCNTVOFF08_EL2 = 0xE6C8
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ARM64_SYSREG_AMEVCNTVOFF09_EL2 = 0xE6C9
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ARM64_SYSREG_AMEVCNTVOFF10_EL2 = 0xE6D0
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ARM64_SYSREG_AMEVCNTVOFF110_EL2 = 0xE6DA
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ARM64_SYSREG_AMEVCNTVOFF111_EL2 = 0xE6DB
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ARM64_SYSREG_AMEVCNTVOFF112_EL2 = 0xE6DC
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ARM64_SYSREG_AMEVCNTVOFF113_EL2 = 0xE6DD
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ARM64_SYSREG_AMEVCNTVOFF114_EL2 = 0xE6DE
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ARM64_SYSREG_AMEVCNTVOFF115_EL2 = 0xE6DF
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ARM64_SYSREG_AMEVCNTVOFF11_EL2 = 0xE6D1
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ARM64_SYSREG_AMEVCNTVOFF12_EL2 = 0xE6D2
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ARM64_SYSREG_AMEVCNTVOFF13_EL2 = 0xE6D3
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ARM64_SYSREG_AMEVCNTVOFF14_EL2 = 0xE6D4
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ARM64_SYSREG_AMEVCNTVOFF15_EL2 = 0xE6D5
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ARM64_SYSREG_AMEVCNTVOFF16_EL2 = 0xE6D6
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ARM64_SYSREG_AMEVCNTVOFF17_EL2 = 0xE6D7
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ARM64_SYSREG_AMEVCNTVOFF18_EL2 = 0xE6D8
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ARM64_SYSREG_AMEVCNTVOFF19_EL2 = 0xE6D9
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ARM64_SYSREG_AMEVTYPER00_EL0 = 0xDEB0
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ARM64_SYSREG_AMEVTYPER01_EL0 = 0xDEB1
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ARM64_SYSREG_AMEVTYPER02_EL0 = 0xDEB2
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ARM64_SYSREG_AMEVTYPER03_EL0 = 0xDEB3
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ARM64_SYSREG_AMEVTYPER10_EL0 = 0xDEF0
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ARM64_SYSREG_AMEVTYPER110_EL0 = 0xDEFA
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ARM64_SYSREG_AMEVTYPER111_EL0 = 0xDEFB
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ARM64_SYSREG_AMEVTYPER112_EL0 = 0xDEFC
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ARM64_SYSREG_AMEVTYPER113_EL0 = 0xDEFD
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ARM64_SYSREG_AMEVTYPER114_EL0 = 0xDEFE
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ARM64_SYSREG_AMEVTYPER115_EL0 = 0xDEFF
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ARM64_SYSREG_AMEVTYPER11_EL0 = 0xDEF1
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ARM64_SYSREG_AMEVTYPER12_EL0 = 0xDEF2
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ARM64_SYSREG_AMEVTYPER13_EL0 = 0xDEF3
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ARM64_SYSREG_AMEVTYPER14_EL0 = 0xDEF4
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ARM64_SYSREG_AMEVTYPER15_EL0 = 0xDEF5
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ARM64_SYSREG_AMEVTYPER16_EL0 = 0xDEF6
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ARM64_SYSREG_AMEVTYPER17_EL0 = 0xDEF7
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ARM64_SYSREG_AMEVTYPER18_EL0 = 0xDEF8
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ARM64_SYSREG_AMEVTYPER19_EL0 = 0xDEF9
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ARM64_SYSREG_AMUSERENR_EL0 = 0xDE93
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ARM64_SYSREG_APDAKEYHI_EL1 = 0xC111
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ARM64_SYSREG_APDAKEYLO_EL1 = 0xC110
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ARM64_SYSREG_APDBKEYHI_EL1 = 0xC113
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ARM64_SYSREG_APDBKEYLO_EL1 = 0xC112
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ARM64_SYSREG_APGAKEYHI_EL1 = 0xC119
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ARM64_SYSREG_APGAKEYLO_EL1 = 0xC118
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ARM64_SYSREG_APIAKEYHI_EL1 = 0xC109
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ARM64_SYSREG_APIAKEYLO_EL1 = 0xC108
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ARM64_SYSREG_APIBKEYHI_EL1 = 0xC10B
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ARM64_SYSREG_APIBKEYLO_EL1 = 0xC10A
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ARM64_SYSREG_BRBCR_EL1 = 0x8C80
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ARM64_SYSREG_BRBCR_EL12 = 0xAC80
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ARM64_SYSREG_BRBCR_EL2 = 0xA480
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ARM64_SYSREG_BRBFCR_EL1 = 0x8C81
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ARM64_SYSREG_BRBIDR0_EL1 = 0x8C90
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ARM64_SYSREG_BRBINF0_EL1 = 0x8C00
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ARM64_SYSREG_BRBINF10_EL1 = 0x8C50
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ARM64_SYSREG_BRBINF11_EL1 = 0x8C58
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ARM64_SYSREG_BRBINF12_EL1 = 0x8C60
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ARM64_SYSREG_BRBINF13_EL1 = 0x8C68
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ARM64_SYSREG_BRBINF14_EL1 = 0x8C70
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ARM64_SYSREG_BRBINF15_EL1 = 0x8C78
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ARM64_SYSREG_BRBINF16_EL1 = 0x8C04
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ARM64_SYSREG_BRBINF17_EL1 = 0x8C0C
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ARM64_SYSREG_BRBINF18_EL1 = 0x8C14
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ARM64_SYSREG_BRBINF19_EL1 = 0x8C1C
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ARM64_SYSREG_BRBINF1_EL1 = 0x8C08
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ARM64_SYSREG_BRBINF20_EL1 = 0x8C24
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ARM64_SYSREG_BRBINF21_EL1 = 0x8C2C
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ARM64_SYSREG_BRBINF22_EL1 = 0x8C34
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ARM64_SYSREG_BRBINF23_EL1 = 0x8C3C
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ARM64_SYSREG_BRBINF24_EL1 = 0x8C44
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ARM64_SYSREG_BRBINF25_EL1 = 0x8C4C
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ARM64_SYSREG_BRBINF26_EL1 = 0x8C54
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ARM64_SYSREG_BRBINF27_EL1 = 0x8C5C
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ARM64_SYSREG_BRBINF28_EL1 = 0x8C64
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ARM64_SYSREG_BRBINF29_EL1 = 0x8C6C
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ARM64_SYSREG_BRBINF2_EL1 = 0x8C10
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ARM64_SYSREG_BRBINF30_EL1 = 0x8C74
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ARM64_SYSREG_BRBINF31_EL1 = 0x8C7C
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ARM64_SYSREG_BRBINF3_EL1 = 0x8C18
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ARM64_SYSREG_BRBINF4_EL1 = 0x8C20
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ARM64_SYSREG_BRBINF5_EL1 = 0x8C28
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ARM64_SYSREG_BRBINF6_EL1 = 0x8C30
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ARM64_SYSREG_BRBINF7_EL1 = 0x8C38
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ARM64_SYSREG_BRBINF8_EL1 = 0x8C40
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ARM64_SYSREG_BRBINF9_EL1 = 0x8C48
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ARM64_SYSREG_BRBINFINJ_EL1 = 0x8C88
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ARM64_SYSREG_BRBSRC0_EL1 = 0x8C01
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ARM64_SYSREG_BRBSRC10_EL1 = 0x8C51
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ARM64_SYSREG_BRBSRC11_EL1 = 0x8C59
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ARM64_SYSREG_BRBSRC12_EL1 = 0x8C61
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ARM64_SYSREG_BRBSRC13_EL1 = 0x8C69
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ARM64_SYSREG_BRBSRC14_EL1 = 0x8C71
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ARM64_SYSREG_BRBSRC15_EL1 = 0x8C79
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ARM64_SYSREG_BRBSRC16_EL1 = 0x8C05
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ARM64_SYSREG_BRBSRC17_EL1 = 0x8C0D
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ARM64_SYSREG_BRBSRC18_EL1 = 0x8C15
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ARM64_SYSREG_BRBSRC19_EL1 = 0x8C1D
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ARM64_SYSREG_BRBSRC1_EL1 = 0x8C09
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ARM64_SYSREG_BRBSRC20_EL1 = 0x8C25
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ARM64_SYSREG_BRBSRC21_EL1 = 0x8C2D
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ARM64_SYSREG_BRBSRC22_EL1 = 0x8C35
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ARM64_SYSREG_BRBSRC23_EL1 = 0x8C3D
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ARM64_SYSREG_BRBSRC24_EL1 = 0x8C45
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ARM64_SYSREG_BRBSRC25_EL1 = 0x8C4D
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ARM64_SYSREG_BRBSRC26_EL1 = 0x8C55
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ARM64_SYSREG_BRBSRC27_EL1 = 0x8C5D
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ARM64_SYSREG_BRBSRC28_EL1 = 0x8C65
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ARM64_SYSREG_BRBSRC29_EL1 = 0x8C6D
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ARM64_SYSREG_BRBSRC2_EL1 = 0x8C11
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ARM64_SYSREG_BRBSRC30_EL1 = 0x8C75
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ARM64_SYSREG_BRBSRC31_EL1 = 0x8C7D
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ARM64_SYSREG_BRBSRC3_EL1 = 0x8C19
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ARM64_SYSREG_BRBSRC4_EL1 = 0x8C21
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ARM64_SYSREG_BRBSRC5_EL1 = 0x8C29
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ARM64_SYSREG_BRBSRC6_EL1 = 0x8C31
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ARM64_SYSREG_BRBSRC7_EL1 = 0x8C39
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ARM64_SYSREG_BRBSRC8_EL1 = 0x8C41
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ARM64_SYSREG_BRBSRC9_EL1 = 0x8C49
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ARM64_SYSREG_BRBSRCINJ_EL1 = 0x8C89
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ARM64_SYSREG_BRBTGT0_EL1 = 0x8C02
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ARM64_SYSREG_BRBTGT10_EL1 = 0x8C52
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ARM64_SYSREG_BRBTGT11_EL1 = 0x8C5A
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ARM64_SYSREG_BRBTGT12_EL1 = 0x8C62
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ARM64_SYSREG_BRBTGT13_EL1 = 0x8C6A
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ARM64_SYSREG_BRBTGT14_EL1 = 0x8C72
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ARM64_SYSREG_BRBTGT15_EL1 = 0x8C7A
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ARM64_SYSREG_BRBTGT16_EL1 = 0x8C06
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ARM64_SYSREG_BRBTGT17_EL1 = 0x8C0E
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ARM64_SYSREG_BRBTGT18_EL1 = 0x8C16
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ARM64_SYSREG_BRBTGT19_EL1 = 0x8C1E
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ARM64_SYSREG_BRBTGT1_EL1 = 0x8C0A
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ARM64_SYSREG_BRBTGT20_EL1 = 0x8C26
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ARM64_SYSREG_BRBTGT21_EL1 = 0x8C2E
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ARM64_SYSREG_BRBTGT22_EL1 = 0x8C36
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ARM64_SYSREG_BRBTGT23_EL1 = 0x8C3E
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ARM64_SYSREG_BRBTGT24_EL1 = 0x8C46
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ARM64_SYSREG_BRBTGT25_EL1 = 0x8C4E
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ARM64_SYSREG_BRBTGT26_EL1 = 0x8C56
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ARM64_SYSREG_BRBTGT27_EL1 = 0x8C5E
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ARM64_SYSREG_BRBTGT28_EL1 = 0x8C66
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ARM64_SYSREG_BRBTGT29_EL1 = 0x8C6E
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ARM64_SYSREG_BRBTGT2_EL1 = 0x8C12
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ARM64_SYSREG_BRBTGT30_EL1 = 0x8C76
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ARM64_SYSREG_BRBTGT31_EL1 = 0x8C7E
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ARM64_SYSREG_BRBTGT3_EL1 = 0x8C1A
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ARM64_SYSREG_BRBTGT4_EL1 = 0x8C22
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ARM64_SYSREG_BRBTGT5_EL1 = 0x8C2A
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ARM64_SYSREG_BRBTGT6_EL1 = 0x8C32
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ARM64_SYSREG_BRBTGT7_EL1 = 0x8C3A
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ARM64_SYSREG_BRBTGT8_EL1 = 0x8C42
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ARM64_SYSREG_BRBTGT9_EL1 = 0x8C4A
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ARM64_SYSREG_BRBTGTINJ_EL1 = 0x8C8A
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ARM64_SYSREG_BRBTS_EL1 = 0x8C82
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ARM64_SYSREG_CCSIDR2_EL1 = 0xC802
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ARM64_SYSREG_CCSIDR_EL1 = 0xC800
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ARM64_SYSREG_CLIDR_EL1 = 0xC801
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ARM64_SYSREG_CNTFRQ_EL0 = 0xDF00
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ARM64_SYSREG_CNTHCTL_EL2 = 0xE708
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ARM64_SYSREG_CNTHPS_CTL_EL2 = 0xE729
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ARM64_SYSREG_CNTHPS_CVAL_EL2 = 0xE72A
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ARM64_SYSREG_CNTHPS_TVAL_EL2 = 0xE728
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|
|
ARM64_SYSREG_CNTHP_CTL_EL2 = 0xE711
|
||
|
|
ARM64_SYSREG_CNTHP_CVAL_EL2 = 0xE712
|
||
|
|
ARM64_SYSREG_CNTHP_TVAL_EL2 = 0xE710
|
||
|
|
ARM64_SYSREG_CNTHVS_CTL_EL2 = 0xE721
|
||
|
|
ARM64_SYSREG_CNTHVS_CVAL_EL2 = 0xE722
|
||
|
|
ARM64_SYSREG_CNTHVS_TVAL_EL2 = 0xE720
|
||
|
|
ARM64_SYSREG_CNTHV_CTL_EL2 = 0xE719
|
||
|
|
ARM64_SYSREG_CNTHV_CVAL_EL2 = 0xE71A
|
||
|
|
ARM64_SYSREG_CNTHV_TVAL_EL2 = 0xE718
|
||
|
|
ARM64_SYSREG_CNTISCALE_EL2 = 0xE705
|
||
|
|
ARM64_SYSREG_CNTKCTL_EL1 = 0xC708
|
||
|
|
ARM64_SYSREG_CNTKCTL_EL12 = 0xEF08
|
||
|
|
ARM64_SYSREG_CNTPCTSS_EL0 = 0xDF05
|
||
|
|
ARM64_SYSREG_CNTPCT_EL0 = 0xDF01
|
||
|
|
ARM64_SYSREG_CNTPOFF_EL2 = 0xE706
|
||
|
|
ARM64_SYSREG_CNTPS_CTL_EL1 = 0xFF11
|
||
|
|
ARM64_SYSREG_CNTPS_CVAL_EL1 = 0xFF12
|
||
|
|
ARM64_SYSREG_CNTPS_TVAL_EL1 = 0xFF10
|
||
|
|
ARM64_SYSREG_CNTP_CTL_EL0 = 0xDF11
|
||
|
|
ARM64_SYSREG_CNTP_CTL_EL02 = 0xEF11
|
||
|
|
ARM64_SYSREG_CNTP_CVAL_EL0 = 0xDF12
|
||
|
|
ARM64_SYSREG_CNTP_CVAL_EL02 = 0xEF12
|
||
|
|
ARM64_SYSREG_CNTP_TVAL_EL0 = 0xDF10
|
||
|
|
ARM64_SYSREG_CNTP_TVAL_EL02 = 0xEF10
|
||
|
|
ARM64_SYSREG_CNTSCALE_EL2 = 0xE704
|
||
|
|
ARM64_SYSREG_CNTVCTSS_EL0 = 0xDF06
|
||
|
|
ARM64_SYSREG_CNTVCT_EL0 = 0xDF02
|
||
|
|
ARM64_SYSREG_CNTVFRQ_EL2 = 0xE707
|
||
|
|
ARM64_SYSREG_CNTVOFF_EL2 = 0xE703
|
||
|
|
ARM64_SYSREG_CNTV_CTL_EL0 = 0xDF19
|
||
|
|
ARM64_SYSREG_CNTV_CTL_EL02 = 0xEF19
|
||
|
|
ARM64_SYSREG_CNTV_CVAL_EL0 = 0xDF1A
|
||
|
|
ARM64_SYSREG_CNTV_CVAL_EL02 = 0xEF1A
|
||
|
|
ARM64_SYSREG_CNTV_TVAL_EL0 = 0xDF18
|
||
|
|
ARM64_SYSREG_CNTV_TVAL_EL02 = 0xEF18
|
||
|
|
ARM64_SYSREG_CONTEXTIDR_EL1 = 0xC681
|
||
|
|
ARM64_SYSREG_CONTEXTIDR_EL12 = 0xEE81
|
||
|
|
ARM64_SYSREG_CONTEXTIDR_EL2 = 0xE681
|
||
|
|
ARM64_SYSREG_CPACR_EL1 = 0xC082
|
||
|
|
ARM64_SYSREG_CPACR_EL12 = 0xE882
|
||
|
|
ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 0xFF90
|
||
|
|
ARM64_SYSREG_CPTR_EL2 = 0xE08A
|
||
|
|
ARM64_SYSREG_CPTR_EL3 = 0xF08A
|
||
|
|
ARM64_SYSREG_CSSELR_EL1 = 0xD000
|
||
|
|
ARM64_SYSREG_CTR_EL0 = 0xD801
|
||
|
|
ARM64_SYSREG_CURRENTEL = 0xC212
|
||
|
|
ARM64_SYSREG_DACR32_EL2 = 0xE180
|
||
|
|
ARM64_SYSREG_DAIF = 0xDA11
|
||
|
|
ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83F6
|
||
|
|
ARM64_SYSREG_DBGBCR0_EL1 = 0x8005
|
||
|
|
ARM64_SYSREG_DBGBCR10_EL1 = 0x8055
|
||
|
|
ARM64_SYSREG_DBGBCR11_EL1 = 0x805D
|
||
|
|
ARM64_SYSREG_DBGBCR12_EL1 = 0x8065
|
||
|
|
ARM64_SYSREG_DBGBCR13_EL1 = 0x806D
|
||
|
|
ARM64_SYSREG_DBGBCR14_EL1 = 0x8075
|
||
|
|
ARM64_SYSREG_DBGBCR15_EL1 = 0x807D
|
||
|
|
ARM64_SYSREG_DBGBCR1_EL1 = 0x800D
|
||
|
|
ARM64_SYSREG_DBGBCR2_EL1 = 0x8015
|
||
|
|
ARM64_SYSREG_DBGBCR3_EL1 = 0x801D
|
||
|
|
ARM64_SYSREG_DBGBCR4_EL1 = 0x8025
|
||
|
|
ARM64_SYSREG_DBGBCR5_EL1 = 0x802D
|
||
|
|
ARM64_SYSREG_DBGBCR6_EL1 = 0x8035
|
||
|
|
ARM64_SYSREG_DBGBCR7_EL1 = 0x803D
|
||
|
|
ARM64_SYSREG_DBGBCR8_EL1 = 0x8045
|
||
|
|
ARM64_SYSREG_DBGBCR9_EL1 = 0x804D
|
||
|
|
ARM64_SYSREG_DBGBVR0_EL1 = 0x8004
|
||
|
|
ARM64_SYSREG_DBGBVR10_EL1 = 0x8054
|
||
|
|
ARM64_SYSREG_DBGBVR11_EL1 = 0x805C
|
||
|
|
ARM64_SYSREG_DBGBVR12_EL1 = 0x8064
|
||
|
|
ARM64_SYSREG_DBGBVR13_EL1 = 0x806C
|
||
|
|
ARM64_SYSREG_DBGBVR14_EL1 = 0x8074
|
||
|
|
ARM64_SYSREG_DBGBVR15_EL1 = 0x807C
|
||
|
|
ARM64_SYSREG_DBGBVR1_EL1 = 0x800C
|
||
|
|
ARM64_SYSREG_DBGBVR2_EL1 = 0x8014
|
||
|
|
ARM64_SYSREG_DBGBVR3_EL1 = 0x801C
|
||
|
|
ARM64_SYSREG_DBGBVR4_EL1 = 0x8024
|
||
|
|
ARM64_SYSREG_DBGBVR5_EL1 = 0x802C
|
||
|
|
ARM64_SYSREG_DBGBVR6_EL1 = 0x8034
|
||
|
|
ARM64_SYSREG_DBGBVR7_EL1 = 0x803C
|
||
|
|
ARM64_SYSREG_DBGBVR8_EL1 = 0x8044
|
||
|
|
ARM64_SYSREG_DBGBVR9_EL1 = 0x804C
|
||
|
|
ARM64_SYSREG_DBGCLAIMCLR_EL1 = 0x83CE
|
||
|
|
ARM64_SYSREG_DBGCLAIMSET_EL1 = 0x83C6
|
||
|
|
ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828
|
||
|
|
ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828
|
||
|
|
ARM64_SYSREG_DBGDTR_EL0 = 0x9820
|
||
|
|
ARM64_SYSREG_DBGPRCR_EL1 = 0x80A4
|
||
|
|
ARM64_SYSREG_DBGVCR32_EL2 = 0xA038
|
||
|
|
ARM64_SYSREG_DBGWCR0_EL1 = 0x8007
|
||
|
|
ARM64_SYSREG_DBGWCR10_EL1 = 0x8057
|
||
|
|
ARM64_SYSREG_DBGWCR11_EL1 = 0x805F
|
||
|
|
ARM64_SYSREG_DBGWCR12_EL1 = 0x8067
|
||
|
|
ARM64_SYSREG_DBGWCR13_EL1 = 0x806F
|
||
|
|
ARM64_SYSREG_DBGWCR14_EL1 = 0x8077
|
||
|
|
ARM64_SYSREG_DBGWCR15_EL1 = 0x807F
|
||
|
|
ARM64_SYSREG_DBGWCR1_EL1 = 0x800F
|
||
|
|
ARM64_SYSREG_DBGWCR2_EL1 = 0x8017
|
||
|
|
ARM64_SYSREG_DBGWCR3_EL1 = 0x801F
|
||
|
|
ARM64_SYSREG_DBGWCR4_EL1 = 0x8027
|
||
|
|
ARM64_SYSREG_DBGWCR5_EL1 = 0x802F
|
||
|
|
ARM64_SYSREG_DBGWCR6_EL1 = 0x8037
|
||
|
|
ARM64_SYSREG_DBGWCR7_EL1 = 0x803F
|
||
|
|
ARM64_SYSREG_DBGWCR8_EL1 = 0x8047
|
||
|
|
ARM64_SYSREG_DBGWCR9_EL1 = 0x804F
|
||
|
|
ARM64_SYSREG_DBGWVR0_EL1 = 0x8006
|
||
|
|
ARM64_SYSREG_DBGWVR10_EL1 = 0x8056
|
||
|
|
ARM64_SYSREG_DBGWVR11_EL1 = 0x805E
|
||
|
|
ARM64_SYSREG_DBGWVR12_EL1 = 0x8066
|
||
|
|
ARM64_SYSREG_DBGWVR13_EL1 = 0x806E
|
||
|
|
ARM64_SYSREG_DBGWVR14_EL1 = 0x8076
|
||
|
|
ARM64_SYSREG_DBGWVR15_EL1 = 0x807E
|
||
|
|
ARM64_SYSREG_DBGWVR1_EL1 = 0x800E
|
||
|
|
ARM64_SYSREG_DBGWVR2_EL1 = 0x8016
|
||
|
|
ARM64_SYSREG_DBGWVR3_EL1 = 0x801E
|
||
|
|
ARM64_SYSREG_DBGWVR4_EL1 = 0x8026
|
||
|
|
ARM64_SYSREG_DBGWVR5_EL1 = 0x802E
|
||
|
|
ARM64_SYSREG_DBGWVR6_EL1 = 0x8036
|
||
|
|
ARM64_SYSREG_DBGWVR7_EL1 = 0x803E
|
||
|
|
ARM64_SYSREG_DBGWVR8_EL1 = 0x8046
|
||
|
|
ARM64_SYSREG_DBGWVR9_EL1 = 0x804E
|
||
|
|
ARM64_SYSREG_DCZID_EL0 = 0xD807
|
||
|
|
ARM64_SYSREG_DISR_EL1 = 0xC609
|
||
|
|
ARM64_SYSREG_DIT = 0xDA15
|
||
|
|
ARM64_SYSREG_DLR_EL0 = 0xDA29
|
||
|
|
ARM64_SYSREG_DSPSR_EL0 = 0xDA28
|
||
|
|
ARM64_SYSREG_ELR_EL1 = 0xC201
|
||
|
|
ARM64_SYSREG_ELR_EL12 = 0xEA01
|
||
|
|
ARM64_SYSREG_ELR_EL2 = 0xE201
|
||
|
|
ARM64_SYSREG_ELR_EL3 = 0xF201
|
||
|
|
ARM64_SYSREG_ERRIDR_EL1 = 0xC298
|
||
|
|
ARM64_SYSREG_ERRSELR_EL1 = 0xC299
|
||
|
|
ARM64_SYSREG_ERXADDR_EL1 = 0xC2A3
|
||
|
|
ARM64_SYSREG_ERXCTLR_EL1 = 0xC2A1
|
||
|
|
ARM64_SYSREG_ERXFR_EL1 = 0xC2A0
|
||
|
|
ARM64_SYSREG_ERXMISC0_EL1 = 0xC2A8
|
||
|
|
ARM64_SYSREG_ERXMISC1_EL1 = 0xC2A9
|
||
|
|
ARM64_SYSREG_ERXMISC2_EL1 = 0xC2AA
|
||
|
|
ARM64_SYSREG_ERXMISC3_EL1 = 0xC2AB
|
||
|
|
ARM64_SYSREG_ERXPFGCDN_EL1 = 0xC2A6
|
||
|
|
ARM64_SYSREG_ERXPFGCTL_EL1 = 0xC2A5
|
||
|
|
ARM64_SYSREG_ERXPFGF_EL1 = 0xC2A4
|
||
|
|
ARM64_SYSREG_ERXSTATUS_EL1 = 0xC2A2
|
||
|
|
ARM64_SYSREG_ESR_EL1 = 0xC290
|
||
|
|
ARM64_SYSREG_ESR_EL12 = 0xEA90
|
||
|
|
ARM64_SYSREG_ESR_EL2 = 0xE290
|
||
|
|
ARM64_SYSREG_ESR_EL3 = 0xF290
|
||
|
|
ARM64_SYSREG_FAR_EL1 = 0xC300
|
||
|
|
ARM64_SYSREG_FAR_EL12 = 0xEB00
|
||
|
|
ARM64_SYSREG_FAR_EL2 = 0xE300
|
||
|
|
ARM64_SYSREG_FAR_EL3 = 0xF300
|
||
|
|
ARM64_SYSREG_FPCR = 0xDA20
|
||
|
|
ARM64_SYSREG_FPEXC32_EL2 = 0xE298
|
||
|
|
ARM64_SYSREG_FPSR = 0xDA21
|
||
|
|
ARM64_SYSREG_GCR_EL1 = 0xC086
|
||
|
|
ARM64_SYSREG_GMID_EL1 = 0xC804
|
||
|
|
ARM64_SYSREG_GPCCR_EL3 = 0xF10E
|
||
|
|
ARM64_SYSREG_GPTBR_EL3 = 0xF10C
|
||
|
|
ARM64_SYSREG_HACR_EL2 = 0xE08F
|
||
|
|
ARM64_SYSREG_HCRX_EL2 = 0xE092
|
||
|
|
ARM64_SYSREG_HCR_EL2 = 0xE088
|
||
|
|
ARM64_SYSREG_HDFGRTR_EL2 = 0xE18C
|
||
|
|
ARM64_SYSREG_HDFGWTR_EL2 = 0xE18D
|
||
|
|
ARM64_SYSREG_HFGITR_EL2 = 0xE08E
|
||
|
|
ARM64_SYSREG_HFGRTR_EL2 = 0xE08C
|
||
|
|
ARM64_SYSREG_HFGWTR_EL2 = 0xE08D
|
||
|
|
ARM64_SYSREG_HPFAR_EL2 = 0xE304
|
||
|
|
ARM64_SYSREG_HSTR_EL2 = 0xE08B
|
||
|
|
ARM64_SYSREG_ICC_AP0R0_EL1 = 0xC644
|
||
|
|
ARM64_SYSREG_ICC_AP0R1_EL1 = 0xC645
|
||
|
|
ARM64_SYSREG_ICC_AP0R2_EL1 = 0xC646
|
||
|
|
ARM64_SYSREG_ICC_AP0R3_EL1 = 0xC647
|
||
|
|
ARM64_SYSREG_ICC_AP1R0_EL1 = 0xC648
|
||
|
|
ARM64_SYSREG_ICC_AP1R1_EL1 = 0xC649
|
||
|
|
ARM64_SYSREG_ICC_AP1R2_EL1 = 0xC64A
|
||
|
|
ARM64_SYSREG_ICC_AP1R3_EL1 = 0xC64B
|
||
|
|
ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xC65E
|
||
|
|
ARM64_SYSREG_ICC_BPR0_EL1 = 0xC643
|
||
|
|
ARM64_SYSREG_ICC_BPR1_EL1 = 0xC663
|
||
|
|
ARM64_SYSREG_ICC_CTLR_EL1 = 0xC664
|
||
|
|
ARM64_SYSREG_ICC_CTLR_EL3 = 0xF664
|
||
|
|
ARM64_SYSREG_ICC_DIR_EL1 = 0xC659
|
||
|
|
ARM64_SYSREG_ICC_EOIR0_EL1 = 0xC641
|
||
|
|
ARM64_SYSREG_ICC_EOIR1_EL1 = 0xC661
|
||
|
|
ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xC642
|
||
|
|
ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xC662
|
||
|
|
ARM64_SYSREG_ICC_IAR0_EL1 = 0xC640
|
||
|
|
ARM64_SYSREG_ICC_IAR1_EL1 = 0xC660
|
||
|
|
ARM64_SYSREG_ICC_IGRPEN0_EL1 = 0xC666
|
||
|
|
ARM64_SYSREG_ICC_IGRPEN1_EL1 = 0xC667
|
||
|
|
ARM64_SYSREG_ICC_IGRPEN1_EL3 = 0xF667
|
||
|
|
ARM64_SYSREG_ICC_PMR_EL1 = 0xC230
|
||
|
|
ARM64_SYSREG_ICC_RPR_EL1 = 0xC65B
|
||
|
|
ARM64_SYSREG_ICC_SGI0R_EL1 = 0xC65F
|
||
|
|
ARM64_SYSREG_ICC_SGI1R_EL1 = 0xC65D
|
||
|
|
ARM64_SYSREG_ICC_SRE_EL1 = 0xC665
|
||
|
|
ARM64_SYSREG_ICC_SRE_EL2 = 0xE64D
|
||
|
|
ARM64_SYSREG_ICC_SRE_EL3 = 0xF665
|
||
|
|
ARM64_SYSREG_ICH_AP0R0_EL2 = 0xE640
|
||
|
|
ARM64_SYSREG_ICH_AP0R1_EL2 = 0xE641
|
||
|
|
ARM64_SYSREG_ICH_AP0R2_EL2 = 0xE642
|
||
|
|
ARM64_SYSREG_ICH_AP0R3_EL2 = 0xE643
|
||
|
|
ARM64_SYSREG_ICH_AP1R0_EL2 = 0xE648
|
||
|
|
ARM64_SYSREG_ICH_AP1R1_EL2 = 0xE649
|
||
|
|
ARM64_SYSREG_ICH_AP1R2_EL2 = 0xE64A
|
||
|
|
ARM64_SYSREG_ICH_AP1R3_EL2 = 0xE64B
|
||
|
|
ARM64_SYSREG_ICH_EISR_EL2 = 0xE65B
|
||
|
|
ARM64_SYSREG_ICH_ELRSR_EL2 = 0xE65D
|
||
|
|
ARM64_SYSREG_ICH_HCR_EL2 = 0xE658
|
||
|
|
ARM64_SYSREG_ICH_LR0_EL2 = 0xE660
|
||
|
|
ARM64_SYSREG_ICH_LR10_EL2 = 0xE66A
|
||
|
|
ARM64_SYSREG_ICH_LR11_EL2 = 0xE66B
|
||
|
|
ARM64_SYSREG_ICH_LR12_EL2 = 0xE66C
|
||
|
|
ARM64_SYSREG_ICH_LR13_EL2 = 0xE66D
|
||
|
|
ARM64_SYSREG_ICH_LR14_EL2 = 0xE66E
|
||
|
|
ARM64_SYSREG_ICH_LR15_EL2 = 0xE66F
|
||
|
|
ARM64_SYSREG_ICH_LR1_EL2 = 0xE661
|
||
|
|
ARM64_SYSREG_ICH_LR2_EL2 = 0xE662
|
||
|
|
ARM64_SYSREG_ICH_LR3_EL2 = 0xE663
|
||
|
|
ARM64_SYSREG_ICH_LR4_EL2 = 0xE664
|
||
|
|
ARM64_SYSREG_ICH_LR5_EL2 = 0xE665
|
||
|
|
ARM64_SYSREG_ICH_LR6_EL2 = 0xE666
|
||
|
|
ARM64_SYSREG_ICH_LR7_EL2 = 0xE667
|
||
|
|
ARM64_SYSREG_ICH_LR8_EL2 = 0xE668
|
||
|
|
ARM64_SYSREG_ICH_LR9_EL2 = 0xE669
|
||
|
|
ARM64_SYSREG_ICH_MISR_EL2 = 0xE65A
|
||
|
|
ARM64_SYSREG_ICH_VMCR_EL2 = 0xE65F
|
||
|
|
ARM64_SYSREG_ICH_VTR_EL2 = 0xE659
|
||
|
|
ARM64_SYSREG_ID_AA64AFR0_EL1 = 0xC02C
|
||
|
|
ARM64_SYSREG_ID_AA64AFR1_EL1 = 0xC02D
|
||
|
|
ARM64_SYSREG_ID_AA64DFR0_EL1 = 0xC028
|
||
|
|
ARM64_SYSREG_ID_AA64DFR1_EL1 = 0xC029
|
||
|
|
ARM64_SYSREG_ID_AA64ISAR0_EL1 = 0xC030
|
||
|
|
ARM64_SYSREG_ID_AA64ISAR1_EL1 = 0xC031
|
||
|
|
ARM64_SYSREG_ID_AA64ISAR2_EL1 = 0xC032
|
||
|
|
ARM64_SYSREG_ID_AA64MMFR0_EL1 = 0xC038
|
||
|
|
ARM64_SYSREG_ID_AA64MMFR1_EL1 = 0xC039
|
||
|
|
ARM64_SYSREG_ID_AA64MMFR2_EL1 = 0xC03A
|
||
|
|
ARM64_SYSREG_ID_AA64PFR0_EL1 = 0xC020
|
||
|
|
ARM64_SYSREG_ID_AA64PFR1_EL1 = 0xC021
|
||
|
|
ARM64_SYSREG_ID_AA64SMFR0_EL1 = 0xC025
|
||
|
|
ARM64_SYSREG_ID_AA64ZFR0_EL1 = 0xC024
|
||
|
|
ARM64_SYSREG_ID_AFR0_EL1 = 0xC00B
|
||
|
|
ARM64_SYSREG_ID_DFR0_EL1 = 0xC00A
|
||
|
|
ARM64_SYSREG_ID_ISAR0_EL1 = 0xC010
|
||
|
|
ARM64_SYSREG_ID_ISAR1_EL1 = 0xC011
|
||
|
|
ARM64_SYSREG_ID_ISAR2_EL1 = 0xC012
|
||
|
|
ARM64_SYSREG_ID_ISAR3_EL1 = 0xC013
|
||
|
|
ARM64_SYSREG_ID_ISAR4_EL1 = 0xC014
|
||
|
|
ARM64_SYSREG_ID_ISAR5_EL1 = 0xC015
|
||
|
|
ARM64_SYSREG_ID_ISAR6_EL1 = 0xC017
|
||
|
|
ARM64_SYSREG_ID_MMFR0_EL1 = 0xC00C
|
||
|
|
ARM64_SYSREG_ID_MMFR1_EL1 = 0xC00D
|
||
|
|
ARM64_SYSREG_ID_MMFR2_EL1 = 0xC00E
|
||
|
|
ARM64_SYSREG_ID_MMFR3_EL1 = 0xC00F
|
||
|
|
ARM64_SYSREG_ID_MMFR4_EL1 = 0xC016
|
||
|
|
ARM64_SYSREG_ID_MMFR5_EL1 = 0xC01E
|
||
|
|
ARM64_SYSREG_ID_PFR0_EL1 = 0xC008
|
||
|
|
ARM64_SYSREG_ID_PFR1_EL1 = 0xC009
|
||
|
|
ARM64_SYSREG_ID_PFR2_EL1 = 0xC01C
|
||
|
|
ARM64_SYSREG_IFSR32_EL2 = 0xE281
|
||
|
|
ARM64_SYSREG_ISR_EL1 = 0xC608
|
||
|
|
ARM64_SYSREG_LORC_EL1 = 0xC523
|
||
|
|
ARM64_SYSREG_LOREA_EL1 = 0xC521
|
||
|
|
ARM64_SYSREG_LORID_EL1 = 0xC527
|
||
|
|
ARM64_SYSREG_LORN_EL1 = 0xC522
|
||
|
|
ARM64_SYSREG_LORSA_EL1 = 0xC520
|
||
|
|
ARM64_SYSREG_MAIR_EL1 = 0xC510
|
||
|
|
ARM64_SYSREG_MAIR_EL12 = 0xED10
|
||
|
|
ARM64_SYSREG_MAIR_EL2 = 0xE510
|
||
|
|
ARM64_SYSREG_MAIR_EL3 = 0xF510
|
||
|
|
ARM64_SYSREG_MDCCINT_EL1 = 0x8010
|
||
|
|
ARM64_SYSREG_MDCCSR_EL0 = 0x9808
|
||
|
|
ARM64_SYSREG_MDCR_EL2 = 0xE089
|
||
|
|
ARM64_SYSREG_MDCR_EL3 = 0xF099
|
||
|
|
ARM64_SYSREG_MDRAR_EL1 = 0x8080
|
||
|
|
ARM64_SYSREG_MDSCR_EL1 = 0x8012
|
||
|
|
ARM64_SYSREG_MFAR_EL3 = 0xF305
|
||
|
|
ARM64_SYSREG_MIDR_EL1 = 0xC000
|
||
|
|
ARM64_SYSREG_MPAM0_EL1 = 0xC529
|
||
|
|
ARM64_SYSREG_MPAM1_EL1 = 0xC528
|
||
|
|
ARM64_SYSREG_MPAM1_EL12 = 0xED28
|
||
|
|
ARM64_SYSREG_MPAM2_EL2 = 0xE528
|
||
|
|
ARM64_SYSREG_MPAM3_EL3 = 0xF528
|
||
|
|
ARM64_SYSREG_MPAMHCR_EL2 = 0xE520
|
||
|
|
ARM64_SYSREG_MPAMIDR_EL1 = 0xC524
|
||
|
|
ARM64_SYSREG_MPAMSM_EL1 = 0xC52B
|
||
|
|
ARM64_SYSREG_MPAMVPM0_EL2 = 0xE530
|
||
|
|
ARM64_SYSREG_MPAMVPM1_EL2 = 0xE531
|
||
|
|
ARM64_SYSREG_MPAMVPM2_EL2 = 0xE532
|
||
|
|
ARM64_SYSREG_MPAMVPM3_EL2 = 0xE533
|
||
|
|
ARM64_SYSREG_MPAMVPM4_EL2 = 0xE534
|
||
|
|
ARM64_SYSREG_MPAMVPM5_EL2 = 0xE535
|
||
|
|
ARM64_SYSREG_MPAMVPM6_EL2 = 0xE536
|
||
|
|
ARM64_SYSREG_MPAMVPM7_EL2 = 0xE537
|
||
|
|
ARM64_SYSREG_MPAMVPMV_EL2 = 0xE521
|
||
|
|
ARM64_SYSREG_MPIDR_EL1 = 0xC005
|
||
|
|
ARM64_SYSREG_MPUIR_EL1 = 0xC004
|
||
|
|
ARM64_SYSREG_MPUIR_EL2 = 0xE004
|
||
|
|
ARM64_SYSREG_MVFR0_EL1 = 0xC018
|
||
|
|
ARM64_SYSREG_MVFR1_EL1 = 0xC019
|
||
|
|
ARM64_SYSREG_MVFR2_EL1 = 0xC01A
|
||
|
|
ARM64_SYSREG_NZCV = 0xDA10
|
||
|
|
ARM64_SYSREG_OSDLR_EL1 = 0x809C
|
||
|
|
ARM64_SYSREG_OSDTRRX_EL1 = 0x8002
|
||
|
|
ARM64_SYSREG_OSDTRTX_EL1 = 0x801A
|
||
|
|
ARM64_SYSREG_OSECCR_EL1 = 0x8032
|
||
|
|
ARM64_SYSREG_OSLAR_EL1 = 0x8084
|
||
|
|
ARM64_SYSREG_OSLSR_EL1 = 0x808C
|
||
|
|
ARM64_SYSREG_PAN = 0xC213
|
||
|
|
ARM64_SYSREG_PAR_EL1 = 0xC3A0
|
||
|
|
ARM64_SYSREG_PMBIDR_EL1 = 0xC4D7
|
||
|
|
ARM64_SYSREG_PMBLIMITR_EL1 = 0xC4D0
|
||
|
|
ARM64_SYSREG_PMBPTR_EL1 = 0xC4D1
|
||
|
|
ARM64_SYSREG_PMBSR_EL1 = 0xC4D3
|
||
|
|
ARM64_SYSREG_PMCCFILTR_EL0 = 0xDF7F
|
||
|
|
ARM64_SYSREG_PMCCNTR_EL0 = 0xDCE8
|
||
|
|
ARM64_SYSREG_PMCEID0_EL0 = 0xDCE6
|
||
|
|
ARM64_SYSREG_PMCEID1_EL0 = 0xDCE7
|
||
|
|
ARM64_SYSREG_PMCNTENCLR_EL0 = 0xDCE2
|
||
|
|
ARM64_SYSREG_PMCNTENSET_EL0 = 0xDCE1
|
||
|
|
ARM64_SYSREG_PMCR_EL0 = 0xDCE0
|
||
|
|
ARM64_SYSREG_PMEVCNTR0_EL0 = 0xDF40
|
||
|
|
ARM64_SYSREG_PMEVCNTR10_EL0 = 0xDF4A
|
||
|
|
ARM64_SYSREG_PMEVCNTR11_EL0 = 0xDF4B
|
||
|
|
ARM64_SYSREG_PMEVCNTR12_EL0 = 0xDF4C
|
||
|
|
ARM64_SYSREG_PMEVCNTR13_EL0 = 0xDF4D
|
||
|
|
ARM64_SYSREG_PMEVCNTR14_EL0 = 0xDF4E
|
||
|
|
ARM64_SYSREG_PMEVCNTR15_EL0 = 0xDF4F
|
||
|
|
ARM64_SYSREG_PMEVCNTR16_EL0 = 0xDF50
|
||
|
|
ARM64_SYSREG_PMEVCNTR17_EL0 = 0xDF51
|
||
|
|
ARM64_SYSREG_PMEVCNTR18_EL0 = 0xDF52
|
||
|
|
ARM64_SYSREG_PMEVCNTR19_EL0 = 0xDF53
|
||
|
|
ARM64_SYSREG_PMEVCNTR1_EL0 = 0xDF41
|
||
|
|
ARM64_SYSREG_PMEVCNTR20_EL0 = 0xDF54
|
||
|
|
ARM64_SYSREG_PMEVCNTR21_EL0 = 0xDF55
|
||
|
|
ARM64_SYSREG_PMEVCNTR22_EL0 = 0xDF56
|
||
|
|
ARM64_SYSREG_PMEVCNTR23_EL0 = 0xDF57
|
||
|
|
ARM64_SYSREG_PMEVCNTR24_EL0 = 0xDF58
|
||
|
|
ARM64_SYSREG_PMEVCNTR25_EL0 = 0xDF59
|
||
|
|
ARM64_SYSREG_PMEVCNTR26_EL0 = 0xDF5A
|
||
|
|
ARM64_SYSREG_PMEVCNTR27_EL0 = 0xDF5B
|
||
|
|
ARM64_SYSREG_PMEVCNTR28_EL0 = 0xDF5C
|
||
|
|
ARM64_SYSREG_PMEVCNTR29_EL0 = 0xDF5D
|
||
|
|
ARM64_SYSREG_PMEVCNTR2_EL0 = 0xDF42
|
||
|
|
ARM64_SYSREG_PMEVCNTR30_EL0 = 0xDF5E
|
||
|
|
ARM64_SYSREG_PMEVCNTR3_EL0 = 0xDF43
|
||
|
|
ARM64_SYSREG_PMEVCNTR4_EL0 = 0xDF44
|
||
|
|
ARM64_SYSREG_PMEVCNTR5_EL0 = 0xDF45
|
||
|
|
ARM64_SYSREG_PMEVCNTR6_EL0 = 0xDF46
|
||
|
|
ARM64_SYSREG_PMEVCNTR7_EL0 = 0xDF47
|
||
|
|
ARM64_SYSREG_PMEVCNTR8_EL0 = 0xDF48
|
||
|
|
ARM64_SYSREG_PMEVCNTR9_EL0 = 0xDF49
|
||
|
|
ARM64_SYSREG_PMEVTYPER0_EL0 = 0xDF60
|
||
|
|
ARM64_SYSREG_PMEVTYPER10_EL0 = 0xDF6A
|
||
|
|
ARM64_SYSREG_PMEVTYPER11_EL0 = 0xDF6B
|
||
|
|
ARM64_SYSREG_PMEVTYPER12_EL0 = 0xDF6C
|
||
|
|
ARM64_SYSREG_PMEVTYPER13_EL0 = 0xDF6D
|
||
|
|
ARM64_SYSREG_PMEVTYPER14_EL0 = 0xDF6E
|
||
|
|
ARM64_SYSREG_PMEVTYPER15_EL0 = 0xDF6F
|
||
|
|
ARM64_SYSREG_PMEVTYPER16_EL0 = 0xDF70
|
||
|
|
ARM64_SYSREG_PMEVTYPER17_EL0 = 0xDF71
|
||
|
|
ARM64_SYSREG_PMEVTYPER18_EL0 = 0xDF72
|
||
|
|
ARM64_SYSREG_PMEVTYPER19_EL0 = 0xDF73
|
||
|
|
ARM64_SYSREG_PMEVTYPER1_EL0 = 0xDF61
|
||
|
|
ARM64_SYSREG_PMEVTYPER20_EL0 = 0xDF74
|
||
|
|
ARM64_SYSREG_PMEVTYPER21_EL0 = 0xDF75
|
||
|
|
ARM64_SYSREG_PMEVTYPER22_EL0 = 0xDF76
|
||
|
|
ARM64_SYSREG_PMEVTYPER23_EL0 = 0xDF77
|
||
|
|
ARM64_SYSREG_PMEVTYPER24_EL0 = 0xDF78
|
||
|
|
ARM64_SYSREG_PMEVTYPER25_EL0 = 0xDF79
|
||
|
|
ARM64_SYSREG_PMEVTYPER26_EL0 = 0xDF7A
|
||
|
|
ARM64_SYSREG_PMEVTYPER27_EL0 = 0xDF7B
|
||
|
|
ARM64_SYSREG_PMEVTYPER28_EL0 = 0xDF7C
|
||
|
|
ARM64_SYSREG_PMEVTYPER29_EL0 = 0xDF7D
|
||
|
|
ARM64_SYSREG_PMEVTYPER2_EL0 = 0xDF62
|
||
|
|
ARM64_SYSREG_PMEVTYPER30_EL0 = 0xDF7E
|
||
|
|
ARM64_SYSREG_PMEVTYPER3_EL0 = 0xDF63
|
||
|
|
ARM64_SYSREG_PMEVTYPER4_EL0 = 0xDF64
|
||
|
|
ARM64_SYSREG_PMEVTYPER5_EL0 = 0xDF65
|
||
|
|
ARM64_SYSREG_PMEVTYPER6_EL0 = 0xDF66
|
||
|
|
ARM64_SYSREG_PMEVTYPER7_EL0 = 0xDF67
|
||
|
|
ARM64_SYSREG_PMEVTYPER8_EL0 = 0xDF68
|
||
|
|
ARM64_SYSREG_PMEVTYPER9_EL0 = 0xDF69
|
||
|
|
ARM64_SYSREG_PMINTENCLR_EL1 = 0xC4F2
|
||
|
|
ARM64_SYSREG_PMINTENSET_EL1 = 0xC4F1
|
||
|
|
ARM64_SYSREG_PMMIR_EL1 = 0xC4F6
|
||
|
|
ARM64_SYSREG_PMOVSCLR_EL0 = 0xDCE3
|
||
|
|
ARM64_SYSREG_PMOVSSET_EL0 = 0xDCF3
|
||
|
|
ARM64_SYSREG_PMSCR_EL1 = 0xC4C8
|
||
|
|
ARM64_SYSREG_PMSCR_EL12 = 0xECC8
|
||
|
|
ARM64_SYSREG_PMSCR_EL2 = 0xE4C8
|
||
|
|
ARM64_SYSREG_PMSELR_EL0 = 0xDCE5
|
||
|
|
ARM64_SYSREG_PMSEVFR_EL1 = 0xC4CD
|
||
|
|
ARM64_SYSREG_PMSFCR_EL1 = 0xC4CC
|
||
|
|
ARM64_SYSREG_PMSICR_EL1 = 0xC4CA
|
||
|
|
ARM64_SYSREG_PMSIDR_EL1 = 0xC4CF
|
||
|
|
ARM64_SYSREG_PMSIRR_EL1 = 0xC4CB
|
||
|
|
ARM64_SYSREG_PMSLATFR_EL1 = 0xC4CE
|
||
|
|
ARM64_SYSREG_PMSNEVFR_EL1 = 0xC4C9
|
||
|
|
ARM64_SYSREG_PMSWINC_EL0 = 0xDCE4
|
||
|
|
ARM64_SYSREG_PMUSERENR_EL0 = 0xDCF0
|
||
|
|
ARM64_SYSREG_PMXEVCNTR_EL0 = 0xDCEA
|
||
|
|
ARM64_SYSREG_PMXEVTYPER_EL0 = 0xDCE9
|
||
|
|
ARM64_SYSREG_PRBAR10_EL1 = 0xC368
|
||
|
|
ARM64_SYSREG_PRBAR10_EL2 = 0xE368
|
||
|
|
ARM64_SYSREG_PRBAR11_EL1 = 0xC36C
|
||
|
|
ARM64_SYSREG_PRBAR11_EL2 = 0xE36C
|
||
|
|
ARM64_SYSREG_PRBAR12_EL1 = 0xC370
|
||
|
|
ARM64_SYSREG_PRBAR12_EL2 = 0xE370
|
||
|
|
ARM64_SYSREG_PRBAR13_EL1 = 0xC374
|
||
|
|
ARM64_SYSREG_PRBAR13_EL2 = 0xE374
|
||
|
|
ARM64_SYSREG_PRBAR14_EL1 = 0xC378
|
||
|
|
ARM64_SYSREG_PRBAR14_EL2 = 0xE378
|
||
|
|
ARM64_SYSREG_PRBAR15_EL1 = 0xC37C
|
||
|
|
ARM64_SYSREG_PRBAR15_EL2 = 0xE37C
|
||
|
|
ARM64_SYSREG_PRBAR1_EL1 = 0xC344
|
||
|
|
ARM64_SYSREG_PRBAR1_EL2 = 0xE344
|
||
|
|
ARM64_SYSREG_PRBAR2_EL1 = 0xC348
|
||
|
|
ARM64_SYSREG_PRBAR2_EL2 = 0xE348
|
||
|
|
ARM64_SYSREG_PRBAR3_EL1 = 0xC34C
|
||
|
|
ARM64_SYSREG_PRBAR3_EL2 = 0xE34C
|
||
|
|
ARM64_SYSREG_PRBAR4_EL1 = 0xC350
|
||
|
|
ARM64_SYSREG_PRBAR4_EL2 = 0xE350
|
||
|
|
ARM64_SYSREG_PRBAR5_EL1 = 0xC354
|
||
|
|
ARM64_SYSREG_PRBAR5_EL2 = 0xE354
|
||
|
|
ARM64_SYSREG_PRBAR6_EL1 = 0xC358
|
||
|
|
ARM64_SYSREG_PRBAR6_EL2 = 0xE358
|
||
|
|
ARM64_SYSREG_PRBAR7_EL1 = 0xC35C
|
||
|
|
ARM64_SYSREG_PRBAR7_EL2 = 0xE35C
|
||
|
|
ARM64_SYSREG_PRBAR8_EL1 = 0xC360
|
||
|
|
ARM64_SYSREG_PRBAR8_EL2 = 0xE360
|
||
|
|
ARM64_SYSREG_PRBAR9_EL1 = 0xC364
|
||
|
|
ARM64_SYSREG_PRBAR9_EL2 = 0xE364
|
||
|
|
ARM64_SYSREG_PRBAR_EL1 = 0xC340
|
||
|
|
ARM64_SYSREG_PRBAR_EL2 = 0xE340
|
||
|
|
ARM64_SYSREG_PRENR_EL1 = 0xC309
|
||
|
|
ARM64_SYSREG_PRENR_EL2 = 0xE309
|
||
|
|
ARM64_SYSREG_PRLAR10_EL1 = 0xC369
|
||
|
|
ARM64_SYSREG_PRLAR10_EL2 = 0xE369
|
||
|
|
ARM64_SYSREG_PRLAR11_EL1 = 0xC36D
|
||
|
|
ARM64_SYSREG_PRLAR11_EL2 = 0xE36D
|
||
|
|
ARM64_SYSREG_PRLAR12_EL1 = 0xC371
|
||
|
|
ARM64_SYSREG_PRLAR12_EL2 = 0xE371
|
||
|
|
ARM64_SYSREG_PRLAR13_EL1 = 0xC375
|
||
|
|
ARM64_SYSREG_PRLAR13_EL2 = 0xE375
|
||
|
|
ARM64_SYSREG_PRLAR14_EL1 = 0xC379
|
||
|
|
ARM64_SYSREG_PRLAR14_EL2 = 0xE379
|
||
|
|
ARM64_SYSREG_PRLAR15_EL1 = 0xC37D
|
||
|
|
ARM64_SYSREG_PRLAR15_EL2 = 0xE37D
|
||
|
|
ARM64_SYSREG_PRLAR1_EL1 = 0xC345
|
||
|
|
ARM64_SYSREG_PRLAR1_EL2 = 0xE345
|
||
|
|
ARM64_SYSREG_PRLAR2_EL1 = 0xC349
|
||
|
|
ARM64_SYSREG_PRLAR2_EL2 = 0xE349
|
||
|
|
ARM64_SYSREG_PRLAR3_EL1 = 0xC34D
|
||
|
|
ARM64_SYSREG_PRLAR3_EL2 = 0xE34D
|
||
|
|
ARM64_SYSREG_PRLAR4_EL1 = 0xC351
|
||
|
|
ARM64_SYSREG_PRLAR4_EL2 = 0xE351
|
||
|
|
ARM64_SYSREG_PRLAR5_EL1 = 0xC355
|
||
|
|
ARM64_SYSREG_PRLAR5_EL2 = 0xE355
|
||
|
|
ARM64_SYSREG_PRLAR6_EL1 = 0xC359
|
||
|
|
ARM64_SYSREG_PRLAR6_EL2 = 0xE359
|
||
|
|
ARM64_SYSREG_PRLAR7_EL1 = 0xC35D
|
||
|
|
ARM64_SYSREG_PRLAR7_EL2 = 0xE35D
|
||
|
|
ARM64_SYSREG_PRLAR8_EL1 = 0xC361
|
||
|
|
ARM64_SYSREG_PRLAR8_EL2 = 0xE361
|
||
|
|
ARM64_SYSREG_PRLAR9_EL1 = 0xC365
|
||
|
|
ARM64_SYSREG_PRLAR9_EL2 = 0xE365
|
||
|
|
ARM64_SYSREG_PRLAR_EL1 = 0xC341
|
||
|
|
ARM64_SYSREG_PRLAR_EL2 = 0xE341
|
||
|
|
ARM64_SYSREG_PRSELR_EL1 = 0xC311
|
||
|
|
ARM64_SYSREG_PRSELR_EL2 = 0xE311
|
||
|
|
ARM64_SYSREG_REVIDR_EL1 = 0xC006
|
||
|
|
ARM64_SYSREG_RGSR_EL1 = 0xC085
|
||
|
|
ARM64_SYSREG_RMR_EL1 = 0xC602
|
||
|
|
ARM64_SYSREG_RMR_EL2 = 0xE602
|
||
|
|
ARM64_SYSREG_RMR_EL3 = 0xF602
|
||
|
|
ARM64_SYSREG_RNDR = 0xD920
|
||
|
|
ARM64_SYSREG_RNDRRS = 0xD921
|
||
|
|
ARM64_SYSREG_RVBAR_EL1 = 0xC601
|
||
|
|
ARM64_SYSREG_RVBAR_EL2 = 0xE601
|
||
|
|
ARM64_SYSREG_RVBAR_EL3 = 0xF601
|
||
|
|
ARM64_SYSREG_SCR_EL3 = 0xF088
|
||
|
|
ARM64_SYSREG_SCTLR_EL1 = 0xC080
|
||
|
|
ARM64_SYSREG_SCTLR_EL12 = 0xE880
|
||
|
|
ARM64_SYSREG_SCTLR_EL2 = 0xE080
|
||
|
|
ARM64_SYSREG_SCTLR_EL3 = 0xF080
|
||
|
|
ARM64_SYSREG_SCXTNUM_EL0 = 0xDE87
|
||
|
|
ARM64_SYSREG_SCXTNUM_EL1 = 0xC687
|
||
|
|
ARM64_SYSREG_SCXTNUM_EL12 = 0xEE87
|
||
|
|
ARM64_SYSREG_SCXTNUM_EL2 = 0xE687
|
||
|
|
ARM64_SYSREG_SCXTNUM_EL3 = 0xF687
|
||
|
|
ARM64_SYSREG_SDER32_EL2 = 0xE099
|
||
|
|
ARM64_SYSREG_SDER32_EL3 = 0xF089
|
||
|
|
ARM64_SYSREG_SMCR_EL1 = 0xC096
|
||
|
|
ARM64_SYSREG_SMCR_EL12 = 0xE896
|
||
|
|
ARM64_SYSREG_SMCR_EL2 = 0xE096
|
||
|
|
ARM64_SYSREG_SMCR_EL3 = 0xF096
|
||
|
|
ARM64_SYSREG_SMIDR_EL1 = 0xC806
|
||
|
|
ARM64_SYSREG_SMPRIMAP_EL2 = 0xE095
|
||
|
|
ARM64_SYSREG_SMPRI_EL1 = 0xC094
|
||
|
|
ARM64_SYSREG_SPSEL = 0xC210
|
||
|
|
ARM64_SYSREG_SPSR_ABT = 0xE219
|
||
|
|
ARM64_SYSREG_SPSR_EL1 = 0xC200
|
||
|
|
ARM64_SYSREG_SPSR_EL12 = 0xEA00
|
||
|
|
ARM64_SYSREG_SPSR_EL2 = 0xE200
|
||
|
|
ARM64_SYSREG_SPSR_EL3 = 0xF200
|
||
|
|
ARM64_SYSREG_SPSR_FIQ = 0xE21B
|
||
|
|
ARM64_SYSREG_SPSR_IRQ = 0xE218
|
||
|
|
ARM64_SYSREG_SPSR_UND = 0xE21A
|
||
|
|
ARM64_SYSREG_SP_EL0 = 0xC208
|
||
|
|
ARM64_SYSREG_SP_EL1 = 0xE208
|
||
|
|
ARM64_SYSREG_SP_EL2 = 0xF208
|
||
|
|
ARM64_SYSREG_SSBS = 0xDA16
|
||
|
|
ARM64_SYSREG_SVCR = 0xDA12
|
||
|
|
ARM64_SYSREG_TCO = 0xDA17
|
||
|
|
ARM64_SYSREG_TCR_EL1 = 0xC102
|
||
|
|
ARM64_SYSREG_TCR_EL12 = 0xE902
|
||
|
|
ARM64_SYSREG_TCR_EL2 = 0xE102
|
||
|
|
ARM64_SYSREG_TCR_EL3 = 0xF102
|
||
|
|
ARM64_SYSREG_TEECR32_EL1 = 0x9000
|
||
|
|
ARM64_SYSREG_TEEHBR32_EL1 = 0x9080
|
||
|
|
ARM64_SYSREG_TFSRE0_EL1 = 0xC2B1
|
||
|
|
ARM64_SYSREG_TFSR_EL1 = 0xC2B0
|
||
|
|
ARM64_SYSREG_TFSR_EL12 = 0xEAB0
|
||
|
|
ARM64_SYSREG_TFSR_EL2 = 0xE2B0
|
||
|
|
ARM64_SYSREG_TFSR_EL3 = 0xF2B0
|
||
|
|
ARM64_SYSREG_TPIDR2_EL0 = 0xDE85
|
||
|
|
ARM64_SYSREG_TPIDRRO_EL0 = 0xDE83
|
||
|
|
ARM64_SYSREG_TPIDR_EL0 = 0xDE82
|
||
|
|
ARM64_SYSREG_TPIDR_EL1 = 0xC684
|
||
|
|
ARM64_SYSREG_TPIDR_EL2 = 0xE682
|
||
|
|
ARM64_SYSREG_TPIDR_EL3 = 0xF682
|
||
|
|
ARM64_SYSREG_TRBBASER_EL1 = 0xC4DA
|
||
|
|
ARM64_SYSREG_TRBIDR_EL1 = 0xC4DF
|
||
|
|
ARM64_SYSREG_TRBLIMITR_EL1 = 0xC4D8
|
||
|
|
ARM64_SYSREG_TRBMAR_EL1 = 0xC4DC
|
||
|
|
ARM64_SYSREG_TRBPTR_EL1 = 0xC4D9
|
||
|
|
ARM64_SYSREG_TRBSR_EL1 = 0xC4DB
|
||
|
|
ARM64_SYSREG_TRBTRG_EL1 = 0xC4DE
|
||
|
|
ARM64_SYSREG_TRCACATR0 = 0x8902
|
||
|
|
ARM64_SYSREG_TRCACATR1 = 0x8912
|
||
|
|
ARM64_SYSREG_TRCACATR10 = 0x8923
|
||
|
|
ARM64_SYSREG_TRCACATR11 = 0x8933
|
||
|
|
ARM64_SYSREG_TRCACATR12 = 0x8943
|
||
|
|
ARM64_SYSREG_TRCACATR13 = 0x8953
|
||
|
|
ARM64_SYSREG_TRCACATR14 = 0x8963
|
||
|
|
ARM64_SYSREG_TRCACATR15 = 0x8973
|
||
|
|
ARM64_SYSREG_TRCACATR2 = 0x8922
|
||
|
|
ARM64_SYSREG_TRCACATR3 = 0x8932
|
||
|
|
ARM64_SYSREG_TRCACATR4 = 0x8942
|
||
|
|
ARM64_SYSREG_TRCACATR5 = 0x8952
|
||
|
|
ARM64_SYSREG_TRCACATR6 = 0x8962
|
||
|
|
ARM64_SYSREG_TRCACATR7 = 0x8972
|
||
|
|
ARM64_SYSREG_TRCACATR8 = 0x8903
|
||
|
|
ARM64_SYSREG_TRCACATR9 = 0x8913
|
||
|
|
ARM64_SYSREG_TRCACVR0 = 0x8900
|
||
|
|
ARM64_SYSREG_TRCACVR1 = 0x8910
|
||
|
|
ARM64_SYSREG_TRCACVR10 = 0x8921
|
||
|
|
ARM64_SYSREG_TRCACVR11 = 0x8931
|
||
|
|
ARM64_SYSREG_TRCACVR12 = 0x8941
|
||
|
|
ARM64_SYSREG_TRCACVR13 = 0x8951
|
||
|
|
ARM64_SYSREG_TRCACVR14 = 0x8961
|
||
|
|
ARM64_SYSREG_TRCACVR15 = 0x8971
|
||
|
|
ARM64_SYSREG_TRCACVR2 = 0x8920
|
||
|
|
ARM64_SYSREG_TRCACVR3 = 0x8930
|
||
|
|
ARM64_SYSREG_TRCACVR4 = 0x8940
|
||
|
|
ARM64_SYSREG_TRCACVR5 = 0x8950
|
||
|
|
ARM64_SYSREG_TRCACVR6 = 0x8960
|
||
|
|
ARM64_SYSREG_TRCACVR7 = 0x8970
|
||
|
|
ARM64_SYSREG_TRCACVR8 = 0x8901
|
||
|
|
ARM64_SYSREG_TRCACVR9 = 0x8911
|
||
|
|
ARM64_SYSREG_TRCAUTHSTATUS = 0x8BF6
|
||
|
|
ARM64_SYSREG_TRCAUXCTLR = 0x8830
|
||
|
|
ARM64_SYSREG_TRCBBCTLR = 0x8878
|
||
|
|
ARM64_SYSREG_TRCCCCTLR = 0x8870
|
||
|
|
ARM64_SYSREG_TRCCIDCCTLR0 = 0x8982
|
||
|
|
ARM64_SYSREG_TRCCIDCCTLR1 = 0x898A
|
||
|
|
ARM64_SYSREG_TRCCIDCVR0 = 0x8980
|
||
|
|
ARM64_SYSREG_TRCCIDCVR1 = 0x8990
|
||
|
|
ARM64_SYSREG_TRCCIDCVR2 = 0x89A0
|
||
|
|
ARM64_SYSREG_TRCCIDCVR3 = 0x89B0
|
||
|
|
ARM64_SYSREG_TRCCIDCVR4 = 0x89C0
|
||
|
|
ARM64_SYSREG_TRCCIDCVR5 = 0x89D0
|
||
|
|
ARM64_SYSREG_TRCCIDCVR6 = 0x89E0
|
||
|
|
ARM64_SYSREG_TRCCIDCVR7 = 0x89F0
|
||
|
|
ARM64_SYSREG_TRCCIDR0 = 0x8BE7
|
||
|
|
ARM64_SYSREG_TRCCIDR1 = 0x8BEF
|
||
|
|
ARM64_SYSREG_TRCCIDR2 = 0x8BF7
|
||
|
|
ARM64_SYSREG_TRCCIDR3 = 0x8BFF
|
||
|
|
ARM64_SYSREG_TRCCLAIMCLR = 0x8BCE
|
||
|
|
ARM64_SYSREG_TRCCLAIMSET = 0x8BC6
|
||
|
|
ARM64_SYSREG_TRCCNTCTLR0 = 0x8825
|
||
|
|
ARM64_SYSREG_TRCCNTCTLR1 = 0x882D
|
||
|
|
ARM64_SYSREG_TRCCNTCTLR2 = 0x8835
|
||
|
|
ARM64_SYSREG_TRCCNTCTLR3 = 0x883D
|
||
|
|
ARM64_SYSREG_TRCCNTRLDVR0 = 0x8805
|
||
|
|
ARM64_SYSREG_TRCCNTRLDVR1 = 0x880D
|
||
|
|
ARM64_SYSREG_TRCCNTRLDVR2 = 0x8815
|
||
|
|
ARM64_SYSREG_TRCCNTRLDVR3 = 0x881D
|
||
|
|
ARM64_SYSREG_TRCCNTVR0 = 0x8845
|
||
|
|
ARM64_SYSREG_TRCCNTVR1 = 0x884D
|
||
|
|
ARM64_SYSREG_TRCCNTVR2 = 0x8855
|
||
|
|
ARM64_SYSREG_TRCCNTVR3 = 0x885D
|
||
|
|
ARM64_SYSREG_TRCCONFIGR = 0x8820
|
||
|
|
ARM64_SYSREG_TRCDEVAFF0 = 0x8BD6
|
||
|
|
ARM64_SYSREG_TRCDEVAFF1 = 0x8BDE
|
||
|
|
ARM64_SYSREG_TRCDEVARCH = 0x8BFE
|
||
|
|
ARM64_SYSREG_TRCDEVID = 0x8B97
|
||
|
|
ARM64_SYSREG_TRCDEVTYPE = 0x8B9F
|
||
|
|
ARM64_SYSREG_TRCDVCMR0 = 0x8906
|
||
|
|
ARM64_SYSREG_TRCDVCMR1 = 0x8926
|
||
|
|
ARM64_SYSREG_TRCDVCMR2 = 0x8946
|
||
|
|
ARM64_SYSREG_TRCDVCMR3 = 0x8966
|
||
|
|
ARM64_SYSREG_TRCDVCMR4 = 0x8907
|
||
|
|
ARM64_SYSREG_TRCDVCMR5 = 0x8927
|
||
|
|
ARM64_SYSREG_TRCDVCMR6 = 0x8947
|
||
|
|
ARM64_SYSREG_TRCDVCMR7 = 0x8967
|
||
|
|
ARM64_SYSREG_TRCDVCVR0 = 0x8904
|
||
|
|
ARM64_SYSREG_TRCDVCVR1 = 0x8924
|
||
|
|
ARM64_SYSREG_TRCDVCVR2 = 0x8944
|
||
|
|
ARM64_SYSREG_TRCDVCVR3 = 0x8964
|
||
|
|
ARM64_SYSREG_TRCDVCVR4 = 0x8905
|
||
|
|
ARM64_SYSREG_TRCDVCVR5 = 0x8925
|
||
|
|
ARM64_SYSREG_TRCDVCVR6 = 0x8945
|
||
|
|
ARM64_SYSREG_TRCDVCVR7 = 0x8965
|
||
|
|
ARM64_SYSREG_TRCEVENTCTL0R = 0x8840
|
||
|
|
ARM64_SYSREG_TRCEVENTCTL1R = 0x8848
|
||
|
|
ARM64_SYSREG_TRCEXTINSELR = 0x8844
|
||
|
|
ARM64_SYSREG_TRCEXTINSELR0 = 0x8844
|
||
|
|
ARM64_SYSREG_TRCEXTINSELR1 = 0x884C
|
||
|
|
ARM64_SYSREG_TRCEXTINSELR2 = 0x8854
|
||
|
|
ARM64_SYSREG_TRCEXTINSELR3 = 0x885C
|
||
|
|
ARM64_SYSREG_TRCIDR0 = 0x8847
|
||
|
|
ARM64_SYSREG_TRCIDR1 = 0x884F
|
||
|
|
ARM64_SYSREG_TRCIDR10 = 0x8816
|
||
|
|
ARM64_SYSREG_TRCIDR11 = 0x881E
|
||
|
|
ARM64_SYSREG_TRCIDR12 = 0x8826
|
||
|
|
ARM64_SYSREG_TRCIDR13 = 0x882E
|
||
|
|
ARM64_SYSREG_TRCIDR2 = 0x8857
|
||
|
|
ARM64_SYSREG_TRCIDR3 = 0x885F
|
||
|
|
ARM64_SYSREG_TRCIDR4 = 0x8867
|
||
|
|
ARM64_SYSREG_TRCIDR5 = 0x886F
|
||
|
|
ARM64_SYSREG_TRCIDR6 = 0x8877
|
||
|
|
ARM64_SYSREG_TRCIDR7 = 0x887F
|
||
|
|
ARM64_SYSREG_TRCIDR8 = 0x8806
|
||
|
|
ARM64_SYSREG_TRCIDR9 = 0x880E
|
||
|
|
ARM64_SYSREG_TRCIMSPEC0 = 0x8807
|
||
|
|
ARM64_SYSREG_TRCIMSPEC1 = 0x880F
|
||
|
|
ARM64_SYSREG_TRCIMSPEC2 = 0x8817
|
||
|
|
ARM64_SYSREG_TRCIMSPEC3 = 0x881F
|
||
|
|
ARM64_SYSREG_TRCIMSPEC4 = 0x8827
|
||
|
|
ARM64_SYSREG_TRCIMSPEC5 = 0x882F
|
||
|
|
ARM64_SYSREG_TRCIMSPEC6 = 0x8837
|
||
|
|
ARM64_SYSREG_TRCIMSPEC7 = 0x883F
|
||
|
|
ARM64_SYSREG_TRCITCTRL = 0x8B84
|
||
|
|
ARM64_SYSREG_TRCLAR = 0x8BE6
|
||
|
|
ARM64_SYSREG_TRCLSR = 0x8BEE
|
||
|
|
ARM64_SYSREG_TRCOSLAR = 0x8884
|
||
|
|
ARM64_SYSREG_TRCOSLSR = 0x888C
|
||
|
|
ARM64_SYSREG_TRCPDCR = 0x88A4
|
||
|
|
ARM64_SYSREG_TRCPDSR = 0x88AC
|
||
|
|
ARM64_SYSREG_TRCPIDR0 = 0x8BC7
|
||
|
|
ARM64_SYSREG_TRCPIDR1 = 0x8BCF
|
||
|
|
ARM64_SYSREG_TRCPIDR2 = 0x8BD7
|
||
|
|
ARM64_SYSREG_TRCPIDR3 = 0x8BDF
|
||
|
|
ARM64_SYSREG_TRCPIDR4 = 0x8BA7
|
||
|
|
ARM64_SYSREG_TRCPIDR5 = 0x8BAF
|
||
|
|
ARM64_SYSREG_TRCPIDR6 = 0x8BB7
|
||
|
|
ARM64_SYSREG_TRCPIDR7 = 0x8BBF
|
||
|
|
ARM64_SYSREG_TRCPRGCTLR = 0x8808
|
||
|
|
ARM64_SYSREG_TRCPROCSELR = 0x8810
|
||
|
|
ARM64_SYSREG_TRCQCTLR = 0x8809
|
||
|
|
ARM64_SYSREG_TRCRSCTLR10 = 0x88D0
|
||
|
|
ARM64_SYSREG_TRCRSCTLR11 = 0x88D8
|
||
|
|
ARM64_SYSREG_TRCRSCTLR12 = 0x88E0
|
||
|
|
ARM64_SYSREG_TRCRSCTLR13 = 0x88E8
|
||
|
|
ARM64_SYSREG_TRCRSCTLR14 = 0x88F0
|
||
|
|
ARM64_SYSREG_TRCRSCTLR15 = 0x88F8
|
||
|
|
ARM64_SYSREG_TRCRSCTLR16 = 0x8881
|
||
|
|
ARM64_SYSREG_TRCRSCTLR17 = 0x8889
|
||
|
|
ARM64_SYSREG_TRCRSCTLR18 = 0x8891
|
||
|
|
ARM64_SYSREG_TRCRSCTLR19 = 0x8899
|
||
|
|
ARM64_SYSREG_TRCRSCTLR2 = 0x8890
|
||
|
|
ARM64_SYSREG_TRCRSCTLR20 = 0x88A1
|
||
|
|
ARM64_SYSREG_TRCRSCTLR21 = 0x88A9
|
||
|
|
ARM64_SYSREG_TRCRSCTLR22 = 0x88B1
|
||
|
|
ARM64_SYSREG_TRCRSCTLR23 = 0x88B9
|
||
|
|
ARM64_SYSREG_TRCRSCTLR24 = 0x88C1
|
||
|
|
ARM64_SYSREG_TRCRSCTLR25 = 0x88C9
|
||
|
|
ARM64_SYSREG_TRCRSCTLR26 = 0x88D1
|
||
|
|
ARM64_SYSREG_TRCRSCTLR27 = 0x88D9
|
||
|
|
ARM64_SYSREG_TRCRSCTLR28 = 0x88E1
|
||
|
|
ARM64_SYSREG_TRCRSCTLR29 = 0x88E9
|
||
|
|
ARM64_SYSREG_TRCRSCTLR3 = 0x8898
|
||
|
|
ARM64_SYSREG_TRCRSCTLR30 = 0x88F1
|
||
|
|
ARM64_SYSREG_TRCRSCTLR31 = 0x88F9
|
||
|
|
ARM64_SYSREG_TRCRSCTLR4 = 0x88A0
|
||
|
|
ARM64_SYSREG_TRCRSCTLR5 = 0x88A8
|
||
|
|
ARM64_SYSREG_TRCRSCTLR6 = 0x88B0
|
||
|
|
ARM64_SYSREG_TRCRSCTLR7 = 0x88B8
|
||
|
|
ARM64_SYSREG_TRCRSCTLR8 = 0x88C0
|
||
|
|
ARM64_SYSREG_TRCRSCTLR9 = 0x88C8
|
||
|
|
ARM64_SYSREG_TRCRSR = 0x8850
|
||
|
|
ARM64_SYSREG_TRCSEQEVR0 = 0x8804
|
||
|
|
ARM64_SYSREG_TRCSEQEVR1 = 0x880C
|
||
|
|
ARM64_SYSREG_TRCSEQEVR2 = 0x8814
|
||
|
|
ARM64_SYSREG_TRCSEQRSTEVR = 0x8834
|
||
|
|
ARM64_SYSREG_TRCSEQSTR = 0x883C
|
||
|
|
ARM64_SYSREG_TRCSSCCR0 = 0x8882
|
||
|
|
ARM64_SYSREG_TRCSSCCR1 = 0x888A
|
||
|
|
ARM64_SYSREG_TRCSSCCR2 = 0x8892
|
||
|
|
ARM64_SYSREG_TRCSSCCR3 = 0x889A
|
||
|
|
ARM64_SYSREG_TRCSSCCR4 = 0x88A2
|
||
|
|
ARM64_SYSREG_TRCSSCCR5 = 0x88AA
|
||
|
|
ARM64_SYSREG_TRCSSCCR6 = 0x88B2
|
||
|
|
ARM64_SYSREG_TRCSSCCR7 = 0x88BA
|
||
|
|
ARM64_SYSREG_TRCSSCSR0 = 0x88C2
|
||
|
|
ARM64_SYSREG_TRCSSCSR1 = 0x88CA
|
||
|
|
ARM64_SYSREG_TRCSSCSR2 = 0x88D2
|
||
|
|
ARM64_SYSREG_TRCSSCSR3 = 0x88DA
|
||
|
|
ARM64_SYSREG_TRCSSCSR4 = 0x88E2
|
||
|
|
ARM64_SYSREG_TRCSSCSR5 = 0x88EA
|
||
|
|
ARM64_SYSREG_TRCSSCSR6 = 0x88F2
|
||
|
|
ARM64_SYSREG_TRCSSCSR7 = 0x88FA
|
||
|
|
ARM64_SYSREG_TRCSSPCICR0 = 0x8883
|
||
|
|
ARM64_SYSREG_TRCSSPCICR1 = 0x888B
|
||
|
|
ARM64_SYSREG_TRCSSPCICR2 = 0x8893
|
||
|
|
ARM64_SYSREG_TRCSSPCICR3 = 0x889B
|
||
|
|
ARM64_SYSREG_TRCSSPCICR4 = 0x88A3
|
||
|
|
ARM64_SYSREG_TRCSSPCICR5 = 0x88AB
|
||
|
|
ARM64_SYSREG_TRCSSPCICR6 = 0x88B3
|
||
|
|
ARM64_SYSREG_TRCSSPCICR7 = 0x88BB
|
||
|
|
ARM64_SYSREG_TRCSTALLCTLR = 0x8858
|
||
|
|
ARM64_SYSREG_TRCSTATR = 0x8818
|
||
|
|
ARM64_SYSREG_TRCSYNCPR = 0x8868
|
||
|
|
ARM64_SYSREG_TRCTRACEIDR = 0x8801
|
||
|
|
ARM64_SYSREG_TRCTSCTLR = 0x8860
|
||
|
|
ARM64_SYSREG_TRCVDARCCTLR = 0x8852
|
||
|
|
ARM64_SYSREG_TRCVDCTLR = 0x8842
|
||
|
|
ARM64_SYSREG_TRCVDSACCTLR = 0x884A
|
||
|
|
ARM64_SYSREG_TRCVICTLR = 0x8802
|
||
|
|
ARM64_SYSREG_TRCVIIECTLR = 0x880A
|
||
|
|
ARM64_SYSREG_TRCVIPCSSCTLR = 0x881A
|
||
|
|
ARM64_SYSREG_TRCVISSCTLR = 0x8812
|
||
|
|
ARM64_SYSREG_TRCVMIDCCTLR0 = 0x8992
|
||
|
|
ARM64_SYSREG_TRCVMIDCCTLR1 = 0x899A
|
||
|
|
ARM64_SYSREG_TRCVMIDCVR0 = 0x8981
|
||
|
|
ARM64_SYSREG_TRCVMIDCVR1 = 0x8991
|
||
|
|
ARM64_SYSREG_TRCVMIDCVR2 = 0x89A1
|
||
|
|
ARM64_SYSREG_TRCVMIDCVR3 = 0x89B1
|
||
|
|
ARM64_SYSREG_TRCVMIDCVR4 = 0x89C1
|
||
|
|
ARM64_SYSREG_TRCVMIDCVR5 = 0x89D1
|
||
|
|
ARM64_SYSREG_TRCVMIDCVR6 = 0x89E1
|
||
|
|
ARM64_SYSREG_TRCVMIDCVR7 = 0x89F1
|
||
|
|
ARM64_SYSREG_TRFCR_EL1 = 0xC091
|
||
|
|
ARM64_SYSREG_TRFCR_EL12 = 0xE891
|
||
|
|
ARM64_SYSREG_TRFCR_EL2 = 0xE091
|
||
|
|
ARM64_SYSREG_TTBR0_EL1 = 0xC100
|
||
|
|
ARM64_SYSREG_TTBR0_EL12 = 0xE900
|
||
|
|
ARM64_SYSREG_TTBR0_EL2 = 0xE100
|
||
|
|
ARM64_SYSREG_TTBR0_EL3 = 0xF100
|
||
|
|
ARM64_SYSREG_TTBR1_EL1 = 0xC101
|
||
|
|
ARM64_SYSREG_TTBR1_EL12 = 0xE901
|
||
|
|
ARM64_SYSREG_TTBR1_EL2 = 0xE101
|
||
|
|
ARM64_SYSREG_UAO = 0xC214
|
||
|
|
ARM64_SYSREG_VBAR_EL1 = 0xC600
|
||
|
|
ARM64_SYSREG_VBAR_EL12 = 0xEE00
|
||
|
|
ARM64_SYSREG_VBAR_EL2 = 0xE600
|
||
|
|
ARM64_SYSREG_VBAR_EL3 = 0xF600
|
||
|
|
ARM64_SYSREG_VDISR_EL2 = 0xE609
|
||
|
|
ARM64_SYSREG_VMPIDR_EL2 = 0xE005
|
||
|
|
ARM64_SYSREG_VNCR_EL2 = 0xE110
|
||
|
|
ARM64_SYSREG_VPIDR_EL2 = 0xE000
|
||
|
|
ARM64_SYSREG_VSCTLR_EL2 = 0xE100
|
||
|
|
ARM64_SYSREG_VSESR_EL2 = 0xE293
|
||
|
|
ARM64_SYSREG_VSTCR_EL2 = 0xE132
|
||
|
|
ARM64_SYSREG_VSTTBR_EL2 = 0xE130
|
||
|
|
ARM64_SYSREG_VTCR_EL2 = 0xE10A
|
||
|
|
ARM64_SYSREG_VTTBR_EL2 = 0xE108
|
||
|
|
ARM64_SYSREG_ZCR_EL1 = 0xC090
|
||
|
|
ARM64_SYSREG_ZCR_EL12 = 0xE890
|
||
|
|
ARM64_SYSREG_ZCR_EL2 = 0xE090
|
||
|
|
ARM64_SYSREG_ZCR_EL3 = 0xF090
|
||
|
|
|
||
|
|
ARM64_PSTATE_INVALID = 0
|
||
|
|
ARM64_PSTATE_SPSEL = 0x05
|
||
|
|
ARM64_PSTATE_DAIFSET = 0x1e
|
||
|
|
ARM64_PSTATE_DAIFCLR = 0x1f
|
||
|
|
ARM64_PSTATE_PAN = 0x4
|
||
|
|
ARM64_PSTATE_UAO = 0x3
|
||
|
|
ARM64_PSTATE_DIT = 0x1a
|
||
|
|
|
||
|
|
ARM64_VAS_INVALID = 0
|
||
|
|
ARM64_VAS_16B = 1
|
||
|
|
ARM64_VAS_8B = 2
|
||
|
|
ARM64_VAS_4B = 3
|
||
|
|
ARM64_VAS_1B = 4
|
||
|
|
ARM64_VAS_8H = 5
|
||
|
|
ARM64_VAS_4H = 6
|
||
|
|
ARM64_VAS_2H = 7
|
||
|
|
ARM64_VAS_1H = 8
|
||
|
|
ARM64_VAS_4S = 9
|
||
|
|
ARM64_VAS_2S = 10
|
||
|
|
ARM64_VAS_1S = 11
|
||
|
|
ARM64_VAS_2D = 12
|
||
|
|
ARM64_VAS_1D = 13
|
||
|
|
ARM64_VAS_1Q = 14
|
||
|
|
|
||
|
|
ARM64_BARRIER_INVALID = 0
|
||
|
|
ARM64_BARRIER_OSHLD = 0x1
|
||
|
|
ARM64_BARRIER_OSHST = 0x2
|
||
|
|
ARM64_BARRIER_OSH = 0x3
|
||
|
|
ARM64_BARRIER_NSHLD = 0x5
|
||
|
|
ARM64_BARRIER_NSHST = 0x6
|
||
|
|
ARM64_BARRIER_NSH = 0x7
|
||
|
|
ARM64_BARRIER_ISHLD = 0x9
|
||
|
|
ARM64_BARRIER_ISHST = 0xa
|
||
|
|
ARM64_BARRIER_ISH = 0xb
|
||
|
|
ARM64_BARRIER_LD = 0xd
|
||
|
|
ARM64_BARRIER_ST = 0xe
|
||
|
|
ARM64_BARRIER_SY = 0xf
|
||
|
|
|
||
|
|
ARM64_OP_INVALID = 0
|
||
|
|
ARM64_OP_REG = 1
|
||
|
|
ARM64_OP_IMM = 2
|
||
|
|
ARM64_OP_MEM = 3
|
||
|
|
ARM64_OP_FP = 4
|
||
|
|
ARM64_OP_CIMM = 64
|
||
|
|
ARM64_OP_REG_MRS = 65
|
||
|
|
ARM64_OP_REG_MSR = 66
|
||
|
|
ARM64_OP_PSTATE = 67
|
||
|
|
ARM64_OP_SYS = 68
|
||
|
|
ARM64_OP_SVCR = 69
|
||
|
|
ARM64_OP_PREFETCH = 70
|
||
|
|
ARM64_OP_BARRIER = 71
|
||
|
|
ARM64_OP_SME_INDEX = 72
|
||
|
|
|
||
|
|
ARM64_SYS_INVALID = 0
|
||
|
|
ARM64_TLBI_ALLE1 = 1
|
||
|
|
ARM64_TLBI_ALLE1IS = 2
|
||
|
|
ARM64_TLBI_ALLE1ISNXS = 3
|
||
|
|
ARM64_TLBI_ALLE1NXS = 4
|
||
|
|
ARM64_TLBI_ALLE1OS = 5
|
||
|
|
ARM64_TLBI_ALLE1OSNXS = 6
|
||
|
|
ARM64_TLBI_ALLE2 = 7
|
||
|
|
ARM64_TLBI_ALLE2IS = 8
|
||
|
|
ARM64_TLBI_ALLE2ISNXS = 9
|
||
|
|
ARM64_TLBI_ALLE2NXS = 10
|
||
|
|
ARM64_TLBI_ALLE2OS = 11
|
||
|
|
ARM64_TLBI_ALLE2OSNXS = 12
|
||
|
|
ARM64_TLBI_ALLE3 = 13
|
||
|
|
ARM64_TLBI_ALLE3IS = 14
|
||
|
|
ARM64_TLBI_ALLE3ISNXS = 15
|
||
|
|
ARM64_TLBI_ALLE3NXS = 16
|
||
|
|
ARM64_TLBI_ALLE3OS = 17
|
||
|
|
ARM64_TLBI_ALLE3OSNXS = 18
|
||
|
|
ARM64_TLBI_ASIDE1 = 19
|
||
|
|
ARM64_TLBI_ASIDE1IS = 20
|
||
|
|
ARM64_TLBI_ASIDE1ISNXS = 21
|
||
|
|
ARM64_TLBI_ASIDE1NXS = 22
|
||
|
|
ARM64_TLBI_ASIDE1OS = 23
|
||
|
|
ARM64_TLBI_ASIDE1OSNXS = 24
|
||
|
|
ARM64_TLBI_IPAS2E1 = 25
|
||
|
|
ARM64_TLBI_IPAS2E1IS = 26
|
||
|
|
ARM64_TLBI_IPAS2E1ISNXS = 27
|
||
|
|
ARM64_TLBI_IPAS2E1NXS = 28
|
||
|
|
ARM64_TLBI_IPAS2E1OS = 29
|
||
|
|
ARM64_TLBI_IPAS2E1OSNXS = 30
|
||
|
|
ARM64_TLBI_IPAS2LE1 = 31
|
||
|
|
ARM64_TLBI_IPAS2LE1IS = 32
|
||
|
|
ARM64_TLBI_IPAS2LE1ISNXS = 33
|
||
|
|
ARM64_TLBI_IPAS2LE1NXS = 34
|
||
|
|
ARM64_TLBI_IPAS2LE1OS = 35
|
||
|
|
ARM64_TLBI_IPAS2LE1OSNXS = 36
|
||
|
|
ARM64_TLBI_PAALL = 37
|
||
|
|
ARM64_TLBI_PAALLNXS = 38
|
||
|
|
ARM64_TLBI_PAALLOS = 39
|
||
|
|
ARM64_TLBI_PAALLOSNXS = 40
|
||
|
|
ARM64_TLBI_RIPAS2E1 = 41
|
||
|
|
ARM64_TLBI_RIPAS2E1IS = 42
|
||
|
|
ARM64_TLBI_RIPAS2E1ISNXS = 43
|
||
|
|
ARM64_TLBI_RIPAS2E1NXS = 44
|
||
|
|
ARM64_TLBI_RIPAS2E1OS = 45
|
||
|
|
ARM64_TLBI_RIPAS2E1OSNXS = 46
|
||
|
|
ARM64_TLBI_RIPAS2LE1 = 47
|
||
|
|
ARM64_TLBI_RIPAS2LE1IS = 48
|
||
|
|
ARM64_TLBI_RIPAS2LE1ISNXS = 49
|
||
|
|
ARM64_TLBI_RIPAS2LE1NXS = 50
|
||
|
|
ARM64_TLBI_RIPAS2LE1OS = 51
|
||
|
|
ARM64_TLBI_RIPAS2LE1OSNXS = 52
|
||
|
|
ARM64_TLBI_RPALOS = 53
|
||
|
|
ARM64_TLBI_RPALOSNXS = 54
|
||
|
|
ARM64_TLBI_RPAOS = 55
|
||
|
|
ARM64_TLBI_RPAOSNXS = 56
|
||
|
|
ARM64_TLBI_RVAAE1 = 57
|
||
|
|
ARM64_TLBI_RVAAE1IS = 58
|
||
|
|
ARM64_TLBI_RVAAE1ISNXS = 59
|
||
|
|
ARM64_TLBI_RVAAE1NXS = 60
|
||
|
|
ARM64_TLBI_RVAAE1OS = 61
|
||
|
|
ARM64_TLBI_RVAAE1OSNXS = 62
|
||
|
|
ARM64_TLBI_RVAALE1 = 63
|
||
|
|
ARM64_TLBI_RVAALE1IS = 64
|
||
|
|
ARM64_TLBI_RVAALE1ISNXS = 65
|
||
|
|
ARM64_TLBI_RVAALE1NXS = 66
|
||
|
|
ARM64_TLBI_RVAALE1OS = 67
|
||
|
|
ARM64_TLBI_RVAALE1OSNXS = 68
|
||
|
|
ARM64_TLBI_RVAE1 = 69
|
||
|
|
ARM64_TLBI_RVAE1IS = 70
|
||
|
|
ARM64_TLBI_RVAE1ISNXS = 71
|
||
|
|
ARM64_TLBI_RVAE1NXS = 72
|
||
|
|
ARM64_TLBI_RVAE1OS = 73
|
||
|
|
ARM64_TLBI_RVAE1OSNXS = 74
|
||
|
|
ARM64_TLBI_RVAE2 = 75
|
||
|
|
ARM64_TLBI_RVAE2IS = 76
|
||
|
|
ARM64_TLBI_RVAE2ISNXS = 77
|
||
|
|
ARM64_TLBI_RVAE2NXS = 78
|
||
|
|
ARM64_TLBI_RVAE2OS = 79
|
||
|
|
ARM64_TLBI_RVAE2OSNXS = 80
|
||
|
|
ARM64_TLBI_RVAE3 = 81
|
||
|
|
ARM64_TLBI_RVAE3IS = 82
|
||
|
|
ARM64_TLBI_RVAE3ISNXS = 83
|
||
|
|
ARM64_TLBI_RVAE3NXS = 84
|
||
|
|
ARM64_TLBI_RVAE3OS = 85
|
||
|
|
ARM64_TLBI_RVAE3OSNXS = 86
|
||
|
|
ARM64_TLBI_RVALE1 = 87
|
||
|
|
ARM64_TLBI_RVALE1IS = 88
|
||
|
|
ARM64_TLBI_RVALE1ISNXS = 89
|
||
|
|
ARM64_TLBI_RVALE1NXS = 90
|
||
|
|
ARM64_TLBI_RVALE1OS = 91
|
||
|
|
ARM64_TLBI_RVALE1OSNXS = 92
|
||
|
|
ARM64_TLBI_RVALE2 = 93
|
||
|
|
ARM64_TLBI_RVALE2IS = 94
|
||
|
|
ARM64_TLBI_RVALE2ISNXS = 95
|
||
|
|
ARM64_TLBI_RVALE2NXS = 96
|
||
|
|
ARM64_TLBI_RVALE2OS = 97
|
||
|
|
ARM64_TLBI_RVALE2OSNXS = 98
|
||
|
|
ARM64_TLBI_RVALE3 = 99
|
||
|
|
ARM64_TLBI_RVALE3IS = 100
|
||
|
|
ARM64_TLBI_RVALE3ISNXS = 101
|
||
|
|
ARM64_TLBI_RVALE3NXS = 102
|
||
|
|
ARM64_TLBI_RVALE3OS = 103
|
||
|
|
ARM64_TLBI_RVALE3OSNXS = 104
|
||
|
|
ARM64_TLBI_VAAE1 = 105
|
||
|
|
ARM64_TLBI_VAAE1IS = 106
|
||
|
|
ARM64_TLBI_VAAE1ISNXS = 107
|
||
|
|
ARM64_TLBI_VAAE1NXS = 108
|
||
|
|
ARM64_TLBI_VAAE1OS = 109
|
||
|
|
ARM64_TLBI_VAAE1OSNXS = 110
|
||
|
|
ARM64_TLBI_VAALE1 = 111
|
||
|
|
ARM64_TLBI_VAALE1IS = 112
|
||
|
|
ARM64_TLBI_VAALE1ISNXS = 113
|
||
|
|
ARM64_TLBI_VAALE1NXS = 114
|
||
|
|
ARM64_TLBI_VAALE1OS = 115
|
||
|
|
ARM64_TLBI_VAALE1OSNXS = 116
|
||
|
|
ARM64_TLBI_VAE1 = 117
|
||
|
|
ARM64_TLBI_VAE1IS = 118
|
||
|
|
ARM64_TLBI_VAE1ISNXS = 119
|
||
|
|
ARM64_TLBI_VAE1NXS = 120
|
||
|
|
ARM64_TLBI_VAE1OS = 121
|
||
|
|
ARM64_TLBI_VAE1OSNXS = 122
|
||
|
|
ARM64_TLBI_VAE2 = 123
|
||
|
|
ARM64_TLBI_VAE2IS = 124
|
||
|
|
ARM64_TLBI_VAE2ISNXS = 125
|
||
|
|
ARM64_TLBI_VAE2NXS = 126
|
||
|
|
ARM64_TLBI_VAE2OS = 127
|
||
|
|
ARM64_TLBI_VAE2OSNXS = 128
|
||
|
|
ARM64_TLBI_VAE3 = 129
|
||
|
|
ARM64_TLBI_VAE3IS = 130
|
||
|
|
ARM64_TLBI_VAE3ISNXS = 131
|
||
|
|
ARM64_TLBI_VAE3NXS = 132
|
||
|
|
ARM64_TLBI_VAE3OS = 133
|
||
|
|
ARM64_TLBI_VAE3OSNXS = 134
|
||
|
|
ARM64_TLBI_VALE1 = 135
|
||
|
|
ARM64_TLBI_VALE1IS = 136
|
||
|
|
ARM64_TLBI_VALE1ISNXS = 137
|
||
|
|
ARM64_TLBI_VALE1NXS = 138
|
||
|
|
ARM64_TLBI_VALE1OS = 139
|
||
|
|
ARM64_TLBI_VALE1OSNXS = 140
|
||
|
|
ARM64_TLBI_VALE2 = 141
|
||
|
|
ARM64_TLBI_VALE2IS = 142
|
||
|
|
ARM64_TLBI_VALE2ISNXS = 143
|
||
|
|
ARM64_TLBI_VALE2NXS = 144
|
||
|
|
ARM64_TLBI_VALE2OS = 145
|
||
|
|
ARM64_TLBI_VALE2OSNXS = 146
|
||
|
|
ARM64_TLBI_VALE3 = 147
|
||
|
|
ARM64_TLBI_VALE3IS = 148
|
||
|
|
ARM64_TLBI_VALE3ISNXS = 149
|
||
|
|
ARM64_TLBI_VALE3NXS = 150
|
||
|
|
ARM64_TLBI_VALE3OS = 151
|
||
|
|
ARM64_TLBI_VALE3OSNXS = 152
|
||
|
|
ARM64_TLBI_VMALLE1 = 153
|
||
|
|
ARM64_TLBI_VMALLE1IS = 154
|
||
|
|
ARM64_TLBI_VMALLE1ISNXS = 155
|
||
|
|
ARM64_TLBI_VMALLE1NXS = 156
|
||
|
|
ARM64_TLBI_VMALLE1OS = 157
|
||
|
|
ARM64_TLBI_VMALLE1OSNXS = 158
|
||
|
|
ARM64_TLBI_VMALLS12E1 = 159
|
||
|
|
ARM64_TLBI_VMALLS12E1IS = 160
|
||
|
|
ARM64_TLBI_VMALLS12E1ISNXS = 161
|
||
|
|
ARM64_TLBI_VMALLS12E1NXS = 162
|
||
|
|
ARM64_TLBI_VMALLS12E1OS = 163
|
||
|
|
ARM64_TLBI_VMALLS12E1OSNXS = 164
|
||
|
|
ARM64_AT_S1E1R = 165
|
||
|
|
ARM64_AT_S1E2R = 166
|
||
|
|
ARM64_AT_S1E3R = 167
|
||
|
|
ARM64_AT_S1E1W = 168
|
||
|
|
ARM64_AT_S1E2W = 169
|
||
|
|
ARM64_AT_S1E3W = 170
|
||
|
|
ARM64_AT_S1E0R = 171
|
||
|
|
ARM64_AT_S1E0W = 172
|
||
|
|
ARM64_AT_S12E1R = 173
|
||
|
|
ARM64_AT_S12E1W = 174
|
||
|
|
ARM64_AT_S12E0R = 175
|
||
|
|
ARM64_AT_S12E0W = 176
|
||
|
|
ARM64_AT_S1E1RP = 177
|
||
|
|
ARM64_AT_S1E1WP = 178
|
||
|
|
ARM64_DC_CGDSW = 179
|
||
|
|
ARM64_DC_CGDVAC = 180
|
||
|
|
ARM64_DC_CGDVADP = 181
|
||
|
|
ARM64_DC_CGDVAP = 182
|
||
|
|
ARM64_DC_CGSW = 183
|
||
|
|
ARM64_DC_CGVAC = 184
|
||
|
|
ARM64_DC_CGVADP = 185
|
||
|
|
ARM64_DC_CGVAP = 186
|
||
|
|
ARM64_DC_CIGDSW = 187
|
||
|
|
ARM64_DC_CIGDVAC = 188
|
||
|
|
ARM64_DC_CIGSW = 189
|
||
|
|
ARM64_DC_CIGVAC = 190
|
||
|
|
ARM64_DC_CISW = 191
|
||
|
|
ARM64_DC_CIVAC = 192
|
||
|
|
ARM64_DC_CSW = 193
|
||
|
|
ARM64_DC_CVAC = 194
|
||
|
|
ARM64_DC_CVADP = 195
|
||
|
|
ARM64_DC_CVAP = 196
|
||
|
|
ARM64_DC_CVAU = 197
|
||
|
|
ARM64_DC_GVA = 198
|
||
|
|
ARM64_DC_GZVA = 199
|
||
|
|
ARM64_DC_IGDSW = 200
|
||
|
|
ARM64_DC_IGDVAC = 201
|
||
|
|
ARM64_DC_IGSW = 202
|
||
|
|
ARM64_DC_IGVAC = 203
|
||
|
|
ARM64_DC_ISW = 204
|
||
|
|
ARM64_DC_IVAC = 205
|
||
|
|
ARM64_DC_ZVA = 206
|
||
|
|
ARM64_IC_IALLUIS = 207
|
||
|
|
ARM64_IC_IALLU = 208
|
||
|
|
ARM64_IC_IVAU = 209
|
||
|
|
|
||
|
|
ARM64_SVCR_INVALID = 0
|
||
|
|
ARM64_SVCR_SVCRSM = 0x1
|
||
|
|
ARM64_SVCR_SVCRSMZA = 0x3
|
||
|
|
ARM64_SVCR_SVCRZA = 0x2
|
||
|
|
|
||
|
|
ARM64_PRFM_INVALID = 0
|
||
|
|
ARM64_PRFM_PLDL1KEEP = 0x00+1
|
||
|
|
ARM64_PRFM_PLDL1STRM = 0x01+1
|
||
|
|
ARM64_PRFM_PLDL2KEEP = 0x02+1
|
||
|
|
ARM64_PRFM_PLDL2STRM = 0x03+1
|
||
|
|
ARM64_PRFM_PLDL3KEEP = 0x04+1
|
||
|
|
ARM64_PRFM_PLDL3STRM = 0x05+1
|
||
|
|
ARM64_PRFM_PLIL1KEEP = 0x08+1
|
||
|
|
ARM64_PRFM_PLIL1STRM = 0x09+1
|
||
|
|
ARM64_PRFM_PLIL2KEEP = 0x0a+1
|
||
|
|
ARM64_PRFM_PLIL2STRM = 0x0b+1
|
||
|
|
ARM64_PRFM_PLIL3KEEP = 0x0c+1
|
||
|
|
ARM64_PRFM_PLIL3STRM = 0x0d+1
|
||
|
|
ARM64_PRFM_PSTL1KEEP = 0x10+1
|
||
|
|
ARM64_PRFM_PSTL1STRM = 0x11+1
|
||
|
|
ARM64_PRFM_PSTL2KEEP = 0x12+1
|
||
|
|
ARM64_PRFM_PSTL2STRM = 0x13+1
|
||
|
|
ARM64_PRFM_PSTL3KEEP = 0x14+1
|
||
|
|
ARM64_PRFM_PSTL3STRM = 0x15+1
|
||
|
|
|
||
|
|
ARM64_REG_INVALID = 0
|
||
|
|
ARM64_REG_FFR = 1
|
||
|
|
ARM64_REG_FP = 2
|
||
|
|
ARM64_REG_LR = 3
|
||
|
|
ARM64_REG_NZCV = 4
|
||
|
|
ARM64_REG_SP = 5
|
||
|
|
ARM64_REG_VG = 6
|
||
|
|
ARM64_REG_WSP = 7
|
||
|
|
ARM64_REG_WZR = 8
|
||
|
|
ARM64_REG_XZR = 9
|
||
|
|
ARM64_REG_ZA = 10
|
||
|
|
ARM64_REG_B0 = 11
|
||
|
|
ARM64_REG_B1 = 12
|
||
|
|
ARM64_REG_B2 = 13
|
||
|
|
ARM64_REG_B3 = 14
|
||
|
|
ARM64_REG_B4 = 15
|
||
|
|
ARM64_REG_B5 = 16
|
||
|
|
ARM64_REG_B6 = 17
|
||
|
|
ARM64_REG_B7 = 18
|
||
|
|
ARM64_REG_B8 = 19
|
||
|
|
ARM64_REG_B9 = 20
|
||
|
|
ARM64_REG_B10 = 21
|
||
|
|
ARM64_REG_B11 = 22
|
||
|
|
ARM64_REG_B12 = 23
|
||
|
|
ARM64_REG_B13 = 24
|
||
|
|
ARM64_REG_B14 = 25
|
||
|
|
ARM64_REG_B15 = 26
|
||
|
|
ARM64_REG_B16 = 27
|
||
|
|
ARM64_REG_B17 = 28
|
||
|
|
ARM64_REG_B18 = 29
|
||
|
|
ARM64_REG_B19 = 30
|
||
|
|
ARM64_REG_B20 = 31
|
||
|
|
ARM64_REG_B21 = 32
|
||
|
|
ARM64_REG_B22 = 33
|
||
|
|
ARM64_REG_B23 = 34
|
||
|
|
ARM64_REG_B24 = 35
|
||
|
|
ARM64_REG_B25 = 36
|
||
|
|
ARM64_REG_B26 = 37
|
||
|
|
ARM64_REG_B27 = 38
|
||
|
|
ARM64_REG_B28 = 39
|
||
|
|
ARM64_REG_B29 = 40
|
||
|
|
ARM64_REG_B30 = 41
|
||
|
|
ARM64_REG_B31 = 42
|
||
|
|
ARM64_REG_D0 = 43
|
||
|
|
ARM64_REG_D1 = 44
|
||
|
|
ARM64_REG_D2 = 45
|
||
|
|
ARM64_REG_D3 = 46
|
||
|
|
ARM64_REG_D4 = 47
|
||
|
|
ARM64_REG_D5 = 48
|
||
|
|
ARM64_REG_D6 = 49
|
||
|
|
ARM64_REG_D7 = 50
|
||
|
|
ARM64_REG_D8 = 51
|
||
|
|
ARM64_REG_D9 = 52
|
||
|
|
ARM64_REG_D10 = 53
|
||
|
|
ARM64_REG_D11 = 54
|
||
|
|
ARM64_REG_D12 = 55
|
||
|
|
ARM64_REG_D13 = 56
|
||
|
|
ARM64_REG_D14 = 57
|
||
|
|
ARM64_REG_D15 = 58
|
||
|
|
ARM64_REG_D16 = 59
|
||
|
|
ARM64_REG_D17 = 60
|
||
|
|
ARM64_REG_D18 = 61
|
||
|
|
ARM64_REG_D19 = 62
|
||
|
|
ARM64_REG_D20 = 63
|
||
|
|
ARM64_REG_D21 = 64
|
||
|
|
ARM64_REG_D22 = 65
|
||
|
|
ARM64_REG_D23 = 66
|
||
|
|
ARM64_REG_D24 = 67
|
||
|
|
ARM64_REG_D25 = 68
|
||
|
|
ARM64_REG_D26 = 69
|
||
|
|
ARM64_REG_D27 = 70
|
||
|
|
ARM64_REG_D28 = 71
|
||
|
|
ARM64_REG_D29 = 72
|
||
|
|
ARM64_REG_D30 = 73
|
||
|
|
ARM64_REG_D31 = 74
|
||
|
|
ARM64_REG_H0 = 75
|
||
|
|
ARM64_REG_H1 = 76
|
||
|
|
ARM64_REG_H2 = 77
|
||
|
|
ARM64_REG_H3 = 78
|
||
|
|
ARM64_REG_H4 = 79
|
||
|
|
ARM64_REG_H5 = 80
|
||
|
|
ARM64_REG_H6 = 81
|
||
|
|
ARM64_REG_H7 = 82
|
||
|
|
ARM64_REG_H8 = 83
|
||
|
|
ARM64_REG_H9 = 84
|
||
|
|
ARM64_REG_H10 = 85
|
||
|
|
ARM64_REG_H11 = 86
|
||
|
|
ARM64_REG_H12 = 87
|
||
|
|
ARM64_REG_H13 = 88
|
||
|
|
ARM64_REG_H14 = 89
|
||
|
|
ARM64_REG_H15 = 90
|
||
|
|
ARM64_REG_H16 = 91
|
||
|
|
ARM64_REG_H17 = 92
|
||
|
|
ARM64_REG_H18 = 93
|
||
|
|
ARM64_REG_H19 = 94
|
||
|
|
ARM64_REG_H20 = 95
|
||
|
|
ARM64_REG_H21 = 96
|
||
|
|
ARM64_REG_H22 = 97
|
||
|
|
ARM64_REG_H23 = 98
|
||
|
|
ARM64_REG_H24 = 99
|
||
|
|
ARM64_REG_H25 = 100
|
||
|
|
ARM64_REG_H26 = 101
|
||
|
|
ARM64_REG_H27 = 102
|
||
|
|
ARM64_REG_H28 = 103
|
||
|
|
ARM64_REG_H29 = 104
|
||
|
|
ARM64_REG_H30 = 105
|
||
|
|
ARM64_REG_H31 = 106
|
||
|
|
ARM64_REG_P0 = 107
|
||
|
|
ARM64_REG_P1 = 108
|
||
|
|
ARM64_REG_P2 = 109
|
||
|
|
ARM64_REG_P3 = 110
|
||
|
|
ARM64_REG_P4 = 111
|
||
|
|
ARM64_REG_P5 = 112
|
||
|
|
ARM64_REG_P6 = 113
|
||
|
|
ARM64_REG_P7 = 114
|
||
|
|
ARM64_REG_P8 = 115
|
||
|
|
ARM64_REG_P9 = 116
|
||
|
|
ARM64_REG_P10 = 117
|
||
|
|
ARM64_REG_P11 = 118
|
||
|
|
ARM64_REG_P12 = 119
|
||
|
|
ARM64_REG_P13 = 120
|
||
|
|
ARM64_REG_P14 = 121
|
||
|
|
ARM64_REG_P15 = 122
|
||
|
|
ARM64_REG_Q0 = 123
|
||
|
|
ARM64_REG_Q1 = 124
|
||
|
|
ARM64_REG_Q2 = 125
|
||
|
|
ARM64_REG_Q3 = 126
|
||
|
|
ARM64_REG_Q4 = 127
|
||
|
|
ARM64_REG_Q5 = 128
|
||
|
|
ARM64_REG_Q6 = 129
|
||
|
|
ARM64_REG_Q7 = 130
|
||
|
|
ARM64_REG_Q8 = 131
|
||
|
|
ARM64_REG_Q9 = 132
|
||
|
|
ARM64_REG_Q10 = 133
|
||
|
|
ARM64_REG_Q11 = 134
|
||
|
|
ARM64_REG_Q12 = 135
|
||
|
|
ARM64_REG_Q13 = 136
|
||
|
|
ARM64_REG_Q14 = 137
|
||
|
|
ARM64_REG_Q15 = 138
|
||
|
|
ARM64_REG_Q16 = 139
|
||
|
|
ARM64_REG_Q17 = 140
|
||
|
|
ARM64_REG_Q18 = 141
|
||
|
|
ARM64_REG_Q19 = 142
|
||
|
|
ARM64_REG_Q20 = 143
|
||
|
|
ARM64_REG_Q21 = 144
|
||
|
|
ARM64_REG_Q22 = 145
|
||
|
|
ARM64_REG_Q23 = 146
|
||
|
|
ARM64_REG_Q24 = 147
|
||
|
|
ARM64_REG_Q25 = 148
|
||
|
|
ARM64_REG_Q26 = 149
|
||
|
|
ARM64_REG_Q27 = 150
|
||
|
|
ARM64_REG_Q28 = 151
|
||
|
|
ARM64_REG_Q29 = 152
|
||
|
|
ARM64_REG_Q30 = 153
|
||
|
|
ARM64_REG_Q31 = 154
|
||
|
|
ARM64_REG_S0 = 155
|
||
|
|
ARM64_REG_S1 = 156
|
||
|
|
ARM64_REG_S2 = 157
|
||
|
|
ARM64_REG_S3 = 158
|
||
|
|
ARM64_REG_S4 = 159
|
||
|
|
ARM64_REG_S5 = 160
|
||
|
|
ARM64_REG_S6 = 161
|
||
|
|
ARM64_REG_S7 = 162
|
||
|
|
ARM64_REG_S8 = 163
|
||
|
|
ARM64_REG_S9 = 164
|
||
|
|
ARM64_REG_S10 = 165
|
||
|
|
ARM64_REG_S11 = 166
|
||
|
|
ARM64_REG_S12 = 167
|
||
|
|
ARM64_REG_S13 = 168
|
||
|
|
ARM64_REG_S14 = 169
|
||
|
|
ARM64_REG_S15 = 170
|
||
|
|
ARM64_REG_S16 = 171
|
||
|
|
ARM64_REG_S17 = 172
|
||
|
|
ARM64_REG_S18 = 173
|
||
|
|
ARM64_REG_S19 = 174
|
||
|
|
ARM64_REG_S20 = 175
|
||
|
|
ARM64_REG_S21 = 176
|
||
|
|
ARM64_REG_S22 = 177
|
||
|
|
ARM64_REG_S23 = 178
|
||
|
|
ARM64_REG_S24 = 179
|
||
|
|
ARM64_REG_S25 = 180
|
||
|
|
ARM64_REG_S26 = 181
|
||
|
|
ARM64_REG_S27 = 182
|
||
|
|
ARM64_REG_S28 = 183
|
||
|
|
ARM64_REG_S29 = 184
|
||
|
|
ARM64_REG_S30 = 185
|
||
|
|
ARM64_REG_S31 = 186
|
||
|
|
ARM64_REG_W0 = 187
|
||
|
|
ARM64_REG_W1 = 188
|
||
|
|
ARM64_REG_W2 = 189
|
||
|
|
ARM64_REG_W3 = 190
|
||
|
|
ARM64_REG_W4 = 191
|
||
|
|
ARM64_REG_W5 = 192
|
||
|
|
ARM64_REG_W6 = 193
|
||
|
|
ARM64_REG_W7 = 194
|
||
|
|
ARM64_REG_W8 = 195
|
||
|
|
ARM64_REG_W9 = 196
|
||
|
|
ARM64_REG_W10 = 197
|
||
|
|
ARM64_REG_W11 = 198
|
||
|
|
ARM64_REG_W12 = 199
|
||
|
|
ARM64_REG_W13 = 200
|
||
|
|
ARM64_REG_W14 = 201
|
||
|
|
ARM64_REG_W15 = 202
|
||
|
|
ARM64_REG_W16 = 203
|
||
|
|
ARM64_REG_W17 = 204
|
||
|
|
ARM64_REG_W18 = 205
|
||
|
|
ARM64_REG_W19 = 206
|
||
|
|
ARM64_REG_W20 = 207
|
||
|
|
ARM64_REG_W21 = 208
|
||
|
|
ARM64_REG_W22 = 209
|
||
|
|
ARM64_REG_W23 = 210
|
||
|
|
ARM64_REG_W24 = 211
|
||
|
|
ARM64_REG_W25 = 212
|
||
|
|
ARM64_REG_W26 = 213
|
||
|
|
ARM64_REG_W27 = 214
|
||
|
|
ARM64_REG_W28 = 215
|
||
|
|
ARM64_REG_W29 = 216
|
||
|
|
ARM64_REG_W30 = 217
|
||
|
|
ARM64_REG_X0 = 218
|
||
|
|
ARM64_REG_X1 = 219
|
||
|
|
ARM64_REG_X2 = 220
|
||
|
|
ARM64_REG_X3 = 221
|
||
|
|
ARM64_REG_X4 = 222
|
||
|
|
ARM64_REG_X5 = 223
|
||
|
|
ARM64_REG_X6 = 224
|
||
|
|
ARM64_REG_X7 = 225
|
||
|
|
ARM64_REG_X8 = 226
|
||
|
|
ARM64_REG_X9 = 227
|
||
|
|
ARM64_REG_X10 = 228
|
||
|
|
ARM64_REG_X11 = 229
|
||
|
|
ARM64_REG_X12 = 230
|
||
|
|
ARM64_REG_X13 = 231
|
||
|
|
ARM64_REG_X14 = 232
|
||
|
|
ARM64_REG_X15 = 233
|
||
|
|
ARM64_REG_X16 = 234
|
||
|
|
ARM64_REG_X17 = 235
|
||
|
|
ARM64_REG_X18 = 236
|
||
|
|
ARM64_REG_X19 = 237
|
||
|
|
ARM64_REG_X20 = 238
|
||
|
|
ARM64_REG_X21 = 239
|
||
|
|
ARM64_REG_X22 = 240
|
||
|
|
ARM64_REG_X23 = 241
|
||
|
|
ARM64_REG_X24 = 242
|
||
|
|
ARM64_REG_X25 = 243
|
||
|
|
ARM64_REG_X26 = 244
|
||
|
|
ARM64_REG_X27 = 245
|
||
|
|
ARM64_REG_X28 = 246
|
||
|
|
ARM64_REG_Z0 = 247
|
||
|
|
ARM64_REG_Z1 = 248
|
||
|
|
ARM64_REG_Z2 = 249
|
||
|
|
ARM64_REG_Z3 = 250
|
||
|
|
ARM64_REG_Z4 = 251
|
||
|
|
ARM64_REG_Z5 = 252
|
||
|
|
ARM64_REG_Z6 = 253
|
||
|
|
ARM64_REG_Z7 = 254
|
||
|
|
ARM64_REG_Z8 = 255
|
||
|
|
ARM64_REG_Z9 = 256
|
||
|
|
ARM64_REG_Z10 = 257
|
||
|
|
ARM64_REG_Z11 = 258
|
||
|
|
ARM64_REG_Z12 = 259
|
||
|
|
ARM64_REG_Z13 = 260
|
||
|
|
ARM64_REG_Z14 = 261
|
||
|
|
ARM64_REG_Z15 = 262
|
||
|
|
ARM64_REG_Z16 = 263
|
||
|
|
ARM64_REG_Z17 = 264
|
||
|
|
ARM64_REG_Z18 = 265
|
||
|
|
ARM64_REG_Z19 = 266
|
||
|
|
ARM64_REG_Z20 = 267
|
||
|
|
ARM64_REG_Z21 = 268
|
||
|
|
ARM64_REG_Z22 = 269
|
||
|
|
ARM64_REG_Z23 = 270
|
||
|
|
ARM64_REG_Z24 = 271
|
||
|
|
ARM64_REG_Z25 = 272
|
||
|
|
ARM64_REG_Z26 = 273
|
||
|
|
ARM64_REG_Z27 = 274
|
||
|
|
ARM64_REG_Z28 = 275
|
||
|
|
ARM64_REG_Z29 = 276
|
||
|
|
ARM64_REG_Z30 = 277
|
||
|
|
ARM64_REG_Z31 = 278
|
||
|
|
ARM64_REG_ZAB0 = 279
|
||
|
|
ARM64_REG_ZAD0 = 280
|
||
|
|
ARM64_REG_ZAD1 = 281
|
||
|
|
ARM64_REG_ZAD2 = 282
|
||
|
|
ARM64_REG_ZAD3 = 283
|
||
|
|
ARM64_REG_ZAD4 = 284
|
||
|
|
ARM64_REG_ZAD5 = 285
|
||
|
|
ARM64_REG_ZAD6 = 286
|
||
|
|
ARM64_REG_ZAD7 = 287
|
||
|
|
ARM64_REG_ZAH0 = 288
|
||
|
|
ARM64_REG_ZAH1 = 289
|
||
|
|
ARM64_REG_ZAQ0 = 290
|
||
|
|
ARM64_REG_ZAQ1 = 291
|
||
|
|
ARM64_REG_ZAQ2 = 292
|
||
|
|
ARM64_REG_ZAQ3 = 293
|
||
|
|
ARM64_REG_ZAQ4 = 294
|
||
|
|
ARM64_REG_ZAQ5 = 295
|
||
|
|
ARM64_REG_ZAQ6 = 296
|
||
|
|
ARM64_REG_ZAQ7 = 297
|
||
|
|
ARM64_REG_ZAQ8 = 298
|
||
|
|
ARM64_REG_ZAQ9 = 299
|
||
|
|
ARM64_REG_ZAQ10 = 300
|
||
|
|
ARM64_REG_ZAQ11 = 301
|
||
|
|
ARM64_REG_ZAQ12 = 302
|
||
|
|
ARM64_REG_ZAQ13 = 303
|
||
|
|
ARM64_REG_ZAQ14 = 304
|
||
|
|
ARM64_REG_ZAQ15 = 305
|
||
|
|
ARM64_REG_ZAS0 = 306
|
||
|
|
ARM64_REG_ZAS1 = 307
|
||
|
|
ARM64_REG_ZAS2 = 308
|
||
|
|
ARM64_REG_ZAS3 = 309
|
||
|
|
ARM64_REG_V0 = 310
|
||
|
|
ARM64_REG_V1 = 311
|
||
|
|
ARM64_REG_V2 = 312
|
||
|
|
ARM64_REG_V3 = 313
|
||
|
|
ARM64_REG_V4 = 314
|
||
|
|
ARM64_REG_V5 = 315
|
||
|
|
ARM64_REG_V6 = 316
|
||
|
|
ARM64_REG_V7 = 317
|
||
|
|
ARM64_REG_V8 = 318
|
||
|
|
ARM64_REG_V9 = 319
|
||
|
|
ARM64_REG_V10 = 320
|
||
|
|
ARM64_REG_V11 = 321
|
||
|
|
ARM64_REG_V12 = 322
|
||
|
|
ARM64_REG_V13 = 323
|
||
|
|
ARM64_REG_V14 = 324
|
||
|
|
ARM64_REG_V15 = 325
|
||
|
|
ARM64_REG_V16 = 326
|
||
|
|
ARM64_REG_V17 = 327
|
||
|
|
ARM64_REG_V18 = 328
|
||
|
|
ARM64_REG_V19 = 329
|
||
|
|
ARM64_REG_V20 = 330
|
||
|
|
ARM64_REG_V21 = 331
|
||
|
|
ARM64_REG_V22 = 332
|
||
|
|
ARM64_REG_V23 = 333
|
||
|
|
ARM64_REG_V24 = 334
|
||
|
|
ARM64_REG_V25 = 335
|
||
|
|
ARM64_REG_V26 = 336
|
||
|
|
ARM64_REG_V27 = 337
|
||
|
|
ARM64_REG_V28 = 338
|
||
|
|
ARM64_REG_V29 = 339
|
||
|
|
ARM64_REG_V30 = 340
|
||
|
|
ARM64_REG_V31 = 341
|
||
|
|
ARM64_REG_ENDING = 342
|
||
|
|
ARM64_REG_IP0 = ARM64_REG_X16
|
||
|
|
ARM64_REG_IP1 = ARM64_REG_X17
|
||
|
|
ARM64_REG_X29 = ARM64_REG_FP
|
||
|
|
ARM64_REG_X30 = ARM64_REG_LR
|
||
|
|
|
||
|
|
ARM64_INS_INVALID = 0
|
||
|
|
ARM64_INS_ABS = 1
|
||
|
|
ARM64_INS_ADC = 2
|
||
|
|
ARM64_INS_ADCLB = 3
|
||
|
|
ARM64_INS_ADCLT = 4
|
||
|
|
ARM64_INS_ADCS = 5
|
||
|
|
ARM64_INS_ADD = 6
|
||
|
|
ARM64_INS_ADDG = 7
|
||
|
|
ARM64_INS_ADDHA = 8
|
||
|
|
ARM64_INS_ADDHN = 9
|
||
|
|
ARM64_INS_ADDHN2 = 10
|
||
|
|
ARM64_INS_ADDHNB = 11
|
||
|
|
ARM64_INS_ADDHNT = 12
|
||
|
|
ARM64_INS_ADDP = 13
|
||
|
|
ARM64_INS_ADDPL = 14
|
||
|
|
ARM64_INS_ADDS = 15
|
||
|
|
ARM64_INS_ADDV = 16
|
||
|
|
ARM64_INS_ADDVA = 17
|
||
|
|
ARM64_INS_ADDVL = 18
|
||
|
|
ARM64_INS_ADR = 19
|
||
|
|
ARM64_INS_ADRP = 20
|
||
|
|
ARM64_INS_AESD = 21
|
||
|
|
ARM64_INS_AESE = 22
|
||
|
|
ARM64_INS_AESIMC = 23
|
||
|
|
ARM64_INS_AESMC = 24
|
||
|
|
ARM64_INS_AND = 25
|
||
|
|
ARM64_INS_ANDS = 26
|
||
|
|
ARM64_INS_ANDV = 27
|
||
|
|
ARM64_INS_ASR = 28
|
||
|
|
ARM64_INS_ASRD = 29
|
||
|
|
ARM64_INS_ASRR = 30
|
||
|
|
ARM64_INS_ASRV = 31
|
||
|
|
ARM64_INS_AUTDA = 32
|
||
|
|
ARM64_INS_AUTDB = 33
|
||
|
|
ARM64_INS_AUTDZA = 34
|
||
|
|
ARM64_INS_AUTDZB = 35
|
||
|
|
ARM64_INS_AUTIA = 36
|
||
|
|
ARM64_INS_AUTIA1716 = 37
|
||
|
|
ARM64_INS_AUTIASP = 38
|
||
|
|
ARM64_INS_AUTIAZ = 39
|
||
|
|
ARM64_INS_AUTIB = 40
|
||
|
|
ARM64_INS_AUTIB1716 = 41
|
||
|
|
ARM64_INS_AUTIBSP = 42
|
||
|
|
ARM64_INS_AUTIBZ = 43
|
||
|
|
ARM64_INS_AUTIZA = 44
|
||
|
|
ARM64_INS_AUTIZB = 45
|
||
|
|
ARM64_INS_AXFLAG = 46
|
||
|
|
ARM64_INS_B = 47
|
||
|
|
ARM64_INS_BC = 48
|
||
|
|
ARM64_INS_BCAX = 49
|
||
|
|
ARM64_INS_BDEP = 50
|
||
|
|
ARM64_INS_BEXT = 51
|
||
|
|
ARM64_INS_BFCVT = 52
|
||
|
|
ARM64_INS_BFCVTN = 53
|
||
|
|
ARM64_INS_BFCVTN2 = 54
|
||
|
|
ARM64_INS_BFCVTNT = 55
|
||
|
|
ARM64_INS_BFDOT = 56
|
||
|
|
ARM64_INS_BFM = 57
|
||
|
|
ARM64_INS_BFMLALB = 58
|
||
|
|
ARM64_INS_BFMLALT = 59
|
||
|
|
ARM64_INS_BFMMLA = 60
|
||
|
|
ARM64_INS_BFMOPA = 61
|
||
|
|
ARM64_INS_BFMOPS = 62
|
||
|
|
ARM64_INS_BGRP = 63
|
||
|
|
ARM64_INS_BIC = 64
|
||
|
|
ARM64_INS_BICS = 65
|
||
|
|
ARM64_INS_BIF = 66
|
||
|
|
ARM64_INS_BIT = 67
|
||
|
|
ARM64_INS_BL = 68
|
||
|
|
ARM64_INS_BLR = 69
|
||
|
|
ARM64_INS_BLRAA = 70
|
||
|
|
ARM64_INS_BLRAAZ = 71
|
||
|
|
ARM64_INS_BLRAB = 72
|
||
|
|
ARM64_INS_BLRABZ = 73
|
||
|
|
ARM64_INS_BR = 74
|
||
|
|
ARM64_INS_BRAA = 75
|
||
|
|
ARM64_INS_BRAAZ = 76
|
||
|
|
ARM64_INS_BRAB = 77
|
||
|
|
ARM64_INS_BRABZ = 78
|
||
|
|
ARM64_INS_BRB = 79
|
||
|
|
ARM64_INS_BRK = 80
|
||
|
|
ARM64_INS_BRKA = 81
|
||
|
|
ARM64_INS_BRKAS = 82
|
||
|
|
ARM64_INS_BRKB = 83
|
||
|
|
ARM64_INS_BRKBS = 84
|
||
|
|
ARM64_INS_BRKN = 85
|
||
|
|
ARM64_INS_BRKNS = 86
|
||
|
|
ARM64_INS_BRKPA = 87
|
||
|
|
ARM64_INS_BRKPAS = 88
|
||
|
|
ARM64_INS_BRKPB = 89
|
||
|
|
ARM64_INS_BRKPBS = 90
|
||
|
|
ARM64_INS_BSL = 91
|
||
|
|
ARM64_INS_BSL1N = 92
|
||
|
|
ARM64_INS_BSL2N = 93
|
||
|
|
ARM64_INS_BTI = 94
|
||
|
|
ARM64_INS_CADD = 95
|
||
|
|
ARM64_INS_CAS = 96
|
||
|
|
ARM64_INS_CASA = 97
|
||
|
|
ARM64_INS_CASAB = 98
|
||
|
|
ARM64_INS_CASAH = 99
|
||
|
|
ARM64_INS_CASAL = 100
|
||
|
|
ARM64_INS_CASALB = 101
|
||
|
|
ARM64_INS_CASALH = 102
|
||
|
|
ARM64_INS_CASB = 103
|
||
|
|
ARM64_INS_CASH = 104
|
||
|
|
ARM64_INS_CASL = 105
|
||
|
|
ARM64_INS_CASLB = 106
|
||
|
|
ARM64_INS_CASLH = 107
|
||
|
|
ARM64_INS_CASP = 108
|
||
|
|
ARM64_INS_CASPA = 109
|
||
|
|
ARM64_INS_CASPAL = 110
|
||
|
|
ARM64_INS_CASPL = 111
|
||
|
|
ARM64_INS_CBNZ = 112
|
||
|
|
ARM64_INS_CBZ = 113
|
||
|
|
ARM64_INS_CCMN = 114
|
||
|
|
ARM64_INS_CCMP = 115
|
||
|
|
ARM64_INS_CDOT = 116
|
||
|
|
ARM64_INS_CFINV = 117
|
||
|
|
ARM64_INS_CINC = 118
|
||
|
|
ARM64_INS_CINV = 119
|
||
|
|
ARM64_INS_CLASTA = 120
|
||
|
|
ARM64_INS_CLASTB = 121
|
||
|
|
ARM64_INS_CLREX = 122
|
||
|
|
ARM64_INS_CLS = 123
|
||
|
|
ARM64_INS_CLZ = 124
|
||
|
|
ARM64_INS_CMEQ = 125
|
||
|
|
ARM64_INS_CMGE = 126
|
||
|
|
ARM64_INS_CMGT = 127
|
||
|
|
ARM64_INS_CMHI = 128
|
||
|
|
ARM64_INS_CMHS = 129
|
||
|
|
ARM64_INS_CMLA = 130
|
||
|
|
ARM64_INS_CMLE = 131
|
||
|
|
ARM64_INS_CMLO = 132
|
||
|
|
ARM64_INS_CMLS = 133
|
||
|
|
ARM64_INS_CMLT = 134
|
||
|
|
ARM64_INS_CMN = 135
|
||
|
|
ARM64_INS_CMP = 136
|
||
|
|
ARM64_INS_CMPEQ = 137
|
||
|
|
ARM64_INS_CMPGE = 138
|
||
|
|
ARM64_INS_CMPGT = 139
|
||
|
|
ARM64_INS_CMPHI = 140
|
||
|
|
ARM64_INS_CMPHS = 141
|
||
|
|
ARM64_INS_CMPLE = 142
|
||
|
|
ARM64_INS_CMPLO = 143
|
||
|
|
ARM64_INS_CMPLS = 144
|
||
|
|
ARM64_INS_CMPLT = 145
|
||
|
|
ARM64_INS_CMPNE = 146
|
||
|
|
ARM64_INS_CMPP = 147
|
||
|
|
ARM64_INS_CMTST = 148
|
||
|
|
ARM64_INS_CNEG = 149
|
||
|
|
ARM64_INS_CNOT = 150
|
||
|
|
ARM64_INS_CNT = 151
|
||
|
|
ARM64_INS_CNTB = 152
|
||
|
|
ARM64_INS_CNTD = 153
|
||
|
|
ARM64_INS_CNTH = 154
|
||
|
|
ARM64_INS_CNTP = 155
|
||
|
|
ARM64_INS_CNTW = 156
|
||
|
|
ARM64_INS_COMPACT = 157
|
||
|
|
ARM64_INS_CPY = 158
|
||
|
|
ARM64_INS_CPYE = 159
|
||
|
|
ARM64_INS_CPYEN = 160
|
||
|
|
ARM64_INS_CPYERN = 161
|
||
|
|
ARM64_INS_CPYERT = 162
|
||
|
|
ARM64_INS_CPYERTN = 163
|
||
|
|
ARM64_INS_CPYERTRN = 164
|
||
|
|
ARM64_INS_CPYERTWN = 165
|
||
|
|
ARM64_INS_CPYET = 166
|
||
|
|
ARM64_INS_CPYETN = 167
|
||
|
|
ARM64_INS_CPYETRN = 168
|
||
|
|
ARM64_INS_CPYETWN = 169
|
||
|
|
ARM64_INS_CPYEWN = 170
|
||
|
|
ARM64_INS_CPYEWT = 171
|
||
|
|
ARM64_INS_CPYEWTN = 172
|
||
|
|
ARM64_INS_CPYEWTRN = 173
|
||
|
|
ARM64_INS_CPYEWTWN = 174
|
||
|
|
ARM64_INS_CPYFE = 175
|
||
|
|
ARM64_INS_CPYFEN = 176
|
||
|
|
ARM64_INS_CPYFERN = 177
|
||
|
|
ARM64_INS_CPYFERT = 178
|
||
|
|
ARM64_INS_CPYFERTN = 179
|
||
|
|
ARM64_INS_CPYFERTRN = 180
|
||
|
|
ARM64_INS_CPYFERTWN = 181
|
||
|
|
ARM64_INS_CPYFET = 182
|
||
|
|
ARM64_INS_CPYFETN = 183
|
||
|
|
ARM64_INS_CPYFETRN = 184
|
||
|
|
ARM64_INS_CPYFETWN = 185
|
||
|
|
ARM64_INS_CPYFEWN = 186
|
||
|
|
ARM64_INS_CPYFEWT = 187
|
||
|
|
ARM64_INS_CPYFEWTN = 188
|
||
|
|
ARM64_INS_CPYFEWTRN = 189
|
||
|
|
ARM64_INS_CPYFEWTWN = 190
|
||
|
|
ARM64_INS_CPYFM = 191
|
||
|
|
ARM64_INS_CPYFMN = 192
|
||
|
|
ARM64_INS_CPYFMRN = 193
|
||
|
|
ARM64_INS_CPYFMRT = 194
|
||
|
|
ARM64_INS_CPYFMRTN = 195
|
||
|
|
ARM64_INS_CPYFMRTRN = 196
|
||
|
|
ARM64_INS_CPYFMRTWN = 197
|
||
|
|
ARM64_INS_CPYFMT = 198
|
||
|
|
ARM64_INS_CPYFMTN = 199
|
||
|
|
ARM64_INS_CPYFMTRN = 200
|
||
|
|
ARM64_INS_CPYFMTWN = 201
|
||
|
|
ARM64_INS_CPYFMWN = 202
|
||
|
|
ARM64_INS_CPYFMWT = 203
|
||
|
|
ARM64_INS_CPYFMWTN = 204
|
||
|
|
ARM64_INS_CPYFMWTRN = 205
|
||
|
|
ARM64_INS_CPYFMWTWN = 206
|
||
|
|
ARM64_INS_CPYFP = 207
|
||
|
|
ARM64_INS_CPYFPN = 208
|
||
|
|
ARM64_INS_CPYFPRN = 209
|
||
|
|
ARM64_INS_CPYFPRT = 210
|
||
|
|
ARM64_INS_CPYFPRTN = 211
|
||
|
|
ARM64_INS_CPYFPRTRN = 212
|
||
|
|
ARM64_INS_CPYFPRTWN = 213
|
||
|
|
ARM64_INS_CPYFPT = 214
|
||
|
|
ARM64_INS_CPYFPTN = 215
|
||
|
|
ARM64_INS_CPYFPTRN = 216
|
||
|
|
ARM64_INS_CPYFPTWN = 217
|
||
|
|
ARM64_INS_CPYFPWN = 218
|
||
|
|
ARM64_INS_CPYFPWT = 219
|
||
|
|
ARM64_INS_CPYFPWTN = 220
|
||
|
|
ARM64_INS_CPYFPWTRN = 221
|
||
|
|
ARM64_INS_CPYFPWTWN = 222
|
||
|
|
ARM64_INS_CPYM = 223
|
||
|
|
ARM64_INS_CPYMN = 224
|
||
|
|
ARM64_INS_CPYMRN = 225
|
||
|
|
ARM64_INS_CPYMRT = 226
|
||
|
|
ARM64_INS_CPYMRTN = 227
|
||
|
|
ARM64_INS_CPYMRTRN = 228
|
||
|
|
ARM64_INS_CPYMRTWN = 229
|
||
|
|
ARM64_INS_CPYMT = 230
|
||
|
|
ARM64_INS_CPYMTN = 231
|
||
|
|
ARM64_INS_CPYMTRN = 232
|
||
|
|
ARM64_INS_CPYMTWN = 233
|
||
|
|
ARM64_INS_CPYMWN = 234
|
||
|
|
ARM64_INS_CPYMWT = 235
|
||
|
|
ARM64_INS_CPYMWTN = 236
|
||
|
|
ARM64_INS_CPYMWTRN = 237
|
||
|
|
ARM64_INS_CPYMWTWN = 238
|
||
|
|
ARM64_INS_CPYP = 239
|
||
|
|
ARM64_INS_CPYPN = 240
|
||
|
|
ARM64_INS_CPYPRN = 241
|
||
|
|
ARM64_INS_CPYPRT = 242
|
||
|
|
ARM64_INS_CPYPRTN = 243
|
||
|
|
ARM64_INS_CPYPRTRN = 244
|
||
|
|
ARM64_INS_CPYPRTWN = 245
|
||
|
|
ARM64_INS_CPYPT = 246
|
||
|
|
ARM64_INS_CPYPTN = 247
|
||
|
|
ARM64_INS_CPYPTRN = 248
|
||
|
|
ARM64_INS_CPYPTWN = 249
|
||
|
|
ARM64_INS_CPYPWN = 250
|
||
|
|
ARM64_INS_CPYPWT = 251
|
||
|
|
ARM64_INS_CPYPWTN = 252
|
||
|
|
ARM64_INS_CPYPWTRN = 253
|
||
|
|
ARM64_INS_CPYPWTWN = 254
|
||
|
|
ARM64_INS_CRC32B = 255
|
||
|
|
ARM64_INS_CRC32CB = 256
|
||
|
|
ARM64_INS_CRC32CH = 257
|
||
|
|
ARM64_INS_CRC32CW = 258
|
||
|
|
ARM64_INS_CRC32CX = 259
|
||
|
|
ARM64_INS_CRC32H = 260
|
||
|
|
ARM64_INS_CRC32W = 261
|
||
|
|
ARM64_INS_CRC32X = 262
|
||
|
|
ARM64_INS_CSDB = 263
|
||
|
|
ARM64_INS_CSEL = 264
|
||
|
|
ARM64_INS_CSET = 265
|
||
|
|
ARM64_INS_CSETM = 266
|
||
|
|
ARM64_INS_CSINC = 267
|
||
|
|
ARM64_INS_CSINV = 268
|
||
|
|
ARM64_INS_CSNEG = 269
|
||
|
|
ARM64_INS_CTERMEQ = 270
|
||
|
|
ARM64_INS_CTERMNE = 271
|
||
|
|
ARM64_INS_DCPS1 = 272
|
||
|
|
ARM64_INS_DCPS2 = 273
|
||
|
|
ARM64_INS_DCPS3 = 274
|
||
|
|
ARM64_INS_DECB = 275
|
||
|
|
ARM64_INS_DECD = 276
|
||
|
|
ARM64_INS_DECH = 277
|
||
|
|
ARM64_INS_DECP = 278
|
||
|
|
ARM64_INS_DECW = 279
|
||
|
|
ARM64_INS_DFB = 280
|
||
|
|
ARM64_INS_DGH = 281
|
||
|
|
ARM64_INS_DMB = 282
|
||
|
|
ARM64_INS_DRPS = 283
|
||
|
|
ARM64_INS_DSB = 284
|
||
|
|
ARM64_INS_DUP = 285
|
||
|
|
ARM64_INS_DUPM = 286
|
||
|
|
ARM64_INS_EON = 287
|
||
|
|
ARM64_INS_EOR = 288
|
||
|
|
ARM64_INS_EOR3 = 289
|
||
|
|
ARM64_INS_EORBT = 290
|
||
|
|
ARM64_INS_EORS = 291
|
||
|
|
ARM64_INS_EORTB = 292
|
||
|
|
ARM64_INS_EORV = 293
|
||
|
|
ARM64_INS_ERET = 294
|
||
|
|
ARM64_INS_ERETAA = 295
|
||
|
|
ARM64_INS_ERETAB = 296
|
||
|
|
ARM64_INS_ESB = 297
|
||
|
|
ARM64_INS_EXT = 298
|
||
|
|
ARM64_INS_EXTR = 299
|
||
|
|
ARM64_INS_FABD = 300
|
||
|
|
ARM64_INS_FABS = 301
|
||
|
|
ARM64_INS_FACGE = 302
|
||
|
|
ARM64_INS_FACGT = 303
|
||
|
|
ARM64_INS_FACLE = 304
|
||
|
|
ARM64_INS_FACLT = 305
|
||
|
|
ARM64_INS_FADD = 306
|
||
|
|
ARM64_INS_FADDA = 307
|
||
|
|
ARM64_INS_FADDP = 308
|
||
|
|
ARM64_INS_FADDV = 309
|
||
|
|
ARM64_INS_FCADD = 310
|
||
|
|
ARM64_INS_FCCMP = 311
|
||
|
|
ARM64_INS_FCCMPE = 312
|
||
|
|
ARM64_INS_FCMEQ = 313
|
||
|
|
ARM64_INS_FCMGE = 314
|
||
|
|
ARM64_INS_FCMGT = 315
|
||
|
|
ARM64_INS_FCMLA = 316
|
||
|
|
ARM64_INS_FCMLE = 317
|
||
|
|
ARM64_INS_FCMLT = 318
|
||
|
|
ARM64_INS_FCMNE = 319
|
||
|
|
ARM64_INS_FCMP = 320
|
||
|
|
ARM64_INS_FCMPE = 321
|
||
|
|
ARM64_INS_FCMUO = 322
|
||
|
|
ARM64_INS_FCPY = 323
|
||
|
|
ARM64_INS_FCSEL = 324
|
||
|
|
ARM64_INS_FCVT = 325
|
||
|
|
ARM64_INS_FCVTAS = 326
|
||
|
|
ARM64_INS_FCVTAU = 327
|
||
|
|
ARM64_INS_FCVTL = 328
|
||
|
|
ARM64_INS_FCVTL2 = 329
|
||
|
|
ARM64_INS_FCVTLT = 330
|
||
|
|
ARM64_INS_FCVTMS = 331
|
||
|
|
ARM64_INS_FCVTMU = 332
|
||
|
|
ARM64_INS_FCVTN = 333
|
||
|
|
ARM64_INS_FCVTN2 = 334
|
||
|
|
ARM64_INS_FCVTNS = 335
|
||
|
|
ARM64_INS_FCVTNT = 336
|
||
|
|
ARM64_INS_FCVTNU = 337
|
||
|
|
ARM64_INS_FCVTPS = 338
|
||
|
|
ARM64_INS_FCVTPU = 339
|
||
|
|
ARM64_INS_FCVTX = 340
|
||
|
|
ARM64_INS_FCVTXN = 341
|
||
|
|
ARM64_INS_FCVTXN2 = 342
|
||
|
|
ARM64_INS_FCVTXNT = 343
|
||
|
|
ARM64_INS_FCVTZS = 344
|
||
|
|
ARM64_INS_FCVTZU = 345
|
||
|
|
ARM64_INS_FDIV = 346
|
||
|
|
ARM64_INS_FDIVR = 347
|
||
|
|
ARM64_INS_FDUP = 348
|
||
|
|
ARM64_INS_FEXPA = 349
|
||
|
|
ARM64_INS_FJCVTZS = 350
|
||
|
|
ARM64_INS_FLOGB = 351
|
||
|
|
ARM64_INS_FMAD = 352
|
||
|
|
ARM64_INS_FMADD = 353
|
||
|
|
ARM64_INS_FMAX = 354
|
||
|
|
ARM64_INS_FMAXNM = 355
|
||
|
|
ARM64_INS_FMAXNMP = 356
|
||
|
|
ARM64_INS_FMAXNMV = 357
|
||
|
|
ARM64_INS_FMAXP = 358
|
||
|
|
ARM64_INS_FMAXV = 359
|
||
|
|
ARM64_INS_FMIN = 360
|
||
|
|
ARM64_INS_FMINNM = 361
|
||
|
|
ARM64_INS_FMINNMP = 362
|
||
|
|
ARM64_INS_FMINNMV = 363
|
||
|
|
ARM64_INS_FMINP = 364
|
||
|
|
ARM64_INS_FMINV = 365
|
||
|
|
ARM64_INS_FMLA = 366
|
||
|
|
ARM64_INS_FMLAL = 367
|
||
|
|
ARM64_INS_FMLAL2 = 368
|
||
|
|
ARM64_INS_FMLALB = 369
|
||
|
|
ARM64_INS_FMLALT = 370
|
||
|
|
ARM64_INS_FMLS = 371
|
||
|
|
ARM64_INS_FMLSL = 372
|
||
|
|
ARM64_INS_FMLSL2 = 373
|
||
|
|
ARM64_INS_FMLSLB = 374
|
||
|
|
ARM64_INS_FMLSLT = 375
|
||
|
|
ARM64_INS_FMMLA = 376
|
||
|
|
ARM64_INS_FMOPA = 377
|
||
|
|
ARM64_INS_FMOPS = 378
|
||
|
|
ARM64_INS_FMOV = 379
|
||
|
|
ARM64_INS_FMSB = 380
|
||
|
|
ARM64_INS_FMSUB = 381
|
||
|
|
ARM64_INS_FMUL = 382
|
||
|
|
ARM64_INS_FMULX = 383
|
||
|
|
ARM64_INS_FNEG = 384
|
||
|
|
ARM64_INS_FNMAD = 385
|
||
|
|
ARM64_INS_FNMADD = 386
|
||
|
|
ARM64_INS_FNMLA = 387
|
||
|
|
ARM64_INS_FNMLS = 388
|
||
|
|
ARM64_INS_FNMSB = 389
|
||
|
|
ARM64_INS_FNMSUB = 390
|
||
|
|
ARM64_INS_FNMUL = 391
|
||
|
|
ARM64_INS_FRECPE = 392
|
||
|
|
ARM64_INS_FRECPS = 393
|
||
|
|
ARM64_INS_FRECPX = 394
|
||
|
|
ARM64_INS_FRINT32X = 395
|
||
|
|
ARM64_INS_FRINT32Z = 396
|
||
|
|
ARM64_INS_FRINT64X = 397
|
||
|
|
ARM64_INS_FRINT64Z = 398
|
||
|
|
ARM64_INS_FRINTA = 399
|
||
|
|
ARM64_INS_FRINTI = 400
|
||
|
|
ARM64_INS_FRINTM = 401
|
||
|
|
ARM64_INS_FRINTN = 402
|
||
|
|
ARM64_INS_FRINTP = 403
|
||
|
|
ARM64_INS_FRINTX = 404
|
||
|
|
ARM64_INS_FRINTZ = 405
|
||
|
|
ARM64_INS_FRSQRTE = 406
|
||
|
|
ARM64_INS_FRSQRTS = 407
|
||
|
|
ARM64_INS_FSCALE = 408
|
||
|
|
ARM64_INS_FSQRT = 409
|
||
|
|
ARM64_INS_FSUB = 410
|
||
|
|
ARM64_INS_FSUBR = 411
|
||
|
|
ARM64_INS_FTMAD = 412
|
||
|
|
ARM64_INS_FTSMUL = 413
|
||
|
|
ARM64_INS_FTSSEL = 414
|
||
|
|
ARM64_INS_GMI = 415
|
||
|
|
ARM64_INS_HINT = 416
|
||
|
|
ARM64_INS_HISTCNT = 417
|
||
|
|
ARM64_INS_HISTSEG = 418
|
||
|
|
ARM64_INS_HLT = 419
|
||
|
|
ARM64_INS_HVC = 420
|
||
|
|
ARM64_INS_INCB = 421
|
||
|
|
ARM64_INS_INCD = 422
|
||
|
|
ARM64_INS_INCH = 423
|
||
|
|
ARM64_INS_INCP = 424
|
||
|
|
ARM64_INS_INCW = 425
|
||
|
|
ARM64_INS_INDEX = 426
|
||
|
|
ARM64_INS_INS = 427
|
||
|
|
ARM64_INS_INSR = 428
|
||
|
|
ARM64_INS_IRG = 429
|
||
|
|
ARM64_INS_ISB = 430
|
||
|
|
ARM64_INS_LASTA = 431
|
||
|
|
ARM64_INS_LASTB = 432
|
||
|
|
ARM64_INS_LD1 = 433
|
||
|
|
ARM64_INS_LD1B = 434
|
||
|
|
ARM64_INS_LD1D = 435
|
||
|
|
ARM64_INS_LD1H = 436
|
||
|
|
ARM64_INS_LD1Q = 437
|
||
|
|
ARM64_INS_LD1R = 438
|
||
|
|
ARM64_INS_LD1RB = 439
|
||
|
|
ARM64_INS_LD1RD = 440
|
||
|
|
ARM64_INS_LD1RH = 441
|
||
|
|
ARM64_INS_LD1ROB = 442
|
||
|
|
ARM64_INS_LD1ROD = 443
|
||
|
|
ARM64_INS_LD1ROH = 444
|
||
|
|
ARM64_INS_LD1ROW = 445
|
||
|
|
ARM64_INS_LD1RQB = 446
|
||
|
|
ARM64_INS_LD1RQD = 447
|
||
|
|
ARM64_INS_LD1RQH = 448
|
||
|
|
ARM64_INS_LD1RQW = 449
|
||
|
|
ARM64_INS_LD1RSB = 450
|
||
|
|
ARM64_INS_LD1RSH = 451
|
||
|
|
ARM64_INS_LD1RSW = 452
|
||
|
|
ARM64_INS_LD1RW = 453
|
||
|
|
ARM64_INS_LD1SB = 454
|
||
|
|
ARM64_INS_LD1SH = 455
|
||
|
|
ARM64_INS_LD1SW = 456
|
||
|
|
ARM64_INS_LD1W = 457
|
||
|
|
ARM64_INS_LD2 = 458
|
||
|
|
ARM64_INS_LD2B = 459
|
||
|
|
ARM64_INS_LD2D = 460
|
||
|
|
ARM64_INS_LD2H = 461
|
||
|
|
ARM64_INS_LD2R = 462
|
||
|
|
ARM64_INS_LD2W = 463
|
||
|
|
ARM64_INS_LD3 = 464
|
||
|
|
ARM64_INS_LD3B = 465
|
||
|
|
ARM64_INS_LD3D = 466
|
||
|
|
ARM64_INS_LD3H = 467
|
||
|
|
ARM64_INS_LD3R = 468
|
||
|
|
ARM64_INS_LD3W = 469
|
||
|
|
ARM64_INS_LD4 = 470
|
||
|
|
ARM64_INS_LD4B = 471
|
||
|
|
ARM64_INS_LD4D = 472
|
||
|
|
ARM64_INS_LD4H = 473
|
||
|
|
ARM64_INS_LD4R = 474
|
||
|
|
ARM64_INS_LD4W = 475
|
||
|
|
ARM64_INS_LD64B = 476
|
||
|
|
ARM64_INS_LDADD = 477
|
||
|
|
ARM64_INS_LDADDA = 478
|
||
|
|
ARM64_INS_LDADDAB = 479
|
||
|
|
ARM64_INS_LDADDAH = 480
|
||
|
|
ARM64_INS_LDADDAL = 481
|
||
|
|
ARM64_INS_LDADDALB = 482
|
||
|
|
ARM64_INS_LDADDALH = 483
|
||
|
|
ARM64_INS_LDADDB = 484
|
||
|
|
ARM64_INS_LDADDH = 485
|
||
|
|
ARM64_INS_LDADDL = 486
|
||
|
|
ARM64_INS_LDADDLB = 487
|
||
|
|
ARM64_INS_LDADDLH = 488
|
||
|
|
ARM64_INS_LDAPR = 489
|
||
|
|
ARM64_INS_LDAPRB = 490
|
||
|
|
ARM64_INS_LDAPRH = 491
|
||
|
|
ARM64_INS_LDAPUR = 492
|
||
|
|
ARM64_INS_LDAPURB = 493
|
||
|
|
ARM64_INS_LDAPURH = 494
|
||
|
|
ARM64_INS_LDAPURSB = 495
|
||
|
|
ARM64_INS_LDAPURSH = 496
|
||
|
|
ARM64_INS_LDAPURSW = 497
|
||
|
|
ARM64_INS_LDAR = 498
|
||
|
|
ARM64_INS_LDARB = 499
|
||
|
|
ARM64_INS_LDARH = 500
|
||
|
|
ARM64_INS_LDAXP = 501
|
||
|
|
ARM64_INS_LDAXR = 502
|
||
|
|
ARM64_INS_LDAXRB = 503
|
||
|
|
ARM64_INS_LDAXRH = 504
|
||
|
|
ARM64_INS_LDCLR = 505
|
||
|
|
ARM64_INS_LDCLRA = 506
|
||
|
|
ARM64_INS_LDCLRAB = 507
|
||
|
|
ARM64_INS_LDCLRAH = 508
|
||
|
|
ARM64_INS_LDCLRAL = 509
|
||
|
|
ARM64_INS_LDCLRALB = 510
|
||
|
|
ARM64_INS_LDCLRALH = 511
|
||
|
|
ARM64_INS_LDCLRB = 512
|
||
|
|
ARM64_INS_LDCLRH = 513
|
||
|
|
ARM64_INS_LDCLRL = 514
|
||
|
|
ARM64_INS_LDCLRLB = 515
|
||
|
|
ARM64_INS_LDCLRLH = 516
|
||
|
|
ARM64_INS_LDEOR = 517
|
||
|
|
ARM64_INS_LDEORA = 518
|
||
|
|
ARM64_INS_LDEORAB = 519
|
||
|
|
ARM64_INS_LDEORAH = 520
|
||
|
|
ARM64_INS_LDEORAL = 521
|
||
|
|
ARM64_INS_LDEORALB = 522
|
||
|
|
ARM64_INS_LDEORALH = 523
|
||
|
|
ARM64_INS_LDEORB = 524
|
||
|
|
ARM64_INS_LDEORH = 525
|
||
|
|
ARM64_INS_LDEORL = 526
|
||
|
|
ARM64_INS_LDEORLB = 527
|
||
|
|
ARM64_INS_LDEORLH = 528
|
||
|
|
ARM64_INS_LDFF1B = 529
|
||
|
|
ARM64_INS_LDFF1D = 530
|
||
|
|
ARM64_INS_LDFF1H = 531
|
||
|
|
ARM64_INS_LDFF1SB = 532
|
||
|
|
ARM64_INS_LDFF1SH = 533
|
||
|
|
ARM64_INS_LDFF1SW = 534
|
||
|
|
ARM64_INS_LDFF1W = 535
|
||
|
|
ARM64_INS_LDG = 536
|
||
|
|
ARM64_INS_LDGM = 537
|
||
|
|
ARM64_INS_LDLAR = 538
|
||
|
|
ARM64_INS_LDLARB = 539
|
||
|
|
ARM64_INS_LDLARH = 540
|
||
|
|
ARM64_INS_LDNF1B = 541
|
||
|
|
ARM64_INS_LDNF1D = 542
|
||
|
|
ARM64_INS_LDNF1H = 543
|
||
|
|
ARM64_INS_LDNF1SB = 544
|
||
|
|
ARM64_INS_LDNF1SH = 545
|
||
|
|
ARM64_INS_LDNF1SW = 546
|
||
|
|
ARM64_INS_LDNF1W = 547
|
||
|
|
ARM64_INS_LDNP = 548
|
||
|
|
ARM64_INS_LDNT1B = 549
|
||
|
|
ARM64_INS_LDNT1D = 550
|
||
|
|
ARM64_INS_LDNT1H = 551
|
||
|
|
ARM64_INS_LDNT1SB = 552
|
||
|
|
ARM64_INS_LDNT1SH = 553
|
||
|
|
ARM64_INS_LDNT1SW = 554
|
||
|
|
ARM64_INS_LDNT1W = 555
|
||
|
|
ARM64_INS_LDP = 556
|
||
|
|
ARM64_INS_LDPSW = 557
|
||
|
|
ARM64_INS_LDR = 558
|
||
|
|
ARM64_INS_LDRAA = 559
|
||
|
|
ARM64_INS_LDRAB = 560
|
||
|
|
ARM64_INS_LDRB = 561
|
||
|
|
ARM64_INS_LDRH = 562
|
||
|
|
ARM64_INS_LDRSB = 563
|
||
|
|
ARM64_INS_LDRSH = 564
|
||
|
|
ARM64_INS_LDRSW = 565
|
||
|
|
ARM64_INS_LDSET = 566
|
||
|
|
ARM64_INS_LDSETA = 567
|
||
|
|
ARM64_INS_LDSETAB = 568
|
||
|
|
ARM64_INS_LDSETAH = 569
|
||
|
|
ARM64_INS_LDSETAL = 570
|
||
|
|
ARM64_INS_LDSETALB = 571
|
||
|
|
ARM64_INS_LDSETALH = 572
|
||
|
|
ARM64_INS_LDSETB = 573
|
||
|
|
ARM64_INS_LDSETH = 574
|
||
|
|
ARM64_INS_LDSETL = 575
|
||
|
|
ARM64_INS_LDSETLB = 576
|
||
|
|
ARM64_INS_LDSETLH = 577
|
||
|
|
ARM64_INS_LDSMAX = 578
|
||
|
|
ARM64_INS_LDSMAXA = 579
|
||
|
|
ARM64_INS_LDSMAXAB = 580
|
||
|
|
ARM64_INS_LDSMAXAH = 581
|
||
|
|
ARM64_INS_LDSMAXAL = 582
|
||
|
|
ARM64_INS_LDSMAXALB = 583
|
||
|
|
ARM64_INS_LDSMAXALH = 584
|
||
|
|
ARM64_INS_LDSMAXB = 585
|
||
|
|
ARM64_INS_LDSMAXH = 586
|
||
|
|
ARM64_INS_LDSMAXL = 587
|
||
|
|
ARM64_INS_LDSMAXLB = 588
|
||
|
|
ARM64_INS_LDSMAXLH = 589
|
||
|
|
ARM64_INS_LDSMIN = 590
|
||
|
|
ARM64_INS_LDSMINA = 591
|
||
|
|
ARM64_INS_LDSMINAB = 592
|
||
|
|
ARM64_INS_LDSMINAH = 593
|
||
|
|
ARM64_INS_LDSMINAL = 594
|
||
|
|
ARM64_INS_LDSMINALB = 595
|
||
|
|
ARM64_INS_LDSMINALH = 596
|
||
|
|
ARM64_INS_LDSMINB = 597
|
||
|
|
ARM64_INS_LDSMINH = 598
|
||
|
|
ARM64_INS_LDSMINL = 599
|
||
|
|
ARM64_INS_LDSMINLB = 600
|
||
|
|
ARM64_INS_LDSMINLH = 601
|
||
|
|
ARM64_INS_LDTR = 602
|
||
|
|
ARM64_INS_LDTRB = 603
|
||
|
|
ARM64_INS_LDTRH = 604
|
||
|
|
ARM64_INS_LDTRSB = 605
|
||
|
|
ARM64_INS_LDTRSH = 606
|
||
|
|
ARM64_INS_LDTRSW = 607
|
||
|
|
ARM64_INS_LDUMAX = 608
|
||
|
|
ARM64_INS_LDUMAXA = 609
|
||
|
|
ARM64_INS_LDUMAXAB = 610
|
||
|
|
ARM64_INS_LDUMAXAH = 611
|
||
|
|
ARM64_INS_LDUMAXAL = 612
|
||
|
|
ARM64_INS_LDUMAXALB = 613
|
||
|
|
ARM64_INS_LDUMAXALH = 614
|
||
|
|
ARM64_INS_LDUMAXB = 615
|
||
|
|
ARM64_INS_LDUMAXH = 616
|
||
|
|
ARM64_INS_LDUMAXL = 617
|
||
|
|
ARM64_INS_LDUMAXLB = 618
|
||
|
|
ARM64_INS_LDUMAXLH = 619
|
||
|
|
ARM64_INS_LDUMIN = 620
|
||
|
|
ARM64_INS_LDUMINA = 621
|
||
|
|
ARM64_INS_LDUMINAB = 622
|
||
|
|
ARM64_INS_LDUMINAH = 623
|
||
|
|
ARM64_INS_LDUMINAL = 624
|
||
|
|
ARM64_INS_LDUMINALB = 625
|
||
|
|
ARM64_INS_LDUMINALH = 626
|
||
|
|
ARM64_INS_LDUMINB = 627
|
||
|
|
ARM64_INS_LDUMINH = 628
|
||
|
|
ARM64_INS_LDUMINL = 629
|
||
|
|
ARM64_INS_LDUMINLB = 630
|
||
|
|
ARM64_INS_LDUMINLH = 631
|
||
|
|
ARM64_INS_LDUR = 632
|
||
|
|
ARM64_INS_LDURB = 633
|
||
|
|
ARM64_INS_LDURH = 634
|
||
|
|
ARM64_INS_LDURSB = 635
|
||
|
|
ARM64_INS_LDURSH = 636
|
||
|
|
ARM64_INS_LDURSW = 637
|
||
|
|
ARM64_INS_LDXP = 638
|
||
|
|
ARM64_INS_LDXR = 639
|
||
|
|
ARM64_INS_LDXRB = 640
|
||
|
|
ARM64_INS_LDXRH = 641
|
||
|
|
ARM64_INS_LSL = 642
|
||
|
|
ARM64_INS_LSLR = 643
|
||
|
|
ARM64_INS_LSLV = 644
|
||
|
|
ARM64_INS_LSR = 645
|
||
|
|
ARM64_INS_LSRR = 646
|
||
|
|
ARM64_INS_LSRV = 647
|
||
|
|
ARM64_INS_MAD = 648
|
||
|
|
ARM64_INS_MADD = 649
|
||
|
|
ARM64_INS_MATCH = 650
|
||
|
|
ARM64_INS_MLA = 651
|
||
|
|
ARM64_INS_MLS = 652
|
||
|
|
ARM64_INS_MNEG = 653
|
||
|
|
ARM64_INS_MOV = 654
|
||
|
|
ARM64_INS_MOVA = 655
|
||
|
|
ARM64_INS_MOVI = 656
|
||
|
|
ARM64_INS_MOVK = 657
|
||
|
|
ARM64_INS_MOVN = 658
|
||
|
|
ARM64_INS_MOVPRFX = 659
|
||
|
|
ARM64_INS_MOVS = 660
|
||
|
|
ARM64_INS_MOVZ = 661
|
||
|
|
ARM64_INS_MRS = 662
|
||
|
|
ARM64_INS_MSB = 663
|
||
|
|
ARM64_INS_MSR = 664
|
||
|
|
ARM64_INS_MSUB = 665
|
||
|
|
ARM64_INS_MUL = 666
|
||
|
|
ARM64_INS_MVN = 667
|
||
|
|
ARM64_INS_MVNI = 668
|
||
|
|
ARM64_INS_NAND = 669
|
||
|
|
ARM64_INS_NANDS = 670
|
||
|
|
ARM64_INS_NBSL = 671
|
||
|
|
ARM64_INS_NEG = 672
|
||
|
|
ARM64_INS_NEGS = 673
|
||
|
|
ARM64_INS_NGC = 674
|
||
|
|
ARM64_INS_NGCS = 675
|
||
|
|
ARM64_INS_NMATCH = 676
|
||
|
|
ARM64_INS_NOP = 677
|
||
|
|
ARM64_INS_NOR = 678
|
||
|
|
ARM64_INS_NORS = 679
|
||
|
|
ARM64_INS_NOT = 680
|
||
|
|
ARM64_INS_NOTS = 681
|
||
|
|
ARM64_INS_ORN = 682
|
||
|
|
ARM64_INS_ORNS = 683
|
||
|
|
ARM64_INS_ORR = 684
|
||
|
|
ARM64_INS_ORRS = 685
|
||
|
|
ARM64_INS_ORV = 686
|
||
|
|
ARM64_INS_PACDA = 687
|
||
|
|
ARM64_INS_PACDB = 688
|
||
|
|
ARM64_INS_PACDZA = 689
|
||
|
|
ARM64_INS_PACDZB = 690
|
||
|
|
ARM64_INS_PACGA = 691
|
||
|
|
ARM64_INS_PACIA = 692
|
||
|
|
ARM64_INS_PACIA1716 = 693
|
||
|
|
ARM64_INS_PACIASP = 694
|
||
|
|
ARM64_INS_PACIAZ = 695
|
||
|
|
ARM64_INS_PACIB = 696
|
||
|
|
ARM64_INS_PACIB1716 = 697
|
||
|
|
ARM64_INS_PACIBSP = 698
|
||
|
|
ARM64_INS_PACIBZ = 699
|
||
|
|
ARM64_INS_PACIZA = 700
|
||
|
|
ARM64_INS_PACIZB = 701
|
||
|
|
ARM64_INS_PFALSE = 702
|
||
|
|
ARM64_INS_PFIRST = 703
|
||
|
|
ARM64_INS_PMUL = 704
|
||
|
|
ARM64_INS_PMULL = 705
|
||
|
|
ARM64_INS_PMULL2 = 706
|
||
|
|
ARM64_INS_PMULLB = 707
|
||
|
|
ARM64_INS_PMULLT = 708
|
||
|
|
ARM64_INS_PNEXT = 709
|
||
|
|
ARM64_INS_PRFB = 710
|
||
|
|
ARM64_INS_PRFD = 711
|
||
|
|
ARM64_INS_PRFH = 712
|
||
|
|
ARM64_INS_PRFM = 713
|
||
|
|
ARM64_INS_PRFUM = 714
|
||
|
|
ARM64_INS_PRFW = 715
|
||
|
|
ARM64_INS_PSB = 716
|
||
|
|
ARM64_INS_PSEL = 717
|
||
|
|
ARM64_INS_PSSBB = 718
|
||
|
|
ARM64_INS_PTEST = 719
|
||
|
|
ARM64_INS_PTRUE = 720
|
||
|
|
ARM64_INS_PTRUES = 721
|
||
|
|
ARM64_INS_PUNPKHI = 722
|
||
|
|
ARM64_INS_PUNPKLO = 723
|
||
|
|
ARM64_INS_RADDHN = 724
|
||
|
|
ARM64_INS_RADDHN2 = 725
|
||
|
|
ARM64_INS_RADDHNB = 726
|
||
|
|
ARM64_INS_RADDHNT = 727
|
||
|
|
ARM64_INS_RAX1 = 728
|
||
|
|
ARM64_INS_RBIT = 729
|
||
|
|
ARM64_INS_RDFFR = 730
|
||
|
|
ARM64_INS_RDFFRS = 731
|
||
|
|
ARM64_INS_RDVL = 732
|
||
|
|
ARM64_INS_RET = 733
|
||
|
|
ARM64_INS_RETAA = 734
|
||
|
|
ARM64_INS_RETAB = 735
|
||
|
|
ARM64_INS_REV = 736
|
||
|
|
ARM64_INS_REV16 = 737
|
||
|
|
ARM64_INS_REV32 = 738
|
||
|
|
ARM64_INS_REV64 = 739
|
||
|
|
ARM64_INS_REVB = 740
|
||
|
|
ARM64_INS_REVD = 741
|
||
|
|
ARM64_INS_REVH = 742
|
||
|
|
ARM64_INS_REVW = 743
|
||
|
|
ARM64_INS_RMIF = 744
|
||
|
|
ARM64_INS_ROR = 745
|
||
|
|
ARM64_INS_RORV = 746
|
||
|
|
ARM64_INS_RSHRN = 747
|
||
|
|
ARM64_INS_RSHRN2 = 748
|
||
|
|
ARM64_INS_RSHRNB = 749
|
||
|
|
ARM64_INS_RSHRNT = 750
|
||
|
|
ARM64_INS_RSUBHN = 751
|
||
|
|
ARM64_INS_RSUBHN2 = 752
|
||
|
|
ARM64_INS_RSUBHNB = 753
|
||
|
|
ARM64_INS_RSUBHNT = 754
|
||
|
|
ARM64_INS_SABA = 755
|
||
|
|
ARM64_INS_SABAL = 756
|
||
|
|
ARM64_INS_SABAL2 = 757
|
||
|
|
ARM64_INS_SABALB = 758
|
||
|
|
ARM64_INS_SABALT = 759
|
||
|
|
ARM64_INS_SABD = 760
|
||
|
|
ARM64_INS_SABDL = 761
|
||
|
|
ARM64_INS_SABDL2 = 762
|
||
|
|
ARM64_INS_SABDLB = 763
|
||
|
|
ARM64_INS_SABDLT = 764
|
||
|
|
ARM64_INS_SADALP = 765
|
||
|
|
ARM64_INS_SADDL = 766
|
||
|
|
ARM64_INS_SADDL2 = 767
|
||
|
|
ARM64_INS_SADDLB = 768
|
||
|
|
ARM64_INS_SADDLBT = 769
|
||
|
|
ARM64_INS_SADDLP = 770
|
||
|
|
ARM64_INS_SADDLT = 771
|
||
|
|
ARM64_INS_SADDLV = 772
|
||
|
|
ARM64_INS_SADDV = 773
|
||
|
|
ARM64_INS_SADDW = 774
|
||
|
|
ARM64_INS_SADDW2 = 775
|
||
|
|
ARM64_INS_SADDWB = 776
|
||
|
|
ARM64_INS_SADDWT = 777
|
||
|
|
ARM64_INS_SB = 778
|
||
|
|
ARM64_INS_SBC = 779
|
||
|
|
ARM64_INS_SBCLB = 780
|
||
|
|
ARM64_INS_SBCLT = 781
|
||
|
|
ARM64_INS_SBCS = 782
|
||
|
|
ARM64_INS_SBFM = 783
|
||
|
|
ARM64_INS_SCLAMP = 784
|
||
|
|
ARM64_INS_SCVTF = 785
|
||
|
|
ARM64_INS_SDIV = 786
|
||
|
|
ARM64_INS_SDIVR = 787
|
||
|
|
ARM64_INS_SDOT = 788
|
||
|
|
ARM64_INS_SEL = 789
|
||
|
|
ARM64_INS_SETE = 790
|
||
|
|
ARM64_INS_SETEN = 791
|
||
|
|
ARM64_INS_SETET = 792
|
||
|
|
ARM64_INS_SETETN = 793
|
||
|
|
ARM64_INS_SETF16 = 794
|
||
|
|
ARM64_INS_SETF8 = 795
|
||
|
|
ARM64_INS_SETFFR = 796
|
||
|
|
ARM64_INS_SETGE = 797
|
||
|
|
ARM64_INS_SETGEN = 798
|
||
|
|
ARM64_INS_SETGET = 799
|
||
|
|
ARM64_INS_SETGETN = 800
|
||
|
|
ARM64_INS_SETGM = 801
|
||
|
|
ARM64_INS_SETGMN = 802
|
||
|
|
ARM64_INS_SETGMT = 803
|
||
|
|
ARM64_INS_SETGMTN = 804
|
||
|
|
ARM64_INS_SETGP = 805
|
||
|
|
ARM64_INS_SETGPN = 806
|
||
|
|
ARM64_INS_SETGPT = 807
|
||
|
|
ARM64_INS_SETGPTN = 808
|
||
|
|
ARM64_INS_SETM = 809
|
||
|
|
ARM64_INS_SETMN = 810
|
||
|
|
ARM64_INS_SETMT = 811
|
||
|
|
ARM64_INS_SETMTN = 812
|
||
|
|
ARM64_INS_SETP = 813
|
||
|
|
ARM64_INS_SETPN = 814
|
||
|
|
ARM64_INS_SETPT = 815
|
||
|
|
ARM64_INS_SETPTN = 816
|
||
|
|
ARM64_INS_SEV = 817
|
||
|
|
ARM64_INS_SEVL = 818
|
||
|
|
ARM64_INS_SHA1C = 819
|
||
|
|
ARM64_INS_SHA1H = 820
|
||
|
|
ARM64_INS_SHA1M = 821
|
||
|
|
ARM64_INS_SHA1P = 822
|
||
|
|
ARM64_INS_SHA1SU0 = 823
|
||
|
|
ARM64_INS_SHA1SU1 = 824
|
||
|
|
ARM64_INS_SHA256H = 825
|
||
|
|
ARM64_INS_SHA256H2 = 826
|
||
|
|
ARM64_INS_SHA256SU0 = 827
|
||
|
|
ARM64_INS_SHA256SU1 = 828
|
||
|
|
ARM64_INS_SHA512H = 829
|
||
|
|
ARM64_INS_SHA512H2 = 830
|
||
|
|
ARM64_INS_SHA512SU0 = 831
|
||
|
|
ARM64_INS_SHA512SU1 = 832
|
||
|
|
ARM64_INS_SHADD = 833
|
||
|
|
ARM64_INS_SHL = 834
|
||
|
|
ARM64_INS_SHLL = 835
|
||
|
|
ARM64_INS_SHLL2 = 836
|
||
|
|
ARM64_INS_SHRN = 837
|
||
|
|
ARM64_INS_SHRN2 = 838
|
||
|
|
ARM64_INS_SHRNB = 839
|
||
|
|
ARM64_INS_SHRNT = 840
|
||
|
|
ARM64_INS_SHSUB = 841
|
||
|
|
ARM64_INS_SHSUBR = 842
|
||
|
|
ARM64_INS_SLI = 843
|
||
|
|
ARM64_INS_SM3PARTW1 = 844
|
||
|
|
ARM64_INS_SM3PARTW2 = 845
|
||
|
|
ARM64_INS_SM3SS1 = 846
|
||
|
|
ARM64_INS_SM3TT1A = 847
|
||
|
|
ARM64_INS_SM3TT1B = 848
|
||
|
|
ARM64_INS_SM3TT2A = 849
|
||
|
|
ARM64_INS_SM3TT2B = 850
|
||
|
|
ARM64_INS_SM4E = 851
|
||
|
|
ARM64_INS_SM4EKEY = 852
|
||
|
|
ARM64_INS_SMADDL = 853
|
||
|
|
ARM64_INS_SMAX = 854
|
||
|
|
ARM64_INS_SMAXP = 855
|
||
|
|
ARM64_INS_SMAXV = 856
|
||
|
|
ARM64_INS_SMC = 857
|
||
|
|
ARM64_INS_SMIN = 858
|
||
|
|
ARM64_INS_SMINP = 859
|
||
|
|
ARM64_INS_SMINV = 860
|
||
|
|
ARM64_INS_SMLAL = 861
|
||
|
|
ARM64_INS_SMLAL2 = 862
|
||
|
|
ARM64_INS_SMLALB = 863
|
||
|
|
ARM64_INS_SMLALT = 864
|
||
|
|
ARM64_INS_SMLSL = 865
|
||
|
|
ARM64_INS_SMLSL2 = 866
|
||
|
|
ARM64_INS_SMLSLB = 867
|
||
|
|
ARM64_INS_SMLSLT = 868
|
||
|
|
ARM64_INS_SMMLA = 869
|
||
|
|
ARM64_INS_SMNEGL = 870
|
||
|
|
ARM64_INS_SMOPA = 871
|
||
|
|
ARM64_INS_SMOPS = 872
|
||
|
|
ARM64_INS_SMOV = 873
|
||
|
|
ARM64_INS_SMSTART = 874
|
||
|
|
ARM64_INS_SMSTOP = 875
|
||
|
|
ARM64_INS_SMSUBL = 876
|
||
|
|
ARM64_INS_SMULH = 877
|
||
|
|
ARM64_INS_SMULL = 878
|
||
|
|
ARM64_INS_SMULL2 = 879
|
||
|
|
ARM64_INS_SMULLB = 880
|
||
|
|
ARM64_INS_SMULLT = 881
|
||
|
|
ARM64_INS_SPLICE = 882
|
||
|
|
ARM64_INS_SQABS = 883
|
||
|
|
ARM64_INS_SQADD = 884
|
||
|
|
ARM64_INS_SQCADD = 885
|
||
|
|
ARM64_INS_SQDECB = 886
|
||
|
|
ARM64_INS_SQDECD = 887
|
||
|
|
ARM64_INS_SQDECH = 888
|
||
|
|
ARM64_INS_SQDECP = 889
|
||
|
|
ARM64_INS_SQDECW = 890
|
||
|
|
ARM64_INS_SQDMLAL = 891
|
||
|
|
ARM64_INS_SQDMLAL2 = 892
|
||
|
|
ARM64_INS_SQDMLALB = 893
|
||
|
|
ARM64_INS_SQDMLALBT = 894
|
||
|
|
ARM64_INS_SQDMLALT = 895
|
||
|
|
ARM64_INS_SQDMLSL = 896
|
||
|
|
ARM64_INS_SQDMLSL2 = 897
|
||
|
|
ARM64_INS_SQDMLSLB = 898
|
||
|
|
ARM64_INS_SQDMLSLBT = 899
|
||
|
|
ARM64_INS_SQDMLSLT = 900
|
||
|
|
ARM64_INS_SQDMULH = 901
|
||
|
|
ARM64_INS_SQDMULL = 902
|
||
|
|
ARM64_INS_SQDMULL2 = 903
|
||
|
|
ARM64_INS_SQDMULLB = 904
|
||
|
|
ARM64_INS_SQDMULLT = 905
|
||
|
|
ARM64_INS_SQINCB = 906
|
||
|
|
ARM64_INS_SQINCD = 907
|
||
|
|
ARM64_INS_SQINCH = 908
|
||
|
|
ARM64_INS_SQINCP = 909
|
||
|
|
ARM64_INS_SQINCW = 910
|
||
|
|
ARM64_INS_SQNEG = 911
|
||
|
|
ARM64_INS_SQRDCMLAH = 912
|
||
|
|
ARM64_INS_SQRDMLAH = 913
|
||
|
|
ARM64_INS_SQRDMLSH = 914
|
||
|
|
ARM64_INS_SQRDMULH = 915
|
||
|
|
ARM64_INS_SQRSHL = 916
|
||
|
|
ARM64_INS_SQRSHLR = 917
|
||
|
|
ARM64_INS_SQRSHRN = 918
|
||
|
|
ARM64_INS_SQRSHRN2 = 919
|
||
|
|
ARM64_INS_SQRSHRNB = 920
|
||
|
|
ARM64_INS_SQRSHRNT = 921
|
||
|
|
ARM64_INS_SQRSHRUN = 922
|
||
|
|
ARM64_INS_SQRSHRUN2 = 923
|
||
|
|
ARM64_INS_SQRSHRUNB = 924
|
||
|
|
ARM64_INS_SQRSHRUNT = 925
|
||
|
|
ARM64_INS_SQSHL = 926
|
||
|
|
ARM64_INS_SQSHLR = 927
|
||
|
|
ARM64_INS_SQSHLU = 928
|
||
|
|
ARM64_INS_SQSHRN = 929
|
||
|
|
ARM64_INS_SQSHRN2 = 930
|
||
|
|
ARM64_INS_SQSHRNB = 931
|
||
|
|
ARM64_INS_SQSHRNT = 932
|
||
|
|
ARM64_INS_SQSHRUN = 933
|
||
|
|
ARM64_INS_SQSHRUN2 = 934
|
||
|
|
ARM64_INS_SQSHRUNB = 935
|
||
|
|
ARM64_INS_SQSHRUNT = 936
|
||
|
|
ARM64_INS_SQSUB = 937
|
||
|
|
ARM64_INS_SQSUBR = 938
|
||
|
|
ARM64_INS_SQXTN = 939
|
||
|
|
ARM64_INS_SQXTN2 = 940
|
||
|
|
ARM64_INS_SQXTNB = 941
|
||
|
|
ARM64_INS_SQXTNT = 942
|
||
|
|
ARM64_INS_SQXTUN = 943
|
||
|
|
ARM64_INS_SQXTUN2 = 944
|
||
|
|
ARM64_INS_SQXTUNB = 945
|
||
|
|
ARM64_INS_SQXTUNT = 946
|
||
|
|
ARM64_INS_SRHADD = 947
|
||
|
|
ARM64_INS_SRI = 948
|
||
|
|
ARM64_INS_SRSHL = 949
|
||
|
|
ARM64_INS_SRSHLR = 950
|
||
|
|
ARM64_INS_SRSHR = 951
|
||
|
|
ARM64_INS_SRSRA = 952
|
||
|
|
ARM64_INS_SSBB = 953
|
||
|
|
ARM64_INS_SSHL = 954
|
||
|
|
ARM64_INS_SSHLL = 955
|
||
|
|
ARM64_INS_SSHLL2 = 956
|
||
|
|
ARM64_INS_SSHLLB = 957
|
||
|
|
ARM64_INS_SSHLLT = 958
|
||
|
|
ARM64_INS_SSHR = 959
|
||
|
|
ARM64_INS_SSRA = 960
|
||
|
|
ARM64_INS_SSUBL = 961
|
||
|
|
ARM64_INS_SSUBL2 = 962
|
||
|
|
ARM64_INS_SSUBLB = 963
|
||
|
|
ARM64_INS_SSUBLBT = 964
|
||
|
|
ARM64_INS_SSUBLT = 965
|
||
|
|
ARM64_INS_SSUBLTB = 966
|
||
|
|
ARM64_INS_SSUBW = 967
|
||
|
|
ARM64_INS_SSUBW2 = 968
|
||
|
|
ARM64_INS_SSUBWB = 969
|
||
|
|
ARM64_INS_SSUBWT = 970
|
||
|
|
ARM64_INS_ST1 = 971
|
||
|
|
ARM64_INS_ST1B = 972
|
||
|
|
ARM64_INS_ST1D = 973
|
||
|
|
ARM64_INS_ST1H = 974
|
||
|
|
ARM64_INS_ST1Q = 975
|
||
|
|
ARM64_INS_ST1W = 976
|
||
|
|
ARM64_INS_ST2 = 977
|
||
|
|
ARM64_INS_ST2B = 978
|
||
|
|
ARM64_INS_ST2D = 979
|
||
|
|
ARM64_INS_ST2G = 980
|
||
|
|
ARM64_INS_ST2H = 981
|
||
|
|
ARM64_INS_ST2W = 982
|
||
|
|
ARM64_INS_ST3 = 983
|
||
|
|
ARM64_INS_ST3B = 984
|
||
|
|
ARM64_INS_ST3D = 985
|
||
|
|
ARM64_INS_ST3H = 986
|
||
|
|
ARM64_INS_ST3W = 987
|
||
|
|
ARM64_INS_ST4 = 988
|
||
|
|
ARM64_INS_ST4B = 989
|
||
|
|
ARM64_INS_ST4D = 990
|
||
|
|
ARM64_INS_ST4H = 991
|
||
|
|
ARM64_INS_ST4W = 992
|
||
|
|
ARM64_INS_ST64B = 993
|
||
|
|
ARM64_INS_ST64BV = 994
|
||
|
|
ARM64_INS_ST64BV0 = 995
|
||
|
|
ARM64_INS_STADD = 996
|
||
|
|
ARM64_INS_STADDB = 997
|
||
|
|
ARM64_INS_STADDH = 998
|
||
|
|
ARM64_INS_STADDL = 999
|
||
|
|
ARM64_INS_STADDLB = 1000
|
||
|
|
ARM64_INS_STADDLH = 1001
|
||
|
|
ARM64_INS_STCLR = 1002
|
||
|
|
ARM64_INS_STCLRB = 1003
|
||
|
|
ARM64_INS_STCLRH = 1004
|
||
|
|
ARM64_INS_STCLRL = 1005
|
||
|
|
ARM64_INS_STCLRLB = 1006
|
||
|
|
ARM64_INS_STCLRLH = 1007
|
||
|
|
ARM64_INS_STEOR = 1008
|
||
|
|
ARM64_INS_STEORB = 1009
|
||
|
|
ARM64_INS_STEORH = 1010
|
||
|
|
ARM64_INS_STEORL = 1011
|
||
|
|
ARM64_INS_STEORLB = 1012
|
||
|
|
ARM64_INS_STEORLH = 1013
|
||
|
|
ARM64_INS_STG = 1014
|
||
|
|
ARM64_INS_STGM = 1015
|
||
|
|
ARM64_INS_STGP = 1016
|
||
|
|
ARM64_INS_STLLR = 1017
|
||
|
|
ARM64_INS_STLLRB = 1018
|
||
|
|
ARM64_INS_STLLRH = 1019
|
||
|
|
ARM64_INS_STLR = 1020
|
||
|
|
ARM64_INS_STLRB = 1021
|
||
|
|
ARM64_INS_STLRH = 1022
|
||
|
|
ARM64_INS_STLUR = 1023
|
||
|
|
ARM64_INS_STLURB = 1024
|
||
|
|
ARM64_INS_STLURH = 1025
|
||
|
|
ARM64_INS_STLXP = 1026
|
||
|
|
ARM64_INS_STLXR = 1027
|
||
|
|
ARM64_INS_STLXRB = 1028
|
||
|
|
ARM64_INS_STLXRH = 1029
|
||
|
|
ARM64_INS_STNP = 1030
|
||
|
|
ARM64_INS_STNT1B = 1031
|
||
|
|
ARM64_INS_STNT1D = 1032
|
||
|
|
ARM64_INS_STNT1H = 1033
|
||
|
|
ARM64_INS_STNT1W = 1034
|
||
|
|
ARM64_INS_STP = 1035
|
||
|
|
ARM64_INS_STR = 1036
|
||
|
|
ARM64_INS_STRB = 1037
|
||
|
|
ARM64_INS_STRH = 1038
|
||
|
|
ARM64_INS_STSET = 1039
|
||
|
|
ARM64_INS_STSETB = 1040
|
||
|
|
ARM64_INS_STSETH = 1041
|
||
|
|
ARM64_INS_STSETL = 1042
|
||
|
|
ARM64_INS_STSETLB = 1043
|
||
|
|
ARM64_INS_STSETLH = 1044
|
||
|
|
ARM64_INS_STSMAX = 1045
|
||
|
|
ARM64_INS_STSMAXB = 1046
|
||
|
|
ARM64_INS_STSMAXH = 1047
|
||
|
|
ARM64_INS_STSMAXL = 1048
|
||
|
|
ARM64_INS_STSMAXLB = 1049
|
||
|
|
ARM64_INS_STSMAXLH = 1050
|
||
|
|
ARM64_INS_STSMIN = 1051
|
||
|
|
ARM64_INS_STSMINB = 1052
|
||
|
|
ARM64_INS_STSMINH = 1053
|
||
|
|
ARM64_INS_STSMINL = 1054
|
||
|
|
ARM64_INS_STSMINLB = 1055
|
||
|
|
ARM64_INS_STSMINLH = 1056
|
||
|
|
ARM64_INS_STTR = 1057
|
||
|
|
ARM64_INS_STTRB = 1058
|
||
|
|
ARM64_INS_STTRH = 1059
|
||
|
|
ARM64_INS_STUMAX = 1060
|
||
|
|
ARM64_INS_STUMAXB = 1061
|
||
|
|
ARM64_INS_STUMAXH = 1062
|
||
|
|
ARM64_INS_STUMAXL = 1063
|
||
|
|
ARM64_INS_STUMAXLB = 1064
|
||
|
|
ARM64_INS_STUMAXLH = 1065
|
||
|
|
ARM64_INS_STUMIN = 1066
|
||
|
|
ARM64_INS_STUMINB = 1067
|
||
|
|
ARM64_INS_STUMINH = 1068
|
||
|
|
ARM64_INS_STUMINL = 1069
|
||
|
|
ARM64_INS_STUMINLB = 1070
|
||
|
|
ARM64_INS_STUMINLH = 1071
|
||
|
|
ARM64_INS_STUR = 1072
|
||
|
|
ARM64_INS_STURB = 1073
|
||
|
|
ARM64_INS_STURH = 1074
|
||
|
|
ARM64_INS_STXP = 1075
|
||
|
|
ARM64_INS_STXR = 1076
|
||
|
|
ARM64_INS_STXRB = 1077
|
||
|
|
ARM64_INS_STXRH = 1078
|
||
|
|
ARM64_INS_STZ2G = 1079
|
||
|
|
ARM64_INS_STZG = 1080
|
||
|
|
ARM64_INS_STZGM = 1081
|
||
|
|
ARM64_INS_SUB = 1082
|
||
|
|
ARM64_INS_SUBG = 1083
|
||
|
|
ARM64_INS_SUBHN = 1084
|
||
|
|
ARM64_INS_SUBHN2 = 1085
|
||
|
|
ARM64_INS_SUBHNB = 1086
|
||
|
|
ARM64_INS_SUBHNT = 1087
|
||
|
|
ARM64_INS_SUBP = 1088
|
||
|
|
ARM64_INS_SUBPS = 1089
|
||
|
|
ARM64_INS_SUBR = 1090
|
||
|
|
ARM64_INS_SUBS = 1091
|
||
|
|
ARM64_INS_SUDOT = 1092
|
||
|
|
ARM64_INS_SUMOPA = 1093
|
||
|
|
ARM64_INS_SUMOPS = 1094
|
||
|
|
ARM64_INS_SUNPKHI = 1095
|
||
|
|
ARM64_INS_SUNPKLO = 1096
|
||
|
|
ARM64_INS_SUQADD = 1097
|
||
|
|
ARM64_INS_SVC = 1098
|
||
|
|
ARM64_INS_SWP = 1099
|
||
|
|
ARM64_INS_SWPA = 1100
|
||
|
|
ARM64_INS_SWPAB = 1101
|
||
|
|
ARM64_INS_SWPAH = 1102
|
||
|
|
ARM64_INS_SWPAL = 1103
|
||
|
|
ARM64_INS_SWPALB = 1104
|
||
|
|
ARM64_INS_SWPALH = 1105
|
||
|
|
ARM64_INS_SWPB = 1106
|
||
|
|
ARM64_INS_SWPH = 1107
|
||
|
|
ARM64_INS_SWPL = 1108
|
||
|
|
ARM64_INS_SWPLB = 1109
|
||
|
|
ARM64_INS_SWPLH = 1110
|
||
|
|
ARM64_INS_SXTB = 1111
|
||
|
|
ARM64_INS_SXTH = 1112
|
||
|
|
ARM64_INS_SXTL = 1113
|
||
|
|
ARM64_INS_SXTL2 = 1114
|
||
|
|
ARM64_INS_SXTW = 1115
|
||
|
|
ARM64_INS_SYS = 1116
|
||
|
|
ARM64_INS_SYSL = 1117
|
||
|
|
ARM64_INS_TBL = 1118
|
||
|
|
ARM64_INS_TBNZ = 1119
|
||
|
|
ARM64_INS_TBX = 1120
|
||
|
|
ARM64_INS_TBZ = 1121
|
||
|
|
ARM64_INS_TCANCEL = 1122
|
||
|
|
ARM64_INS_TCOMMIT = 1123
|
||
|
|
ARM64_INS_TRN1 = 1124
|
||
|
|
ARM64_INS_TRN2 = 1125
|
||
|
|
ARM64_INS_TSB = 1126
|
||
|
|
ARM64_INS_TST = 1127
|
||
|
|
ARM64_INS_TSTART = 1128
|
||
|
|
ARM64_INS_TTEST = 1129
|
||
|
|
ARM64_INS_UABA = 1130
|
||
|
|
ARM64_INS_UABAL = 1131
|
||
|
|
ARM64_INS_UABAL2 = 1132
|
||
|
|
ARM64_INS_UABALB = 1133
|
||
|
|
ARM64_INS_UABALT = 1134
|
||
|
|
ARM64_INS_UABD = 1135
|
||
|
|
ARM64_INS_UABDL = 1136
|
||
|
|
ARM64_INS_UABDL2 = 1137
|
||
|
|
ARM64_INS_UABDLB = 1138
|
||
|
|
ARM64_INS_UABDLT = 1139
|
||
|
|
ARM64_INS_UADALP = 1140
|
||
|
|
ARM64_INS_UADDL = 1141
|
||
|
|
ARM64_INS_UADDL2 = 1142
|
||
|
|
ARM64_INS_UADDLB = 1143
|
||
|
|
ARM64_INS_UADDLP = 1144
|
||
|
|
ARM64_INS_UADDLT = 1145
|
||
|
|
ARM64_INS_UADDLV = 1146
|
||
|
|
ARM64_INS_UADDV = 1147
|
||
|
|
ARM64_INS_UADDW = 1148
|
||
|
|
ARM64_INS_UADDW2 = 1149
|
||
|
|
ARM64_INS_UADDWB = 1150
|
||
|
|
ARM64_INS_UADDWT = 1151
|
||
|
|
ARM64_INS_UBFM = 1152
|
||
|
|
ARM64_INS_UCLAMP = 1153
|
||
|
|
ARM64_INS_UCVTF = 1154
|
||
|
|
ARM64_INS_UDF = 1155
|
||
|
|
ARM64_INS_UDIV = 1156
|
||
|
|
ARM64_INS_UDIVR = 1157
|
||
|
|
ARM64_INS_UDOT = 1158
|
||
|
|
ARM64_INS_UHADD = 1159
|
||
|
|
ARM64_INS_UHSUB = 1160
|
||
|
|
ARM64_INS_UHSUBR = 1161
|
||
|
|
ARM64_INS_UMADDL = 1162
|
||
|
|
ARM64_INS_UMAX = 1163
|
||
|
|
ARM64_INS_UMAXP = 1164
|
||
|
|
ARM64_INS_UMAXV = 1165
|
||
|
|
ARM64_INS_UMIN = 1166
|
||
|
|
ARM64_INS_UMINP = 1167
|
||
|
|
ARM64_INS_UMINV = 1168
|
||
|
|
ARM64_INS_UMLAL = 1169
|
||
|
|
ARM64_INS_UMLAL2 = 1170
|
||
|
|
ARM64_INS_UMLALB = 1171
|
||
|
|
ARM64_INS_UMLALT = 1172
|
||
|
|
ARM64_INS_UMLSL = 1173
|
||
|
|
ARM64_INS_UMLSL2 = 1174
|
||
|
|
ARM64_INS_UMLSLB = 1175
|
||
|
|
ARM64_INS_UMLSLT = 1176
|
||
|
|
ARM64_INS_UMMLA = 1177
|
||
|
|
ARM64_INS_UMNEGL = 1178
|
||
|
|
ARM64_INS_UMOPA = 1179
|
||
|
|
ARM64_INS_UMOPS = 1180
|
||
|
|
ARM64_INS_UMOV = 1181
|
||
|
|
ARM64_INS_UMSUBL = 1182
|
||
|
|
ARM64_INS_UMULH = 1183
|
||
|
|
ARM64_INS_UMULL = 1184
|
||
|
|
ARM64_INS_UMULL2 = 1185
|
||
|
|
ARM64_INS_UMULLB = 1186
|
||
|
|
ARM64_INS_UMULLT = 1187
|
||
|
|
ARM64_INS_UQADD = 1188
|
||
|
|
ARM64_INS_UQDECB = 1189
|
||
|
|
ARM64_INS_UQDECD = 1190
|
||
|
|
ARM64_INS_UQDECH = 1191
|
||
|
|
ARM64_INS_UQDECP = 1192
|
||
|
|
ARM64_INS_UQDECW = 1193
|
||
|
|
ARM64_INS_UQINCB = 1194
|
||
|
|
ARM64_INS_UQINCD = 1195
|
||
|
|
ARM64_INS_UQINCH = 1196
|
||
|
|
ARM64_INS_UQINCP = 1197
|
||
|
|
ARM64_INS_UQINCW = 1198
|
||
|
|
ARM64_INS_UQRSHL = 1199
|
||
|
|
ARM64_INS_UQRSHLR = 1200
|
||
|
|
ARM64_INS_UQRSHRN = 1201
|
||
|
|
ARM64_INS_UQRSHRN2 = 1202
|
||
|
|
ARM64_INS_UQRSHRNB = 1203
|
||
|
|
ARM64_INS_UQRSHRNT = 1204
|
||
|
|
ARM64_INS_UQSHL = 1205
|
||
|
|
ARM64_INS_UQSHLR = 1206
|
||
|
|
ARM64_INS_UQSHRN = 1207
|
||
|
|
ARM64_INS_UQSHRN2 = 1208
|
||
|
|
ARM64_INS_UQSHRNB = 1209
|
||
|
|
ARM64_INS_UQSHRNT = 1210
|
||
|
|
ARM64_INS_UQSUB = 1211
|
||
|
|
ARM64_INS_UQSUBR = 1212
|
||
|
|
ARM64_INS_UQXTN = 1213
|
||
|
|
ARM64_INS_UQXTN2 = 1214
|
||
|
|
ARM64_INS_UQXTNB = 1215
|
||
|
|
ARM64_INS_UQXTNT = 1216
|
||
|
|
ARM64_INS_URECPE = 1217
|
||
|
|
ARM64_INS_URHADD = 1218
|
||
|
|
ARM64_INS_URSHL = 1219
|
||
|
|
ARM64_INS_URSHLR = 1220
|
||
|
|
ARM64_INS_URSHR = 1221
|
||
|
|
ARM64_INS_URSQRTE = 1222
|
||
|
|
ARM64_INS_URSRA = 1223
|
||
|
|
ARM64_INS_USDOT = 1224
|
||
|
|
ARM64_INS_USHL = 1225
|
||
|
|
ARM64_INS_USHLL = 1226
|
||
|
|
ARM64_INS_USHLL2 = 1227
|
||
|
|
ARM64_INS_USHLLB = 1228
|
||
|
|
ARM64_INS_USHLLT = 1229
|
||
|
|
ARM64_INS_USHR = 1230
|
||
|
|
ARM64_INS_USMMLA = 1231
|
||
|
|
ARM64_INS_USMOPA = 1232
|
||
|
|
ARM64_INS_USMOPS = 1233
|
||
|
|
ARM64_INS_USQADD = 1234
|
||
|
|
ARM64_INS_USRA = 1235
|
||
|
|
ARM64_INS_USUBL = 1236
|
||
|
|
ARM64_INS_USUBL2 = 1237
|
||
|
|
ARM64_INS_USUBLB = 1238
|
||
|
|
ARM64_INS_USUBLT = 1239
|
||
|
|
ARM64_INS_USUBW = 1240
|
||
|
|
ARM64_INS_USUBW2 = 1241
|
||
|
|
ARM64_INS_USUBWB = 1242
|
||
|
|
ARM64_INS_USUBWT = 1243
|
||
|
|
ARM64_INS_UUNPKHI = 1244
|
||
|
|
ARM64_INS_UUNPKLO = 1245
|
||
|
|
ARM64_INS_UXTB = 1246
|
||
|
|
ARM64_INS_UXTH = 1247
|
||
|
|
ARM64_INS_UXTL = 1248
|
||
|
|
ARM64_INS_UXTL2 = 1249
|
||
|
|
ARM64_INS_UXTW = 1250
|
||
|
|
ARM64_INS_UZP1 = 1251
|
||
|
|
ARM64_INS_UZP2 = 1252
|
||
|
|
ARM64_INS_WFE = 1253
|
||
|
|
ARM64_INS_WFET = 1254
|
||
|
|
ARM64_INS_WFI = 1255
|
||
|
|
ARM64_INS_WFIT = 1256
|
||
|
|
ARM64_INS_WHILEGE = 1257
|
||
|
|
ARM64_INS_WHILEGT = 1258
|
||
|
|
ARM64_INS_WHILEHI = 1259
|
||
|
|
ARM64_INS_WHILEHS = 1260
|
||
|
|
ARM64_INS_WHILELE = 1261
|
||
|
|
ARM64_INS_WHILELO = 1262
|
||
|
|
ARM64_INS_WHILELS = 1263
|
||
|
|
ARM64_INS_WHILELT = 1264
|
||
|
|
ARM64_INS_WHILERW = 1265
|
||
|
|
ARM64_INS_WHILEWR = 1266
|
||
|
|
ARM64_INS_WRFFR = 1267
|
||
|
|
ARM64_INS_XAFLAG = 1268
|
||
|
|
ARM64_INS_XAR = 1269
|
||
|
|
ARM64_INS_XPACD = 1270
|
||
|
|
ARM64_INS_XPACI = 1271
|
||
|
|
ARM64_INS_XPACLRI = 1272
|
||
|
|
ARM64_INS_XTN = 1273
|
||
|
|
ARM64_INS_XTN2 = 1274
|
||
|
|
ARM64_INS_YIELD = 1275
|
||
|
|
ARM64_INS_ZERO = 1276
|
||
|
|
ARM64_INS_ZIP1 = 1277
|
||
|
|
ARM64_INS_ZIP2 = 1278
|
||
|
|
ARM64_INS_SBFIZ = 1279
|
||
|
|
ARM64_INS_UBFIZ = 1280
|
||
|
|
ARM64_INS_SBFX = 1281
|
||
|
|
ARM64_INS_UBFX = 1282
|
||
|
|
ARM64_INS_BFI = 1283
|
||
|
|
ARM64_INS_BFXIL = 1284
|
||
|
|
ARM64_INS_IC = 1285
|
||
|
|
ARM64_INS_DC = 1286
|
||
|
|
ARM64_INS_AT = 1287
|
||
|
|
ARM64_INS_TLBI = 1288
|
||
|
|
ARM64_INS_ENDING = 1289
|
||
|
|
|
||
|
|
ARM64_GRP_INVALID = 0
|
||
|
|
ARM64_GRP_JUMP = 1
|
||
|
|
ARM64_GRP_CALL = 2
|
||
|
|
ARM64_GRP_RET = 3
|
||
|
|
ARM64_GRP_INT = 4
|
||
|
|
ARM64_GRP_PRIVILEGE = 6
|
||
|
|
ARM64_GRP_BRANCH_RELATIVE = 7
|
||
|
|
ARM64_GRP_PAC = 8
|
||
|
|
ARM64_GRP_CRYPTO = 128
|
||
|
|
ARM64_GRP_FPARMV8 = 129
|
||
|
|
ARM64_GRP_NEON = 130
|
||
|
|
ARM64_GRP_CRC = 131
|
||
|
|
ARM64_GRP_AES = 132
|
||
|
|
ARM64_GRP_DOTPROD = 133
|
||
|
|
ARM64_GRP_FULLFP16 = 134
|
||
|
|
ARM64_GRP_LSE = 135
|
||
|
|
ARM64_GRP_RCPC = 136
|
||
|
|
ARM64_GRP_RDM = 137
|
||
|
|
ARM64_GRP_SHA2 = 138
|
||
|
|
ARM64_GRP_SHA3 = 139
|
||
|
|
ARM64_GRP_SM4 = 140
|
||
|
|
ARM64_GRP_SVE = 141
|
||
|
|
ARM64_GRP_SVE2 = 142
|
||
|
|
ARM64_GRP_SVE2AES = 143
|
||
|
|
ARM64_GRP_SVE2BitPerm = 144
|
||
|
|
ARM64_GRP_SVE2SHA3 = 145
|
||
|
|
ARM64_GRP_SVE2SM4 = 146
|
||
|
|
ARM64_GRP_SME = 147
|
||
|
|
ARM64_GRP_SMEF64 = 148
|
||
|
|
ARM64_GRP_SMEI64 = 149
|
||
|
|
ARM64_GRP_MatMulFP32 = 150
|
||
|
|
ARM64_GRP_MatMulFP64 = 151
|
||
|
|
ARM64_GRP_MatMulInt8 = 152
|
||
|
|
ARM64_GRP_V8_1A = 153
|
||
|
|
ARM64_GRP_V8_3A = 154
|
||
|
|
ARM64_GRP_V8_4A = 155
|
||
|
|
ARM64_GRP_ENDING = 156
|