136 lines
3.4 KiB
Python
136 lines
3.4 KiB
Python
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#!/usr/bin/env python3
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#
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# Cross Platform and Multi Architecture Advanced Binary Emulation Framework
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#
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from functools import cached_property
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from unicorn import Uc, UC_ARCH_X86, UC_MODE_16, UC_MODE_32, UC_MODE_64
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from capstone import Cs, CS_ARCH_X86, CS_MODE_16, CS_MODE_32, CS_MODE_64
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from keystone import Ks, KS_ARCH_X86, KS_MODE_16, KS_MODE_32, KS_MODE_64
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from qiling.arch.arch import QlArch
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from qiling.arch.msr import QlMsrManager
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from qiling.arch.register import QlRegisterManager
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from qiling.arch import x86_const
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from qiling.const import QL_ARCH, QL_ENDIAN
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class QlArchIntel(QlArch):
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@property
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def endian(self) -> QL_ENDIAN:
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return QL_ENDIAN.EL
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@cached_property
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def msr(self) -> QlMsrManager:
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"""Model-Specific Registers.
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"""
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return QlMsrManager(self.uc)
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class QlArchA8086(QlArchIntel):
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type = QL_ARCH.A8086
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bits = 16
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@cached_property
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def uc(self) -> Uc:
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return Uc(UC_ARCH_X86, UC_MODE_16)
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@cached_property
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def regs(self) -> QlRegisterManager:
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regs_map = dict(
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**x86_const.reg_map_8,
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**x86_const.reg_map_16,
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**x86_const.reg_map_misc
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)
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pc_reg = 'ip'
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sp_reg = 'sp'
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return QlRegisterManager(self.uc, regs_map, pc_reg, sp_reg)
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@cached_property
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def disassembler(self) -> Cs:
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return Cs(CS_ARCH_X86, CS_MODE_16)
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@cached_property
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def assembler(self) -> Ks:
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return Ks(KS_ARCH_X86, KS_MODE_16)
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class QlArchX86(QlArchIntel):
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type = QL_ARCH.X86
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bits = 32
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@cached_property
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def uc(self) -> Uc:
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return Uc(UC_ARCH_X86, UC_MODE_32)
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@cached_property
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def regs(self) -> QlRegisterManager:
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regs_map = dict(
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**x86_const.reg_map_8,
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**x86_const.reg_map_16,
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**x86_const.reg_map_32,
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**x86_const.reg_map_cr,
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**x86_const.reg_map_dr,
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**x86_const.reg_map_st,
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**x86_const.reg_map_misc
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)
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pc_reg = 'eip'
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sp_reg = 'esp'
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return QlRegisterManager(self.uc, regs_map, pc_reg, sp_reg)
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@cached_property
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def disassembler(self) -> Cs:
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return Cs(CS_ARCH_X86, CS_MODE_32)
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@cached_property
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def assembler(self) -> Ks:
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return Ks(KS_ARCH_X86, KS_MODE_32)
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class QlArchX8664(QlArchIntel):
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type = QL_ARCH.X8664
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bits = 64
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@cached_property
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def uc(self) -> Uc:
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return Uc(UC_ARCH_X86, UC_MODE_64)
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@cached_property
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def regs(self) -> QlRegisterManager:
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regs_map = dict(
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**x86_const.reg_map_8,
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**x86_const.reg_map_16,
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**x86_const.reg_map_32,
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**x86_const.reg_map_64,
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**x86_const.reg_map_cr,
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**x86_const.reg_map_dr,
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**x86_const.reg_map_st,
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**x86_const.reg_map_misc,
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**x86_const.reg_map_64_b,
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**x86_const.reg_map_64_w,
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**x86_const.reg_map_64_d,
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**x86_const.reg_map_seg_base,
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**x86_const.reg_map_xmm,
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**x86_const.reg_map_ymm,
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**x86_const.reg_map_zmm
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)
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pc_reg = 'rip'
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sp_reg = 'rsp'
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return QlRegisterManager(self.uc, regs_map, pc_reg, sp_reg)
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@cached_property
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def disassembler(self) -> Cs:
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return Cs(CS_ARCH_X86, CS_MODE_64)
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@cached_property
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def assembler(self) -> Ks:
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return Ks(KS_ARCH_X86, KS_MODE_64)
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