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Samsung_S7/source/exploit/exynos8895-reference.dtsi

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small docs update
2024-08-03 13:38:10 +00:00
/*
* SAMSUNG EXYNOS8895 SoC device tree source
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SAMSUNG EXYNOS8895 SoC device nodes are listed in this file.
* EXYNOS8895 based board files can include this file and provide
* values for board specfic bindings.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/clock/exynos8895.h>
#include <dt-bindings/ufs/ufs.h>
#include <dt-bindings/soc/samsung/exynos8895.h>
#include <dt-bindings/sysmmu/sysmmu.h>
#include <dt-bindings/thermal/thermal.h>
#include "exynos8895-pinctrl.dtsi"
#include "exynos8895-pm-domains.dtsi"
#include "exynos8895-ess.dtsi"
/ {
compatible = "samsung,armv8", "samsung,exynos8895";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <1>;
arm-pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 24 4>,
<0 25 4>,
<0 26 4>,
<0 27 4>,
<0 40 4>,
<0 41 4>,
<0 42 4>,
<0 43 4>;
};
aliases {
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
pinctrl3 = &pinctrl_3;
pinctrl4 = &pinctrl_4;
pinctrl5 = &pinctrl_5;
pinctrl6 = &pinctrl_6;
pinctrl7 = &pinctrl_7;
usi0 = &usi_0;
usi1 = &usi_1;
usi2 = &usi_2;
usi3 = &usi_3;
usi4 = &usi_4;
usi5 = &usi_5;
usi6 = &usi_6;
usi7 = &usi_7;
usi8 = &usi_8;
usi9 = &usi_9;
usi10 = &usi_10;
usi11 = &usi_11;
usi12 = &usi_12;
usi13 = &usi_13;
uart0 = &serial_0;
uart1 = &serial_1;
uart2 = &serial_2;
uart3 = &serial_3;
uart4 = &serial_4;
uart5 = &serial_5;
uart6 = &serial_6;
uart7 = &serial_7;
uart8 = &serial_8;
uart9 = &serial_9;
uart10 = &serial_10;
uart11 = &serial_11;
uart12 = &serial_12;
uart13 = &serial_13;
uart14 = &serial_14;
uart15 = &serial_15;
hsi2c0 = &hsi2c_0;
hsi2c1 = &hsi2c_1;
hsi2c2 = &hsi2c_2;
hsi2c3 = &hsi2c_3;
hsi2c4 = &hsi2c_4;
hsi2c5 = &hsi2c_5;
hsi2c6 = &hsi2c_6;
hsi2c7 = &hsi2c_7;
hsi2c8 = &hsi2c_8;
hsi2c9 = &hsi2c_9;
hsi2c10 = &hsi2c_10;
hsi2c11 = &hsi2c_11;
hsi2c12 = &hsi2c_12;
hsi2c13 = &hsi2c_13;
hsi2c14 = &hsi2c_14;
hsi2c15 = &hsi2c_15;
hsi2c16 = &hsi2c_16;
hsi2c17 = &hsi2c_17;
hsi2c18 = &hsi2c_18;
hsi2c19 = &hsi2c_19;
hsi2c20 = &hsi2c_20;
hsi2c21 = &hsi2c_21;
hsi2c22 = &hsi2c_22;
hsi2c23 = &hsi2c_23;
hsi2c24 = &hsi2c_24;
hsi2c25 = &hsi2c_25;
hsi2c26 = &hsi2c_26;
hsi2c27 = &hsi2c_27;
hsi2c28 = &hsi2c_28;
hsi2c29 = &hsi2c_29;
hsi2c30 = &hsi2c_30;
hsi2c31 = &hsi2c_31;
hsi2c32 = &hsi2c_32;
spi0 = &spi_0;
spi1 = &spi_1;
spi2 = &spi_2;
spi3 = &spi_3;
spi4 = &spi_4;
spi5 = &spi_5;
spi6 = &spi_6;
spi7 = &spi_7;
spi8 = &spi_8;
spi9 = &spi_9;
spi10 = &spi_10;
spi11 = &spi_11;
spi12 = &spi_12;
spi13 = &spi_13;
spi14 = &spi_14;
spi15 = &spi_15;
dpp0 = &idma_g0;
dpp1 = &idma_g1;
dpp2 = &idma_vg0;
dpp3 = &idma_vg1;
dpp4 = &idma_vgf0;
dpp5 = &idma_vgf1;
dpp6 = &odma_wb;
dsim0 = &dsim_0;
displayport = &displayport;
decon0 = &decon_f;
decon1 = &decon_s;
decon2 = &decon_t;
mshc2 = &dwmmc_2;
scaler0 = &scaler_0;
mfc0 = &mfc_0;
};
chipid@10000000 {
compatible = "samsung,exynos8895-chipid";
reg = <0x0 0x10000000 0x100>;
};
reboot {
compatible = "exynos,reboot";
pmu_base = <0x16480000>;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
hmp {
up_threshold = <524>;
down_threshold = <214>;
semiboost_up_threshold = <254>;
semiboost_down_threshold = <163>;
bootboost-duration-us = <40000000>;
down_compensation_timeout = <30>; /* ms */
down_compensation_high_freq = <1248000>; /* min qos lock for little cpu */
down_compensation_mid_freq = <1053000>; /* min qos lock for little cpu */
down_compensation_low_freq = <832000>; /* min qos lock for little cpu */
hmp_up_compst_ratio = <512>;
hmp_down_compst_ratio = <2048>;
little-id = <1>;
};
auto_cpu_mapping {
enabled = <1>;
};
cpu0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x100>;
logical-id = <0>;
enable-method = "psci";
cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
current = <60240 40410 27260 20180 16850 13710 10710 8290 6060>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x101>;
logical-id = <1>;
enable-method = "psci";
cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
current = <60240 40410 27260 20180 16850 13710 10710 8290 6060>;
};
cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x102>;
logical-id = <2>;
enable-method = "psci";
cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
current = <60240 40410 27260 20180 16850 13710 10710 8290 6060>;
};
cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x103>;
logical-id = <3>;
enable-method = "psci";
cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
current = <60240 40410 27260 20180 16850 13710 10710 8290 6060>;
};
cpu4: cpu@0 {
device_type = "cpu";
compatible = "arm,mongoose", "arm,armv8";
reg = <0x0 0x0>;
logical-id = <4>;
enable-method = "psci";
cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
current = <355850 295970 251060 233620 201350 177320 137850 111850 100000 88090 78470 69380 58880>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,mongoose", "arm,armv8";
reg = <0x0 0x1>;
logical-id = <5>;
enable-method = "psci";
cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
current = <355850 295970 251060 233620 201350 177320 137850 111850 100000 88090 78470 69380 58880>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,mongoose", "arm,armv8";
reg = <0x0 0x2>;
logical-id = <6>;
enable-method = "psci";
cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
current = <355850 295970 251060 233620 201350 177320 137850 111850 100000 88090 78470 69380 58880>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,mongoose", "arm,armv8";
reg = <0x0 0x3>;
logical-id = <7>;
enable-method = "psci";
cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
current = <355850 295970 251060 233620 201350 177320 137850 111850 100000 88090 78470 69380 58880>;
};
idle-states {
entry-method = "arm,psci";
BOOTCL_CPU_SLEEP: bootcl-cpu-sleep {
idle-state-name = "c2";
compatible = "exynos,idle-state";
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <35>;
exit-latency-us = <90>;
min-residency-us = <750>;
status = "okay";
};
NONBOOTCL_CPU_SLEEP: nobootcl-cpu-sleep {
idle-state-name = "c2";
compatible = "exynos,idle-state";
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <30>;
exit-latency-us = <75>;
min-residency-us = <2000>;
status = "okay";
};
};
};
psci {
compatible = "arm,psci";
method = "smc";
cpu_suspend = <0xC4000001>;
cpu_off = <0x84000002>;
cpu_on = <0xC4000003>;
};
cpu_hotplug {
compatible = "exynos,cpu_hotplug";
boot_lock_time = <40>;
};
exynos-pmu {
compatible = "samsung,exynos-pmu";
samsung,syscon-phandle = <&pmu_system_controller>;
};
pmu_system_controller: system-controller@16480000 {
compatible = "samsung,exynos8895-pmu", "syscon";
reg = <0x0 0x16480000 0x10000>;
};
exynos-pm {
compatible = "samsung,exynos-pm";
reg = <0x0 0x164B0000 0x1000>,
<0x0 0x10201200 0x100>;
reg-names = "gpio_alive_base",
"gicd_ispendrn_base";
num-eint = <32>;
num-gic = <16>;
suspend_mode_idx = <8>; /* SYS_SLEEP */
suspend_psci_idx = <133>; /* PSCI_SYSTEM_SLEEP */
cp_call_mode_idx = <10>; /* SYS_SLEEP_AUD_ON */
cp_call_psci_idx = <133>; /* PSCI_SYSTEM_SLEEP */
extra_wakeup_stat = <0x640>;
};
exynos-powermode {
cpd_residency = <3000>;
sicd_residency = <3000>;
cpd_enabled = <1>;
sicd_enabled = <1>;
idle-ip = "104c0000.pwm", /* [ 0] pwm */
"15b70000.adc", /* [ 1] adc */
"15bc0000.hsi2c", /* [ 2] hsi2c_0 */
"10990000.hsi2c", /* [ 3] hsi2c_1 */
"109a0000.hsi2c", /* [ 4] hsi2c_2 */
"109b0000.hsi2c", /* [ 5] hsi2c_3 */
"109c0000.hsi2c", /* [ 6] hsi2c_4 */
"10440000.hsi2c", /* [ 7] hsi2c_5 */
"10450000.hsi2c", /* [ 8] hsi2c_6 */
"10460000.hsi2c", /* [ 9] hsi2c_7 */
"10470000.hsi2c", /* [10] hsi2c_8 */
"10480000.hsi2c", /* [11] hsi2c_9 */
"10490000.hsi2c", /* [12] hsi2c_10 */
"104a0000.hsi2c", /* [13] hsi2c_11 */
"104b0000.hsi2c", /* [14] hsi2c_12 */
"10840000.hsi2c", /* [15] hsi2c_13 */
"10850000.hsi2c", /* [16] hsi2c_14 */
"10860000.hsi2c", /* [17] hsi2c_15 */
"10870000.hsi2c", /* [18] hsi2c_16 */
"10880000.hsi2c", /* [19] hsi2c_17 */
"10890000.hsi2c", /* [20] hsi2c_18 */
"108a0000.hsi2c", /* [21] hsi2c_19 */
"108b0000.hsi2c", /* [22] hsi2c_20 */
"108c0000.hsi2c", /* [23] hsi2c_21 */
"108d0000.hsi2c", /* [24] hsi2c_22 */
"108e0000.hsi2c", /* [25] hsi2c_23 */
"108f0000.hsi2c", /* [26] hsi2c_24 */
"10900000.hsi2c", /* [27] hsi2c_25 */
"10910000.hsi2c", /* [28] hsi2c_26 */
"10920000.hsi2c", /* [29] hsi2c_27 */
"10930000.hsi2c", /* [30] hsi2c_28 */
"10940000.hsi2c", /* [31] hsi2c_29 */
"10950000.hsi2c", /* [32] hsi2c_30 */
"10960000.hsi2c", /* [33] hsi2c_31 */
"10970000.hsi2c", /* [34] hsi2c_32 */
"109e0000.spi", /* [35] spi_0 */
"109e0000.spi", /* [36] spi_1 */
"10440000.spi", /* [37] spi_2 */
"10460000.spi", /* [38] spi_3 */
"10480000.spi", /* [39] spi_4 */
"104a0000.spi", /* [40] spi_5 */
"10840000.spi", /* [41] spi_6 */
"10860000.spi", /* [42] spi_7 */
"10880000.spi", /* [43] spi_8 */
"108a0000.spi", /* [44] spi_9 */
"108c0000.spi", /* [45] spi_10 */
"108e0000.spi", /* [46] spi_11 */
"10900000.spi", /* [47] spi_12 */
"10920000.spi", /* [48] spi_13 */
"10940000.spi", /* [49] spi_14 */
"10960000.spi", /* [50] spi_15 */
"11120000.ufs", /* [51] ufs */
"11500000.dwmmc2", /* [52] dwmmc2 */
"10c00000.usb", /* [53] usb */
"14040000.mailbox", /* [54] mailbox */
"116a0000.pcie0", /* [55] pcie0 */
"116b0000.pcie1", /* [56] pcie1 */
"pd-abox", /* [57] pd-abox */
"pd-cam", /* [58] pd-cam */
"pd-dbg", /* [59] pd-dbg */
"pd-dcam", /* [60] pd-dcam */
"pd-dpu0", /* [61] pd-dpu0 */
"pd-dpu1", /* [62] pd-dpu1 */
"pd-dsp", /* [63] pd-dsp */
"pd-g2d", /* [64] pd-g2d */
"pd-g3d", /* [65] pd-g3d */
"pd-isphq", /* [66] pd-isphq */
"pd-isplp", /* [67] pd-isplp */
"pd-iva", /* [68] pd-iva */
"pd-mfc", /* [69] pd-mfc */
"pd-srdz", /* [70] pd-srdz */
"pd-vpu", /* [71] pd-vpu */
"pd-vts", /* [72] pd-vts */
"bluetooth"; /* [73] bluetooth */
fix-idle-ip = "acpm_dvfs";
fix-idle-ip-index = <96>;
idle_ip_mask {
sicd: SYS_SICD {
mode-index = <0>;
ref-idle-ip = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>,
<10>, <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>,
<20>, <21>, <22>, <23>, <24>, <25>, <26>, <27>, <28>, <29>,
<30>, <31>, <32>, <33>, <34>, <35>, <36>, <37>, <38>, <39>,
<40>, <41>, <42>, <43>, <44>, <45>, <46>, <47>, <48>, <49>,
<50>, <51>, <52>, <53>, <54>, <55>, <56>, <58>,
<60>, <61>, <62>, <63>, <64>, <65>, <66>, <67>, <68>, <69>,
<70>, <71>, <73>, <96>;
};
};
wakeup-masks {
/*
* wakeup_mask configuration
* SICD SICD_CPD AFTR STOP
* LPD LPA ALPA DSTOP
* SLEEP SLEEP_VTS_ON SLEEP_AUD_ON FAPO
*/
wakeup-mask {
mask = <0x400001E0>, <0x0>, <0x0>, <0x0>,
<0x0>, <0x0>, <0x0>, <0x0>,
<0x500F7E7E>, <0x500F7E7E>, <0x500F7E7E>, <0x0>;
reg-offset = <0x610>;
};
wakeup-mask2 {
mask = <0x0>, <0x0>, <0x0>, <0x0>,
<0x0>, <0x0>, <0x0>, <0x0>,
<0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>;
reg-offset = <0x614>;
};
wakeup-mask3 {
mask = <0x0>, <0x0>, <0x0>, <0x0>,
<0x0>, <0x0>, <0x0>, <0x0>,
<0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>;
reg-offset = <0x618>;
};
wakeup-mask4 {
mask = <0x0>, <0x0>, <0x0>, <0x0>,
<0x0>, <0x0>, <0x0>, <0x0>,
<0x0>, <0x0>, <0x0>, <0x0>;
reg-offset = <0x644>;
};
};
};
schedtune {
domain@0 {
device_type = "schedtune-freqvar";
shared-cpus = "0-3";
/* this table works like target_load of interactive parameter */
table = < 100 598000 60 715000 30 832000 20 949000 10 1053000 0 >;
};
domain@1 {
device_type = "schedtune-freqvar";
shared-cpus = "4-7";
/* this table works like target_load of interactive parameter */
table = < 20 858000 15 962000 5 1261000 0 >;
};
};
cpufreq {
domain@0 {
device_type = "cpufreq-domain";
sibling-cpus = "0-3";
cal-id = <ACPM_DVFS_CPUCL1>;
dm-type = <DM_CPU_CL0>;
min-freq = <455000>;
/* PM QoS Class ID*/
pm_qos-min-class = <3>;
pm_qos-max-class = <4>;
user-default-qos = <715000>;
/* auto calibration value */
auto-cal-freq = <1053000>;
auto-cal-duration = <400>; /* ms */
dm-constraints {
mif-perf {
const-type = <CONSTRAINT_MIN>;
dm-type = <DM_MIF>;
/* cpu mif */
table = < 2002000 1014000
1898000 1014000
1794000 1014000
1690000 1014000
1456000 845000
1248000 845000
1053000 845000
949000 845000
832000 676000
715000 676000
598000 421000
455000 0
>;
};
mif-skew {
guidance;
const-type = <CONSTRAINT_MIN>;
dm-type = <DM_MIF>;
ect-name = "dvfs_cpucl1";
};
};
};
domain@1 {
device_type = "cpufreq-domain";
sibling-cpus = "4-7";
cal-id = <ACPM_DVFS_CPUCL0>;
dm-type = <DM_CPU_CL1>;
min-freq = <741000>;
/* PM QoS Class ID*/
pm_qos-min-class = <5>;
pm_qos-max-class = <6>;
pm_qos-jigbooting = <1469000>;
/* auto calibration value */
auto-cal-freq = <1703000>;
auto-cal-duration = <400>; /* ms */
dm-constraints {
mif-perf {
const-type = <CONSTRAINT_MIN>;
dm-type = <DM_MIF>;
/* cpu mif */
table = < 2808000 1794000
2704000 1794000
2652000 1794000
2574000 1794000
2496000 1794000
2314000 1794000
2158000 1540000
2002000 1540000
1937000 1352000
1807000 1352000
1703000 1014000
1469000 845000
1261000 676000
1170000 546000
1066000 546000
962000 421000
858000 421000
741000 421000 >;
};
mif-skew {
guidance;
const-type = <CONSTRAINT_MIN>;
dm-type = <DM_MIF>;
ect-name = "dvfs_cpucl0";
};
};
};
};
gic:interrupt-controller@10200000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x10201000 0x1000>,
<0x0 0x10202000 0x1000>,
<0x0 0x10204000 0x2000>,
<0x0 0x10206000 0x2000>;
interrupts = <1 9 0xf04>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xff01>,
<1 14 0xff01>,
<1 11 0xff01>,
<1 10 0xff01>;
clock-frequency = <26000000>;
use-clocksource-only;
use-physical-timer;
};
clock: clock-controller@0x15a80000 {
compatible = "samsung,exynos8895-clock";
reg = <0x0 0x15a80000 0x8000>;
#clock-cells = <1>;
acpm-ipc-channel = <0>;
};
sysreg_fsys0_controller: sysreg-controller@11020000 {
compatible = "samsung,exynos8895-sysreg", "syscon";
reg = <0x0 0x11020000 0x1200>;
};
sysreg_fsys1_controller: sysreg-controller@11420000 {
compatible = "samsung,exynos8895-sysreg", "syscon";
reg = <0x0 0x11420000 0x1200>;
};
mct@10040000 {
compatible = "samsung,exynos4210-mct";
reg = <0x0 0x10040000 0x800>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&mct_map>;
interrupts = <0>, <1>, <2>, <3>,
<4>, <5>, <6>, <7>,
<8>, <9>, <10>, <11>;
clocks = <&clock OSCCLK>, <&clock GATE_MCT>;
clock-names = "fin_pll", "mct";
use-clockevent-only;
mct_map: mct-map {
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = <0 &gic 0 455 0>,
<1 &gic 0 456 0>,
<2 &gic 0 457 0>,
<3 &gic 0 458 0>,
<4 &gic 0 459 0>,
<5 &gic 0 460 0>,
<6 &gic 0 461 0>,
<7 &gic 0 462 0>,
<8 &gic 0 463 0>,
<9 &gic 0 464 0>,
<10 &gic 0 465 0>,
<11 &gic 0 466 0>;
};
};
/* DMA */
amba {
#address-cells = <2>;
#size-cells = <1>;
compatible = "arm,amba-bus";
interrupt-parent = <&gic>;
ranges;
pdma0: pdma0@15A40000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0x15A40000 0x1000>;
interrupts = <0 107 0>;
clocks = <&clock GATE_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <2>;
#dma-channels = <8>;
#dma-requests = <32>;
#dma_mcode_addr = <0x13F2C000>;
#dma-multi-irq = <1>;
dma-arwrapper = <0x15A44400>,
<0x15A44420>,
<0x15A44440>,
<0x15A44460>,
<0x15A44480>,
<0x15A444A0>,
<0x15A444C0>,
<0x15A444E0>;
dma-awwrapper = <0x15A44404>,
<0x15A44424>,
<0x15A44444>,
<0x15A44464>,
<0x15A44484>,
<0x15A444A4>,
<0x15A444C4>,
<0x15A444E4>;
dma-instwrapper = <0x15A44500>;
dma-selchan = <0x15A22200>;
dma-mask-bit = <36>;
coherent-mask-bit = <36>;
};
};
ITMON@0 {
compatible = "samsung,exynos-itmon";
interrupts = <0 72 0>, /* DATA_BUS_1 */
<0 311 0>, /* DATA_CORE */
<0 92 0>, /* DATA_BUS_C */
<0 315 0>, /* PERI_CORE_0 */
<0 316 0>, /* PERI_CORE_1 */
<0 93 0>, /* PERI_BUS_C */
<0 77 0>; /* PERI_BUS_1 */
};
/* ALIVE */
pinctrl_0: pinctrl@164B0000 {
compatible = "samsung,exynos8895-pinctrl";
reg = <0x0 0x164B0000 0x1000>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
wakeup-interrupt-controller {
compatible = "samsung,exynos7-wakeup-eint";
interrupt-parent = <&gic>;
interrupts = <0 16 0>;
};
};
/* A-BOX */
pinctrl_1: pinctrl@13E60000{
compatible = "samsung,exynos8895-pinctrl";
reg = <0x0 0x13E60000 0x1000>;
};
/* VTS */
pinctrl_2: pinctrl@14080000 {
compatible = "samsung,exynos8895-pinctrl";
reg = <0x0 0x14080000 0x1000>;
};
/* FSYS0 */
pinctrl_3: pinctrl@11050000 {
compatible = "samsung,exynos8895-pinctrl";
reg = <0x0 0x11050000 0x1000>;
interrupts = <0 335 0>;
};
/* FSYS1 */
pinctrl_4: pinctrl@11430000 {
compatible = "samsung,exynos8895-pinctrl";
reg = <0x0 0x11430000 0x1000>;
interrupts = <0 342 0>;
};
/* BUSC */
pinctrl_5: pinctrl@15A30000 {
compatible = "samsung,exynos8895-pinctrl";
reg = <0x0 0x15A30000 0x1000>;
interrupts = <0 103 0>;
};
/* PERIC0 */
pinctrl_6: pinctrl@104D0000 {
compatible = "samsung,exynos8895-pinctrl";
reg = <0x0 0x104D0000 0x1000>;
interrupts = <0 386 0>;
pinctrl-names = "default";
};
/* PERIC1 */
pinctrl_7: pinctrl@10980000 {
compatible = "samsung,exynos8895-pinctrl";
reg = <0x0 0x10980000 0x1000>;
interrupts = <0 430 0>;
};
mali: mali@13900000 {
compatible = "arm,mali";
reg = <0x0 0x13900000 0x5000>;
interrupts = <0 60 0>, <0 61 0>, <0 59 0>;
interrupt-names = "JOB", "MMU", "GPU";
g3d_cmu_cal_id = <ACPM_DVFS_G3D>;
samsung,power-domain = <&pd_g3d>;
#cooling-cells = <2>; /* min followed by max */
};
ufs@0x11120000 {
/* ----------------------- */
/* 1. SYSTEM CONFIGURATION */
/* ----------------------- */
compatible ="samsung,exynos-ufs";
#address-cells = <2>;
#size-cells = <1>;
ranges;
reg =
<0x0 0x11120000 0x200>, /* 0: HCI standard */
<0x0 0x11121100 0x200>, /* 1: Vendor specificed */
<0x0 0x11110000 0x8000>, /* 2: UNIPRO */
<0x0 0x11130000 0x100>; /* 3: UFS protector */
interrupts = <0 334 0>;
pinctrl-names = "default";
pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
clocks =
/* aclk clock */
<&clock GATE_UFS_EMBD>,
/* unipro clocks */
<&clock UFS_EMBD>;
clock-names =
/* aclk clocks */
"GATE_UFS_EMBD",
/* unipro clocks */
"UFS_EMBD";
/* PM QoS for INT power domain */
ufs-pm-qos-int = <400000>;
/* DMA coherent callback, should be coupled with 'ufs-sys' */
dma-coherent;
/* Alive block sfr for TCXO control */
samsung,pmu-phandle = <&pmu_system_controller>;
/* ----------------------- */
/* 2. UFS COMMON */
/* ----------------------- */
freq-table-hz = <0 0>, <0 0>;
pclk-freq-avail-range = <70000000 166000000>;
ufs,pmd-local-l2-timer = <8000 28000 20000>;
ufs,pmd-remote-l2-timer = <12000 32000 16000>;
vcc-supply = <&ufs_fixed_vcc>;
vcc-fixed-regulator;
/* ----------------------- */
/* 3. UFS EXYNOS */
/* ----------------------- */
hw-rev = <UFS_VER_0004>;
/* power mode change */
ufs,pmd-attr-mode = "FAST";
ufs,pmd-attr-lane = /bits/ 8 <2>;
ufs,pmd-attr-gear = /bits/ 8 <3>;
ufs,pmd-attr-hs-series = "HS_rate_b";
/* hiberantion */
ufs-rx-adv-fine-gran-sup_en = <0>;
ufs-rx-min-activate-time-cap = <3>;
ufs-rx-hibern8-time-cap = <2>;
ufs-tx-hibern8-time-cap = <2>;
/* misc table */
phy-init =
<0x9514 0x00 PMD_ALL UNIPRO_DBG_PRD>, //Unipro Clock Period
<0x200 0x40 PMD_ALL PHY_PCS_COMN>, //OV_TM On
<0x12 0x00 PMD_ALL PHY_PCS_RX_PRD>, //PCS RX Clock Period
<0xAA 0x00 PMD_ALL PHY_PCS_TX_PRD>, //PCS TX Clock Period
<0x5C 0x38 PMD_ALL PHY_PCS_RX>,
<0x0F 0x0 PMD_ALL PHY_PCS_RX>,
<0x65 0x01 PMD_ALL PHY_PCS_RX>, //PCS RX INT_H8_COUNT_CAP_ENABLE[0] = 1b'1(THIBERN8 CAPABILITY(200us))
<0x69 0x01 PMD_ALL PHY_PCS_RX>,
<0x21 0x00 PMD_ALL PHY_PCS_RX>,
<0x22 0x00 PMD_ALL PHY_PCS_RX>,
<0x84 0x01 PMD_ALL PHY_PCS_RX>,
<0x04 0x01 PMD_ALL PHY_PCS_TX>,
<0x200 0x0 PMD_ALL PHY_PCS_COMN>, //OV_TM Off
<0x9536 0x4E20 PMD_ALL UNIPRO_DBG_MIB>,
<0x9564 0x2e820183 PMD_ALL UNIPRO_DBG_MIB>, //DBG_PA_OPTION_SUITE
<0x155E 0x0 PMD_ALL UNIPRO_STD_MIB>, //LCC disable
<0x3000 0x0 PMD_ALL UNIPRO_STD_MIB>, //N_DeviceID
<0x3001 0x1 PMD_ALL UNIPRO_STD_MIB>, //N_DeviceID_valid
<0x4021 0x1 PMD_ALL UNIPRO_STD_MIB>, //T_PeerDeviceID
<0x4020 0x1 PMD_ALL UNIPRO_STD_MIB>, //T_ConnectionState
<0x8C 0x80 PMD_ALL PHY_PMA_COMN>,
<0x74 0x10 PMD_ALL PHY_PMA_COMN>, //CMN_1D(0x74), PWM clock generation selection: CMN_REG1D(0x10 = Refclk, 0x20 = int OSC)
<0x110 0xB5 PMD_ALL PHY_PMA_TRSV>, //TRSVx_14(0x110/0x250), TRSVx_REG14(RXAFE_DIFN_SQ_PULSE_REJ_EN = 1b'0)
<0x134 0x43 PMD_ALL PHY_PMA_TRSV>, //TRSVx_1D(0x134/0x274),
<0x16C 0x20 PMD_ALL PHY_PMA_TRSV>, //TRSVx_2B(0x16C/0x2AC),
<0x178 0xC0 PMD_ALL PHY_PMA_TRSV>, //TRSVx_2E(0x178/0x2B8),
<0xE0 0x12 PMD_ALL PHY_PMA_TRSV>,
<0x164 0x58 PMD_ALL PHY_PMA_TRSV>,
<0x8C 0xC0 PMD_ALL PHY_PMA_COMN>,
<0x8C 0x00 PMD_ALL PHY_PMA_COMN>,
<0x00 0xC8 PMD_ALL COMMON_WAIT>,
<0 0 0 0>;
post-phy-init =
<0x9529 0x1 PMD_ALL UNIPRO_DBG_MIB>, //Unipro Debug Mode On
<0x15A4 0xFA PMD_ALL UNIPRO_STD_MIB>, //PA_SaveConfigTime
<0x9529 0x0 PMD_ALL UNIPRO_DBG_MIB>, //Unipro Debug Mode Off
<0x200 0x40 PMD_ALL PHY_PCS_COMN>,
<0x35 0x05 PMD_ALL PHY_PCS_RX>,
<0x73 0x01 PMD_ALL PHY_PCS_RX>,
<0x41 0x02 PMD_ALL PHY_PCS_RX>,
<0x42 0xAC PMD_ALL PHY_PCS_RX>,
<0x200 0x0 PMD_ALL PHY_PCS_COMN>,
<0 0 0 0>;
calib-of-pwm =
<0x1569 0x0 PMD_PWM UNIPRO_STD_MIB>,
<0x1584 0x0 PMD_PWM UNIPRO_STD_MIB>,
<0x2041 8064 PMD_PWM UNIPRO_STD_MIB>,
<0x2042 28224 PMD_PWM UNIPRO_STD_MIB>,
<0x2043 20160 PMD_PWM UNIPRO_STD_MIB>,
<0x15B0 12000 PMD_PWM UNIPRO_STD_MIB>,
<0x15B1 32000 PMD_PWM UNIPRO_STD_MIB>,
<0x15B2 16000 PMD_PWM UNIPRO_STD_MIB>,
<0x7888 8064 PMD_PWM UNIPRO_DBG_APB>,
<0x788C 28224 PMD_PWM UNIPRO_DBG_APB>,
<0x7890 20160 PMD_PWM UNIPRO_DBG_APB>,
<0x78B8 12000 PMD_PWM UNIPRO_DBG_APB>,
<0x78BC 32000 PMD_PWM UNIPRO_DBG_APB>,
<0x78C0 16000 PMD_PWM UNIPRO_DBG_APB>,
/*MPHY tuning value*/
<0xC8 0x40 PMD_PWM PHY_PMA_TRSV>, //TRSVx_02(0xC8/0x208),
<0xF0 0x77 PMD_PWM PHY_PMA_TRSV>, //TRSVx_0c(0xF0/0x230), TX_SLEW_PREEMP_EN_CTRL_EN(bit3) = 1b'0
<0x120 0x80 PMD_PWM PHY_PMA_TRSV>, //TRSVx_18(0x120/0x260), TX_AMPL_CNTR_EN(bit6) = 1b'0
<0x128 0x00 PMD_PWM PHY_PMA_TRSV>, //TRSVx_1a(0x128/0x268), TX_AMPL_CTRL(bit[4:0], Amplitude) = 5b'00000(PWM)
<0x12C 0x00 PMD_PWM PHY_PMA_TRSV>, //TRSVx_1b(0x12C/0x26C), TX_PREEMP_CTRL(bit[5:4]) = 2b'00(0dB)
<0x134 0x43 PMD_PWM PHY_PMA_TRSV>, //TRSVx_1d(0x134/0x274), TX_AUX_CAP_INV_SEL(bit7) = 1b'0, TX_AUX_CAP_CTRL(bit[6:4]) = 3b'100
<0 0 0 0>;
calib-of-hs-rate-a =
<0x1569 0x1 PMD_HS UNIPRO_STD_MIB>,
<0x1584 0x1 PMD_HS UNIPRO_STD_MIB>,
<0x2041 8064 PMD_HS UNIPRO_STD_MIB>,
<0x2042 28224 PMD_HS UNIPRO_STD_MIB>,
<0x2043 20160 PMD_HS UNIPRO_STD_MIB>,
<0x15B0 12000 PMD_HS UNIPRO_STD_MIB>,
<0x15B1 32000 PMD_HS UNIPRO_STD_MIB>,
<0x15B2 16000 PMD_HS UNIPRO_STD_MIB>,
<0x7888 8064 PMD_HS UNIPRO_DBG_APB>,
<0x788C 28224 PMD_HS UNIPRO_DBG_APB>,
<0x7890 20160 PMD_HS UNIPRO_DBG_APB>,
<0x78B8 12000 PMD_HS UNIPRO_DBG_APB>,
<0x78BC 32000 PMD_HS UNIPRO_DBG_APB>,
<0x78C0 16000 PMD_HS UNIPRO_DBG_APB>,
/*MPHY tuning value*/
<0xC8 0xBC PMD_HS PHY_PMA_TRSV>, //TRSVx_02(0xC8/0x208),
<0xF0 0x7F PMD_HS PHY_PMA_TRSV>, //TRSVx_0c(0xF0/0x230), TX_SLEW_PREEMP_EN_CTRL_EN(bit3) = 1b'1
<0x120 0xC0 PMD_HS PHY_PMA_TRSV>, //TRSVx_18(0x120/0x260), TX_AMPL_CNTR_EN(bit6) = 1b'1
<0x128 0x08 PMD_HS_G1_L2 PHY_PMA_TRSV>, //TRSVx_1a(0x128/0x268), TX_AMPL_CTRL(bit[4:0], Amplitude) = 5b'01000(G1A/B)
<0x128 0x02 PMD_HS_G2_L2 PHY_PMA_TRSV>, // TX_AMPL_CTRL(bit[4:0], Amplitude) = 5b'00010(G2A/B)
<0x128 0x00 PMD_HS_G3_L2 PHY_PMA_TRSV>, // TX_AMPL_CTRL(bit[4:0], Amplitude) = 5b'00000(G3A/B)
<0x12C 0x00 (PMD_HS_G1_L2|PMD_HS_G3_L2) PHY_PMA_TRSV>, // TX_PREEMP_CTRL(bit[5:4]) = 2b'00(0dB)
<0x12C 0x00 PMD_HS_G2_L2 PHY_PMA_TRSV>, // TX_PREEMP_CTRL(bit[5:4]) = 2b'00(0dB, G2A/B))
<0x134 0xd3 PMD_HS_G1_L2 PHY_PMA_TRSV>, //TRSVx_1d(0x134/0x274), TX_AUX_CAP_INV_SEL(bit7) = 1b'1, TX_AUX_CAP_CTRL(bit[6:4]) = 3b'101
<0x134 0x73 PMD_HS_G2_L2 PHY_PMA_TRSV>, // TX_AUX_CAP_CTRL(bit[6:4]) = 3b'111
<0x134 0x63 PMD_HS_G3_L2 PHY_PMA_TRSV>, // TX_AUX_CAP_CTRL(bit[6:4]) = 3b'110
<0x108 0x5D PMD_HS PHY_PMA_TRSV>, //
<0x10C 0x90 PMD_HS PHY_PMA_TRSV>, //
<0 0 0 0>;
calib-of-hs-rate-b =
<0x1569 0x1 PMD_HS UNIPRO_STD_MIB>,
<0x1584 0x1 PMD_HS UNIPRO_STD_MIB>,
<0x2041 8064 PMD_HS UNIPRO_STD_MIB>,
<0x2042 28224 PMD_HS UNIPRO_STD_MIB>,
<0x2043 20160 PMD_HS UNIPRO_STD_MIB>,
<0x15B0 12000 PMD_HS UNIPRO_STD_MIB>,
<0x15B1 32000 PMD_HS UNIPRO_STD_MIB>,
<0x15B2 16000 PMD_HS UNIPRO_STD_MIB>,
<0x7888 8064 PMD_HS UNIPRO_DBG_APB>,
<0x788C 28224 PMD_HS UNIPRO_DBG_APB>,
<0x7890 20160 PMD_HS UNIPRO_DBG_APB>,
<0x78B8 12000 PMD_HS UNIPRO_DBG_APB>,
<0x78BC 32000 PMD_HS UNIPRO_DBG_APB>,
<0x78C0 16000 PMD_HS UNIPRO_DBG_APB>,
/*MPHY tuning value*/
<0xC8 0xBC PMD_HS PHY_PMA_TRSV>, //TRSVx_02(0xC8/0x208),
<0xF0 0x7F PMD_HS PHY_PMA_TRSV>, //TRSVx_0c(0xF0/0x230), TX_SLEW_PREEMP_EN_CTRL_EN(bit3) = 1b'1
<0x120 0xC0 PMD_HS PHY_PMA_TRSV>, //TRSVx_18(0x120/0x260), TX_AMPL_CNTR_EN(bit6) = 1b'1
<0x128 0x08 PMD_HS_G1_L2 PHY_PMA_TRSV>, //TRSVx_1a(0x128/0x268), TX_AMPL_CTRL(bit[4:0], Amplitude) = 5b'01000(G1A/B)
<0x128 0x02 PMD_HS_G2_L2 PHY_PMA_TRSV>, // TX_AMPL_CTRL(bit[4:0], Amplitude) = 5b'00010(G2A/B)
<0x128 0x00 PMD_HS_G3_L2 PHY_PMA_TRSV>, // TX_AMPL_CTRL(bit[4:0], Amplitude) = 5b'00000(G3A/B)
<0x12C 0x00 (PMD_HS_G1_L2|PMD_HS_G3_L2) PHY_PMA_TRSV>, // TX_PREEMP_CTRL(bit[5:4]) = 2b'00(0dB)
<0x12C 0x00 PMD_HS_G2_L2 PHY_PMA_TRSV>, // TX_PREEMP_CTRL(bit[5:4]) = 2b'00(0dB, G2A/B))
<0x134 0xd3 PMD_HS_G1_L2 PHY_PMA_TRSV>, //TRSVx_1d(0x134/0x274), TX_AUX_CAP_INV_SEL(bit7) = 1b'1, TX_AUX_CAP_CTRL(bit[6:4]) = 3b'101
<0x134 0x73 PMD_HS_G2_L2 PHY_PMA_TRSV>, // TX_AUX_CAP_CTRL(bit[6:4]) = 3b'111
<0x134 0x63 PMD_HS_G3_L2 PHY_PMA_TRSV>, //
<0x108 0x5D PMD_HS PHY_PMA_TRSV>, //
<0x10C 0x90 PMD_HS PHY_PMA_TRSV>, //
<0 0 0 0>;
post-calib-of-pwm =
<0 0 0 0>;
post-calib-of-hs-rate-a =
<0x1fc 0x01 PMD_HS PHY_CDR_WAIT>,
<0 0 0 0>;
post-calib-of-hs-rate-b =
<0x1fc 0x01 PMD_HS PHY_CDR_WAIT>,
<0 0 0 0>;
lpa-restore =
<0 0 0 0>;
pre-clk-off =
/* SQ off */
<0x0C4 0x99 PMD_ALL PHY_PMA_TRSV>,
<0x0E8 0x7F PMD_ALL PHY_PMA_TRSV>,
<0x004 0x02 PMD_ALL PHY_PMA_COMN>,
<0 0 0 0>;
post-clk-on =
/* SQ on */
<0x004 0x00 PMD_ALL PHY_PMA_COMN>,
<0x0C4 0xD9 PMD_ALL PHY_PMA_TRSV>,
<0x0E8 0x77 PMD_ALL PHY_PMA_TRSV>,
<0 0 0 0>;
lane1-sq-off =
/* SQ off only for 1lane */
<0x0C4 0x19 PMD_ALL PHY_PMA_TRSV_LANE1_SQ_OFF>,
<0x0E8 0xFF PMD_ALL PHY_PMA_TRSV_LANE1_SQ_OFF>,
<0 0 0 0>;
/* ----------------------- */
/* 4. ADDITIONAL NODES */
/* ----------------------- */
/* PHY isolation */
ufs-phy {
#address-cells = <2>;
#size-cells = <1>;
ranges;
reg = <0x0 0x11124000 0x800>;
ufs-phy-sys {
reg = <0x0 0x16480724 0x4>;
};
};
/* SYSREG */
ufs-io-coherency {
#address-cells = <2>;
#size-cells = <1>;
ranges;
reg =
<0x0 0x11020700 0x4>;
mask = <(BIT_8 | BIT_9)>;
bits = <(BIT_8 | BIT_9)>;
};
ufs-tcxo-sel {
#address-cells = <2>;
#size-cells = <1>;
ranges;
reg =
<0x0 0x11021150 0x4>;
mask = <BIT_0>;
bits = <BIT_0>; // use alternative
};
};
ufs_fixed_vcc: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "ufs-vcc";
gpio = <&gpg0 0 0>;
regulator-boot-on;
enable-active-high;
};
/* UART_DBG */
serial_0: uart@10430000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x10430000 0x100>;
samsung,fifo-size = <256>;
interrupts = <0 385 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_bus>;
clocks = <&clock GATE_UART_DBG>, <&clock UART_DBG>;
clock-names = "gate_pclk0", "gate_uart0";
status = "disabled";
};
/* UART_BT */
serial_1: uart@10830000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x10830000 0x100>;
samsung,fifo-size = <256>;
interrupts = <0 389 0>;
pinctrl-names = "btdefault", "btsleep";
pinctrl-0 = <&uart1_default>;
pinctrl-1 = <&uart1_btsleep>;
clocks = <&clock GATE_UART_BT>, <&clock UART_BT>;
clock-names = "gate_pclk1", "gate_uart1";
status = "okay";
};
/* USI0_UART */
serial_2: uart@10440000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x10440000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 366 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_bus_single>; /* or <&uart2_bus_dual> */
clocks = <&clock GATE_USI00>, <&clock USI00>;
clock-names = "gate_pclk2", "gate_uart2";
status = "disabled";
};
/* USI1_UART */
serial_3: uart@10460000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x10460000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 370 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_bus_single>; /* or <&uart3_bus_dual> */
clocks = <&clock GATE_USI01>, <&clock USI01>;
clock-names = "gate_pclk3", "gate_uart3";
status = "disabled";
};
/* USI2_UART */
serial_4: uart@10480000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x10480000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 374 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart4_bus_single>; /* or <&uart4_bus_dual> */
clocks = <&clock GATE_USI02>, <&clock USI02>;
clock-names = "gate_pclk4", "gate_uart4";
status = "disabled";
};
/* USI3_UART */
serial_5: uart@104A0000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x104A0000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 378 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart5_bus_single>; /* or <&uart5_bus_dual> */
clocks = <&clock GATE_USI03>, <&clock USI03>;
clock-names = "gate_pclk5", "gate_uart5";
status = "disabled";
};
/* USI4_UART */
serial_6: uart@10840000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x10840000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 392 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart6_bus_single>; /* or <&uart6_bus_dual> */
clocks = <&clock GATE_USI04>, <&clock USI04>;
clock-names = "gate_pclk6", "gate_uart6";
status = "disabled";
};
/* USI5_UART */
serial_7: uart@10860000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x10860000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 396 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart7_bus_single>; /* or <&uart7_bus_dual> */
clocks = <&clock GATE_USI05>, <&clock USI05>;
clock-names = "gate_pclk7", "gate_uart7";
status = "disabled";
};
/* USI6_UART */
serial_8: uart@10880000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x10880000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 400 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart8_bus_single>; /* or <&uart8_bus_dual> */
clocks = <&clock GATE_USI06>, <&clock USI06>;
clock-names = "gate_pclk8", "gate_uart8";
status = "disabled";
};
/* USI7_UART */
serial_9: uart@108A0000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x108A0000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 404 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart9_bus_single>; /* or <&uart9_bus_dual> */
clocks = <&clock GATE_USI07>, <&clock USI07>;
clock-names = "gate_pclk9", "gate_uart9";
status = "disabled";
};
/* USI8_UART */
serial_10: uart@108C0000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x108C0000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 408 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart10_bus_single>; /* or <&uart10_bus_dual> */
clocks = <&clock GATE_USI08>, <&clock USI08>;
clock-names = "gate_pclk10", "gate_uart10";
status = "disabled";
};
/* USI9_UART */
serial_11: uart@108E0000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x108E0000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 412 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart11_bus_single>; /* or <&uart11_bus_dual> */
clocks = <&clock GATE_USI09>, <&clock USI09>;
clock-names = "gate_pclk11", "gate_uart11";
status = "disabled";
};
/* USI10_UART */
serial_12: uart@10900000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x10900000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 416 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart12_bus_single>; /* or <&uart12_bus_dual> */
clocks = <&clock GATE_USI10>, <&clock USI10>;
clock-names = "gate_pclk12", "gate_uart12";
status = "disabled";
};
/* USI11_UART */
serial_13: uart@10920000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x10920000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 420 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart13_bus_single>; /* or <&uart13_bus_dual> */
clocks = <&clock GATE_USI11>, <&clock USI11>;
clock-names = "gate_pclk13", "gate_uart13";
status = "disabled";
};
/* USI12_UART */
serial_14: uart@10940000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x10940000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 424 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart14_bus_single>; /* or <&uart14_bus_dual> */
clocks = <&clock GATE_USI12>, <&clock USI12>;
clock-names = "gate_pclk14", "gate_uart14";
status = "disabled";
};
/* USI13_UART */
serial_15: uart@10960000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x10960000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 428 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart15_bus_single>; /* or <&uart15_bus_dual> */
clocks = <&clock GATE_USI13>, <&clock USI13>;
clock-names = "gate_pclk15", "gate_uart15";
status = "disabled";
};
/* USI_0 */
usi_0: usi@10421000 {
compatible = "samsung,exynos-usi";
reg = <0x0 0x10421000 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_1 */
usi_1: usi@10421004 {
compatible = "samsung,exynos-usi";
reg = <0x0 0x10421004 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_2 */
usi_2: usi@10421008 {
compatible = "samsung,exynos-usi";
reg = <0x0 0x10421008 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_3 */
usi_3: usi@1042100C {
compatible = "samsung,exynos-usi";
reg = <0x0 0x1042100C 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_4 */
usi_4: usi@10821008 {
compatible = "samsung,exynos-usi";
reg = <0x0 0x10821008 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_5 */
usi_5: usi@1082100C {
compatible = "samsung,exynos-usi";
reg = <0x0 0x1082100C 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_6 */
usi_6: usi@10821010 {
compatible = "samsung,exynos-usi";
reg = <0x0 0x10821010 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_7 */
usi_7: usi@10821014 {
compatible = "samsung,exynos-usi";
reg = <0x0 0x10821014 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_8 */
usi_8: usi@10821018 {
compatible = "samsung,exynos-usi";
reg = <0x0 0x10821018 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_9 */
usi_9: usi@1082101C {
compatible = "samsung,exynos-usi";
reg = <0x0 0x1082101C 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_10 */
usi_10: usi@10821020 {
compatible = "samsung,exynos-usi";
reg = <0x0 0x10821020 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_11 */
usi_11: usi@10821024 {
compatible = "samsung,exynos-usi";
reg = <0x0 0x10821024 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_12 */
usi_12: usi@10821028 {
compatible = "samsung,exynos-usi";
reg = <0x0 0x10821028 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_13 */
usi_13: usi@1082102C {
compatible = "samsung,exynos-usi";
reg = <0x0 0x1082102C 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* HSI2C_PMIC */
hsi2c_0: hsi2c@15BC0000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x15BC0000 0x1000>;
interrupts = <0 113 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c0_bus>;
clocks = <&clock UMUX_CLKCMU_BUSC_BUSPHSI2C>, <&clock GATE_HSI2CDF>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpb2 0 0x1>;
gpio_scl= <&gpb2 1 0x1>;
status = "disabled";
};
/* HSI2C_CAM0 */
hsi2c_1: hsi2c@10990000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10990000 0x1000>;
interrupts = <0 431 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c1_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_HSI2C_CAM0>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpc2 0 0x1>;
gpio_scl= <&gpc2 1 0x1>;
status = "disabled";
};
/* HSI2C_CAM1 */
hsi2c_2: hsi2c@109A0000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x109A0000 0x1000>;
interrupts = <0 432 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c2_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_HSI2C_CAM1>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpc2 2 0x1>;
gpio_scl= <&gpc2 3 0x1>;
status = "disabled";
};
/* HSI2C_CAM2 */
hsi2c_3: hsi2c@109B0000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x109B0000 0x1000>;
interrupts = <0 433 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c3_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_HSI2C_CAM2>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpc2 4 0x1>;
gpio_scl= <&gpc2 5 0x1>;
status = "disabled";
};
/* HSI2C_CAM3 */
hsi2c_4: hsi2c@109C0000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x109C0000 0x1000>;
interrupts = <0 434 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c4_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_HSI2C_CAM3>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpc2 6 0x1>;
gpio_scl= <&gpc2 7 0x1>;
status = "disabled";
};
/* HSI2C_USI0_0 */
hsi2c_5: hsi2c@10440000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10440000 0x1000>;
interrupts = <0 364 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c5_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock GATE_USI00>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpd1 0 0x1>;
gpio_scl= <&gpd1 1 0x1>;
status = "disabled";
};
/* HSI2C_USI0_1 */
hsi2c_6: hsi2c@10450000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10450000 0x1000>;
interrupts = <0 365 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c6_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock GATE_USI00>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpd1 2 0x1>;
gpio_scl= <&gpd1 3 0x1>;
status = "disabled";
};
/* HSI2C_USI1_0 */
hsi2c_7: hsi2c@10460000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10460000 0x1000>;
interrupts = <0 368 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c7_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock GATE_USI01>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpd1 4 0x1>;
gpio_scl= <&gpd1 5 0x1>;
status = "disabled";
};
/* HSI2C_USI1_1 */
hsi2c_8: hsi2c@10470000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10470000 0x1000>;
interrupts = <0 369 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c8_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock GATE_USI01>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpd1 6 0x1>;
gpio_scl= <&gpd1 7 0x1>;
status = "disabled";
};
/* HSI2C_USI2_0 */
hsi2c_9: hsi2c@10480000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10480000 0x1000>;
interrupts = <0 372 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c9_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock GATE_USI02>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpd2 0 0x1>;
gpio_scl= <&gpd2 1 0x1>;
status = "disabled";
};
/* HSI2C_USI2_1 */
hsi2c_10: hsi2c@10490000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10490000 0x1000>;
interrupts = <0 373 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c10_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock GATE_USI02>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpd2 2 0x1>;
gpio_scl= <&gpd2 3 0x1>;
status = "disabled";
};
/* HSI2C_USI3_0 */
hsi2c_11: hsi2c@104A0000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x104A0000 0x1000>;
interrupts = <0 376 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c11_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock GATE_USI03>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpd3 0 0x1>;
gpio_scl= <&gpd3 1 0x1>;
status = "disabled";
};
/* HSI2C_USI3_1 */
hsi2c_12: hsi2c@104B0000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x104B0000 0x1000>;
interrupts = <0 377 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c12_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock GATE_USI03>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpd3 2 0x1>;
gpio_scl= <&gpd3 3 0x1>;
status = "disabled";
};
/* HSI2C_USI4_0 */
hsi2c_13: hsi2c@10840000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10840000 0x1000>;
interrupts = <0 390 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c13_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI04>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe5 0 0x1>;
gpio_scl= <&gpe5 1 0x1>;
status = "disabled";
};
/* HSI2C_USI4_1 */
hsi2c_14: hsi2c@10850000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10850000 0x1000>;
interrupts = <0 391 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c14_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI04>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe5 2 0x1>;
gpio_scl= <&gpe5 3 0x1>;
status = "disabled";
};
/* HSI2C_USI5_0 */
hsi2c_15: hsi2c@10860000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10860000 0x1000>;
interrupts = <0 394 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c15_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI05>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe1 0 0x1>;
gpio_scl= <&gpe1 1 0x1>;
status = "disabled";
};
/* HSI2C_USI5_1 */
hsi2c_16: hsi2c@10870000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10870000 0x1000>;
interrupts = <0 395 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c16_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI05>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe1 2 0x1>;
gpio_scl= <&gpe1 3 0x1>;
status = "disabled";
};
/* HSI2C_USI6_0 */
hsi2c_17: hsi2c@10880000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10880000 0x1000>;
interrupts = <0 398 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c17_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI06>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe1 4 0x1>;
gpio_scl= <&gpe1 5 0x1>;
status = "disabled";
};
/* HSI2C_USI6_1 */
hsi2c_18: hsi2c@10890000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10890000 0x1000>;
interrupts = <0 399 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c18_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI06>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe1 6 0x1>;
gpio_scl= <&gpe1 7 0x1>;
status = "disabled";
};
/* HSI2C_USI7_0 */
hsi2c_19: hsi2c@108A0000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x108A0000 0x1000>;
interrupts = <0 402 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c19_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI07>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe2 0 0x1>;
gpio_scl= <&gpe2 1 0x1>;
status = "disabled";
};
/* HSI2C_USI7_1 */
hsi2c_20: hsi2c@108B0000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x108B0000 0x1000>;
interrupts = <0 403 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c20_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI07>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe2 2 0x1>;
gpio_scl= <&gpe2 3 0x1>;
status = "disabled";
};
/* HSI2C_USI8_0 */
hsi2c_21: hsi2c@108C0000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x108C0000 0x1000>;
interrupts = <0 406 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c21_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI08>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe2 4 0x1>;
gpio_scl= <&gpe2 5 0x1>;
status = "disabled";
};
/* HSI2C_USI8_1 */
hsi2c_22: hsi2c@108D0000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x108D0000 0x1000>;
interrupts = <0 407 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c22_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI08>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe2 6 0x1>;
gpio_scl= <&gpe2 7 0x1>;
status = "disabled";
};
/* HSI2C_USI9_0 */
hsi2c_23: hsi2c@108E0000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x108E0000 0x1000>;
interrupts = <0 410 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c23_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI09>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe3 0 0x1>;
gpio_scl= <&gpe3 1 0x1>;
status = "disabled";
};
/* HSI2C_USI9_1 */
hsi2c_24: hsi2c@108F0000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x108F0000 0x1000>;
interrupts = <0 411 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c24_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI09>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe3 2 0x1>;
gpio_scl= <&gpe3 3 0x1>;
status = "disabled";
};
/* HSI2C_USI10_0 */
hsi2c_25: hsi2c@10900000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10900000 0x1000>;
interrupts = <0 414 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c25_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI10>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe3 4 0x1>;
gpio_scl= <&gpe3 5 0x1>;
status = "disabled";
};
/* HSI2C_USI10_1 */
hsi2c_26: hsi2c@10910000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10910000 0x1000>;
interrupts = <0 415 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c26_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI10>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe3 6 0x1>;
gpio_scl= <&gpe3 7 0x1>;
status = "disabled";
};
/* HSI2C_USI11_0 */
hsi2c_27: hsi2c@10920000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10920000 0x1000>;
interrupts = <0 418 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c27_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI11>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe4 0 0x1>;
gpio_scl= <&gpe4 1 0x1>;
status = "disabled";
};
/* HSI2C_USI11_1 */
hsi2c_28: hsi2c@10930000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10930000 0x1000>;
interrupts = <0 419 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c28_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI11>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe4 2 0x1>;
gpio_scl= <&gpe4 3 0x1>;
status = "disabled";
};
/* HSI2C_USI12_0 */
hsi2c_29: hsi2c@10940000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10940000 0x1000>;
interrupts = <0 422 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c29_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI12>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe4 4 0x1>;
gpio_scl= <&gpe4 5 0x1>;
status = "disabled";
};
/* HSI2C_USI12_1 */
hsi2c_30: hsi2c@10950000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10950000 0x1000>;
interrupts = <0 423 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c30_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI12>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe4 6 0x1>;
gpio_scl= <&gpe4 7 0x1>;
status = "disabled";
};
/* HSI2C_USI13_0 */
hsi2c_31: hsi2c@10960000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10960000 0x1000>;
interrupts = <0 426 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c31_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI13>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe5 4 0x1>;
gpio_scl= <&gpe5 5 0x1>;
status = "disabled";
};
/* HSI2C_USI13_1 */
hsi2c_32: hsi2c@10970000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x10970000 0x1000>;
interrupts = <0 427 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c32_bus>;
clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI13>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpe5 6 0x1>;
gpio_scl= <&gpe5 7 0x1>;
status = "disabled";
};
/* SPI CAM_0 */
spi_0: spi@109D0000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x109D0000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 435 0>;
/*
To use DMA in SPI CAM_0, do not use DMA in SPI USI_13.
dma-mode;
dmas = <&pdma0 31 1
&pdma0 30 1>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_SPI_CAM0>, <&clock DOUT_CLKCMU_PERIC1_SPI_CAM0>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi0_bus>;
status = "disabled";
};
/* SPI CAM_1 */
spi_1: spi@109E0000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x109E0000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 436 0>;
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_SPI_CAM1>, <&clock DOUT_CLKCMU_PERIC1_SPI_CAM1>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
status = "disabled";
};
/* SPI USI_0 */
spi_2: spi@10440000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x10440000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 367 0>;
/*
dma-mode;
dmas = <&pdma0 1 0
&pdma0 0 0>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI00>, <&clock USI00>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi2_bus>;
status = "disabled";
};
/* SPI USI_1 */
spi_3: spi@10460000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x10460000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 371 0>;
/*
dma-mode;
dmas = <&pdma0 3 0
&pdma0 2 0>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI01>, <&clock USI01>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi3_bus>;
status = "disabled";
};
/* SPI USI_2 */
spi_4: spi@10480000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x10480000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 375 0>;
/*
dma-mode;
dmas = <&pdma0 5 0
&pdma0 4 0>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI02>, <&clock USI02>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi4_bus>;
status = "disabled";
};
/* SPI USI_3 */
spi_5: spi@104A0000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x104A0000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 379 0>;
/*
dma-mode;
dmas = <&pdma0 7 0
&pdma0 6 0>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI03>, <&clock USI03>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi5_bus>;
status = "disabled";
};
/* SPI USI_4 */
spi_6: spi@10840000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x10840000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 393 0>;
/*
dma-mode;
dmas = <&pdma0 13 0
&pdma0 12 0>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI04>, <&clock USI04>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi6_bus>;
status = "disabled";
};
/* SPI USI_5 */
spi_7: spi@10860000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x10860000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 397 0>;
/*
dma-mode;
dmas = <&pdma0 15 0
&pdma0 14 0>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI05>, <&clock USI05>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi7_bus>;
status = "disabled";
};
/* SPI USI_6 */
spi_8: spi@10880000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x10880000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 401 0>;
/*
dma-mode;
dmas = <&pdma0 17 0
&pdma0 16 0>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI06>, <&clock USI06>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi8_bus>;
status = "disabled";
};
/* SPI USI_7 */
spi_9: spi@108A0000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x108A0000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 405 0>;
/*
dma-mode;
dmas = <&pdma0 19 0
&pdma0 18 0>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI07>, <&clock USI07>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi9_bus>;
status = "disabled";
};
/* SPI USI_8 */
spi_10: spi@108C0000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x108C0000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 409 0>;
/*
dma-mode;
dmas = <&pdma0 21 0
&pdma0 20 0>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI08>, <&clock USI08>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi10_bus>;
status = "disabled";
};
/* SPI USI_9 */
spi_11: spi@108E0000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x108E0000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 413 0>;
/*
dma-mode;
dmas = <&pdma0 23 0
&pdma0 22 0>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI09>, <&clock USI09>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi11_bus>;
status = "disabled";
};
/* SPI USI_10 */
spi_12: spi@10900000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x10900000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 417 0>;
/*
dma-mode;
dmas = <&pdma0 25 0
&pdma0 24 0>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI10>, <&clock USI10>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi12_bus>;
status = "disabled";
};
/* SPI USI_11 */
spi_13: spi@10920000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x10920000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 421 0>;
/*
dma-mode;
dmas = <&pdma0 27 0
&pdma0 26 0>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI11>, <&clock USI11>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi13_bus>;
status = "disabled";
};
/* SPI USI_12 */
spi_14: spi@10940000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x10940000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 425 0>;
/*
dma-mode;
dmas = <&pdma0 29 0
&pdma0 28 0>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI12>, <&clock USI12>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi14_bus>;
status = "disabled";
};
/* SPI USI_13 */
spi_15: spi@10960000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x10960000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 429 0>;
/*
To use DMA in SPI USI_13, do not use DMA in SPI CAM_0.
dma-mode;
dmas = <&pdma0 31 0
&pdma0 30 0>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI13>, <&clock USI13>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi15_bus>;
status = "disabled";
};
acpm {
compatible = "samsung,exynos-acpm";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x0 0x16488000 0x1000>; /* PMU_ALIVE */
acpm-ipc-channel = <4>;
};
acpm_ipc {
compatible = "samsung,exynos-acpm-ipc";
#address-cells = <2>;
#size-cells = <1>;
interrupts = <0 39 0>;
reg = <0x0 0x16440000 0x1000>, /* AP2APM MAILBOX */
<0x0 0x16500000 0xB400>; /* APM SRAM */
initdata-base = <0x2850>;
num-timestamps = <32>;
debug-log-level = <0>;
logging-period = <500>;
dump-base = <0x16500000>;
dump-size = <0xB400>;
};
acpm_dvfs {
compatible = "samsung,exynos-acpm-dvfs";
acpm-ipc-channel = <5>;
cpu_cold_temp_list = <ACPM_DVFS_MIF>, <ACPM_DVFS_INT>,
<ACPM_DVFS_CPUCL0>, <ACPM_DVFS_CPUCL1>,
<ACPM_DVFS_INTCAM>, <ACPM_DVFS_CAM>,
<ACPM_DVFS_DISP>;
gpu_cold_temp_list = <ACPM_DVFS_G3D>;
};
smc_info: mcinfo@160300000 {
compatible = "samsung,exynos-mcinfo";
reg = <0x0 0x1603004C 0x4>,
<0x0 0x1613004C 0x4>,
<0x0 0x1623004C 0x4>,
<0x0 0x1633004C 0x4>;
bit_field = <20 4>;
/* start bit, width */
basecnt = <4>;
irqcnt = <4>;
interrupts = <0 115 0>, <0 122 0>, <0 129 0>, <0 136 0>;
};
devfreq_0: devfreq_mif@17000010 {
compatible = "samsung,exynos-devfreq";
reg = <0x0 0x17000010 0x0>;
devfreq_type = "mif";
devfreq_domain_name = "dvfs_mif";
/* Delay time */
use_delay_time = "true";
delay_time_list = "20";
freq_info = <2093000 208000 1014000 208000 2093000 421000>;
/* initial_freq, default_qos, suspend_freq, min_freq, max_freq reboot_freq */
/* Booting value */
boot_info = <40 1794000>;
/* boot_qos_timeout, boot_freq */
use_get_dev = "false";
polling_ms = <0>;
/* governor data */
gov_name = "interactive";
use_reg = "false";
use_tmu = "true";
use_cl_dvfs = "false";
use_sw_clk = "false";
dfs_id = <ACPM_DVFS_MIF>;
acpm-ipc-channel = <1>;
use_acpm = "true";
};
devfreq_1: devfreq_int@17000020 {
compatible = "samsung,exynos-devfreq";
reg = <0x0 0x17000020 0x0>;
devfreq_type = "int";
devfreq_domain_name = "dvfs_int";
/* Delay time */
use_delay_time = "false";
freq_info = <667000 178000 107000 107000 667000 667000>;
/* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
/* Booting value */
boot_info = <40 667000>;
/* boot_qos_timeout, boot_freq */
/* default_dev_profile */
use_get_dev = "false";
polling_ms = <0>;
/* governor data */
gov_name = "interactive";
use_reg = "false";
use_tmu = "true";
use_cl_dvfs = "false";
use_sw_clk = "false";
dfs_id = <ACPM_DVFS_INT>;
acpm-ipc-channel = <1>;
use_acpm = "true";
};
devfreq_2: devfreq_intcam@17000030 {
compatible = "samsung,exynos-devfreq";
reg = <0x0 0x17000030 0x0>;
devfreq_type = "intcam";
devfreq_domain_name = "dvfs_intcam";
/* Delay time */
use_delay_time = "false";
freq_info = <690000 640000 690000 640000 690000 690000>;
/* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
/* Booting value */
boot_info = <40 640000>;
/* boot_qos_timeout, boot_freq */
/* default_dev_profile */
use_get_dev = "false";
polling_ms = <0>;
/* governor data */
gov_name = "interactive";
use_reg = "false";
use_tmu = "true";
use_cl_dvfs = "false";
use_sw_clk = "false";
dfs_id = <ACPM_DVFS_INTCAM>;
};
devfreq_3: devfreq_disp@17000040 {
compatible = "samsung,exynos-devfreq";
reg = <0x0 0x17000040 0x0>;
devfreq_type = "disp";
devfreq_domain_name = "dvfs_disp";
/* Delay time */
use_delay_time = "false";
freq_info = <630000 134000 630000 134000 630000 630000>;
/* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
/* Booting value */
boot_info = <40 630000>;
/* boot_qos_timeout, boot_freq */
/* default dev profile */
use_get_dev = "false";
polling_ms = <0>;
/* governor data */
gov_name = "interactive";
use_reg = "false";
use_tmu = "true";
use_cl_dvfs = "false";
use_sw_clk = "false";
dfs_id = <ACPM_DVFS_DISP>;
};
devfreq_4: devfreq_cam@17000050 {
compatible = "samsung,exynos-devfreq";
reg = <0x0 0x17000050 0x0>;
devfreq_type = "cam";
devfreq_domain_name = "dvfs_cam";
/* Delay time */
use_delay_time = "false";
freq_info = <690000 630000 690000 630000 690000 690000>;
/* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
/* Booting value */
boot_info = <40 630000>;
/* boot_qos_timeout, boot_freq */
/* default dev profile */
use_get_dev = "false";
polling_ms = <0>;
/* governor data */
gov_name = "interactive";
use_reg = "false";
use_tmu = "true";
use_cl_dvfs = "false";
use_sw_clk = "false";
dfs_id = <ACPM_DVFS_CAM>;
};
exynos_dm: exynos-dm@17000000 {
compatible = "samsung,exynos-dvfs-manager";
reg = <0x0 0x17000000 0x0>;
acpm-ipc-channel = <1>;
cpufreq_cl0 {
dm-index = <DM_CPU_CL0>;
available = "true";
cal_id = <ACPM_DVFS_CPUCL0>;
};
cpufreq_cl1 {
dm-index = <DM_CPU_CL1>;
available = "true";
cal_id = <ACPM_DVFS_CPUCL1>;
};
devfreq_mif {
dm-index = <DM_MIF>;
available = "true";
policy_use = "true";
cal_id = <ACPM_DVFS_MIF>;
};
devfreq_int {
dm-index = <DM_INT>;
available = "true";
policy_use = "true";
cal_id = <ACPM_DVFS_INT>;
};
devfreq_intcam {
dm-index = <DM_INTCAM>;
available = "true";
cal_id = <ACPM_DVFS_INTCAM>;
};
devfreq_disp {
dm-index = <DM_DISP>;
available = "true";
cal_id = <ACPM_DVFS_DISP>;
};
devfreq_cam {
dm-index = <DM_CAM>;
available = "true";
cal_id = <ACPM_DVFS_CAM>;
};
dvfs_gpu {
dm-index = <DM_GPU>;
available = "false";
cal_id = <ACPM_DVFS_G3D>;
};
};
fimg2d_0: fimg2d@15100000 {
compatible = "samsung,s5p-fimg2d";
reg = <0x0 0x13A30000 0x1000>;
interrupts = <0 224 0>;
clocks = <&clock GATE_G2D>;
clock-names="gate";
samsung,power-domain = <&pd_g2d>;
iommus = <&sysmmu_g2d_0>, <&sysmmu_g2d_1>;
hw_ppc = <2800>, <2400>, <3800>;
/* cluster1 cluster0 mif */
skia_qos_table = <0 0 1014000
0 0 1014000
0 0 845000
0 0 845000
0 0 676000
0 0 0
>;
};
sysmmu_g2d_0: sysmmu@13A60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x13A60000 0x3000>;
interrupts = <0 215 0>, <0 216 0>;
clock-names = "aclk";
clocks = <&clock GATE_SMMU_G2DD0>;
port-name = "G2D0";
sysmmu,secure-irq;
sysmmu,secure_base = <0x13A80000>;
#iommu-cells = <0>;
};
sysmmu_g2d_1: sysmmu@13A70000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x13A70000 0x3000>;
interrupts = <0 218 0>, <0 219 0>;
clock-names = "aclk";
clocks = <&clock GATE_SMMU_G2DD1>;
port-name = "G2D1";
sysmmu,secure-irq;
sysmmu,secure_base = <0x13A90000>;
#iommu-cells = <0>;
};
/* SPEEDY IP_BATCHER_AP */
speedy@15B50000 {
compatible = "samsung,exynos-speedy";
reg = <0x0 0x15B50000 0x2000>;
interrupts = <0 109 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&speedy_bus>;
clocks = <&clock GATE_SPEEDY_BATCHER_WRAP_BATCHER_AP>;
clock-names = "gate_speedy";
status = "disabled";
};
vpu: vpu@13300000 {
compatible = "samsung,exynos-vpu";
#pb-id-cells = <4>;
reg = <0x0 0x133C0000 0x20000>, /* RAM0 */
<0x0 0x133E0000 0x20000>, /* RAM1 */
<0x0 0x13380000 0x20000>, /* CODE */
<0x0 0x13300000 0x50000>; /* APB */
interrupts = <0 190 0>, <0 191 0>;
samsung,power-domain = <&pd_vpu>;
clocks = <&clock GATE_VPU>;
clock-names = "vpu";
iommus = <&sysmmu_vpu>;
};
iommu-domain_vpu {
compatible = "samsung,exynos-iommu-bus";
#dma-address-cells = <1>;
#dma-size-cells = <1>;
/* start address, size */
dma-window = <0x30000000 0xA0000000>;
domain-clients = <&vpu>;
};
sysmmu_vpu: sysmmu@13250000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x13250000 0x3000>;
interrupts = <0 194 0>, <0 195 0>;
qos = <15>;
clock-names = "aclk";
clocks = <&clock GATE_SMMU_VPU>;
port-name = "VPU";
sysmmu,secure-irq;
sysmmu,secure_base = <0x13240000>;
sysmmu,tlb_property =
<(SYSMMU_PUBLIC_NO_PREFETCH | SYSMMU_BL8) SYSMMU_NOID>;
#iommu-cells = <0>;
};
iommu-domain_disp {
compatible = "samsung,exynos-iommu-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges;
domain-clients = <&idma_g0>, <&idma_g1>, <&idma_vg0>, <&idma_vg1>,
<&idma_vgf0>, <&idma_vgf1>, <&odma_wb>;
};
sysmmu_dpu0: sysmmu@12900000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x12900000 0x3000>;
interrupts = <0 152 0>, <0 153 0>;
qos = <15>;
clock-names = "aclk";
clocks = <&clock GATE_SYSMMU_DPUD0>;
port-name = "DPU0 (VGR, VGF)";
sysmmu,secure-irq;
sysmmu,secure_base = <0x12930000>;
sysmmu,tlb_property =
/* 0~1 : VGR */
<(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL16) SYSMMU_ID_MASK(0x100, 0x180)>,
<(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL16) SYSMMU_ID_MASK(0x180, 0x180)>,
/* 2~3 : VGF */
<(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_READ | SYSMMU_BL8) SYSMMU_ID_MASK(0x0, 0x180)>,
<(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_READ | SYSMMU_BL8) SYSMMU_ID_MASK(0x80, 0x180)>;
#iommu-cells = <0>;
};
sysmmu_dpu1: sysmmu@12910000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x12910000 0x3000>;
interrupts = <0 155 0>, <0 156 0>;
qos = <15>;
clock-names = "aclk";
clocks = <&clock GATE_SYSMMU_DPUD1>;
port-name = "DPU1 (G0, VG0)";
sysmmu,secure-irq;
sysmmu,secure_base = <0x12940000>;
sysmmu,tlb_property =
/* 0 : G0 */
<(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_READ | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x600)>,
/* 1~2 : VG0 */
<(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_READ | SYSMMU_BL1) SYSMMU_ID_MASK(0x400, 0x600)>,
<(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_READ | SYSMMU_BL1) SYSMMU_ID_MASK(0x600, 0x600)>;
#iommu-cells = <0>;
};
sysmmu_dpu2: sysmmu@12920000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x12920000 0x3000>;
interrupts = <0 158 0>, <0 159 0>;
qos = <15>;
clock-names = "aclk";
clocks = <&clock GATE_SYSMMU_DPUD2>;
port-name = "DPU2 (G1, VG1, WB)";
sysmmu,secure-irq;
sysmmu,secure_base = <0x12950000>;
sysmmu,tlb_property =
/* 0 : G1 */
<(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_READ | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x600)>,
/* 1~2 : VG1 */
<(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_READ | SYSMMU_BL1) SYSMMU_ID_MASK(0x400, 0x600)>,
<(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_READ | SYSMMU_BL1) SYSMMU_ID_MASK(0x600, 0x600)>,
/* 3~4 : WB */
<(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_WRITE | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x100)>,
<(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_WRITE | SYSMMU_BL1) SYSMMU_ID_MASK(0x100, 0x100)>;
#iommu-cells = <0>;
};
idma_g0: dpp@0x12851000{
compatible = "samsung,exynos8-dpp";
#pb-id-cells = <3>;
reg = <0x0 0x12851000 0x1000>, <0x0 0x128B1000 0x1000>, <0x0 0x128B0000 0x100>;
interrupts = <0 183 0>, <0 179 0>;
iommus = <&sysmmu_dpu1>;
/* power domain */
samsung,power-domain = <&pd_dpu0>;
};
idma_g1: dpp@0x12852000{
compatible = "samsung,exynos8-dpp";
#pb-id-cells = <6>;
reg = <0x0 0x12852000 0x1000>, <0x0 0x128B2000 0x1000>, <0x0 0x128B0000 0x100>;
interrupts = <0 184 0>, <0 181 0>;
iommus = <&sysmmu_dpu2>;
/* power domain */
samsung,power-domain = <&pd_dpu0>;
};
idma_vg0: dpp@0x12853000{
compatible = "samsung,exynos8-dpp";
#pb-id-cells = <3>;
reg = <0x0 0x12853000 0x1000>, <0x0 0x128B3000 0x1000>, <0x0 0x128B0000 0x100>;
interrupts = <0 185 0>, <0 180 0>;
iommus = <&sysmmu_dpu1>;
/* power domain */
samsung,power-domain = <&pd_dpu0>;
};
idma_vg1: dpp@0x12854000{
compatible = "samsung,exynos8-dpp";
#pb-id-cells = <3>;
reg = <0x0 0x12854000 0x1000>, <0x0 0x128B4000 0x1000>, <0x0 0x128B0000 0x100>;
interrupts = <0 186 0>, <0 182 0>;
iommus = <&sysmmu_dpu2>;
/* power domain */
samsung,power-domain = <&pd_dpu0>;
};
idma_vgf0: dpp@0x12855000{
compatible = "samsung,exynos8-dpp";
#pb-id-cells = <3>;
reg = <0x0 0x12855000 0x1000>, <0x0 0x128B5000 0x1000>, <0x0 0x128B0000 0x100>;
interrupts = <0 188 0>, <0 177 0>;
iommus = <&sysmmu_dpu0>;
/* power domain */
samsung,power-domain = <&pd_dpu0>;
};
idma_vgf1: dpp@0x12856000{
compatible = "samsung,exynos8-dpp";
#pb-id-cells = <3>;
reg = <0x0 0x12856000 0x1000>, <0x0 0x128B6000 0x1000>, <0x0 0x128B0000 0x100>;
interrupts = <0 187 0>, <0 178 0>;
iommus = <&sysmmu_dpu0>;
/* power domain */
samsung,power-domain = <&pd_dpu0>;
};
odma_wb: dpp@0x12890000{
compatible = "samsung,exynos8-dpp";
#pb-id-cells = <3>;
reg = <0x0 0x12890000 0x1000>, <0x0 0x128B7000 0x1000>, <0x0 0x128B0000 0x100>;
interrupts = <0 189 0>;
iommus = <&sysmmu_dpu2>;
/* power domain */
samsung,power-domain = <&pd_dpu0>;
};
ion {
compatible = "samsung,exynos5430-ion";
};
disp_ss: disp_ss@0x12820000 {
compatible = "samsung,exynos8-disp_ss";
reg = <0x0 0x12821000 0x10>;
};
disp_ver: disp_ver@0x10000010 {
compatible = "samsung,exynos8-disp-ver";
reg = <0x0 0x10000010 0x4>;
};
mipi_phy_dsim: phy_m4s4_dsi@0x12821008 {
compatible = "samsung,mipi-phy-m4s4-mod";
samsung,pmu-syscon = <&pmu_system_controller>;
isolation = <0x710>;
/* PHY reset be controlled from DSIM */
/* reg = <0x0 0x12821008 0x4>; */
/* reset = <0 1>; */
/* init = <4 5>; */ /* PHY reset control path bit of SYSREG */
owner = <0>; /* 0: DSI, 1: CSI */
#phy-cells = <1>;
};
dsim_0: dsim@0x12870000 {
compatible = "samsung,exynos8-dsim";
reg = <0x0 0x12870000 0x100>;
interrupts = <0 150 0>;
phys = <&mipi_phy_dsim 0>;
phy-names = "dsim_dphy";
/* power domain */
samsung,power-domain = <&pd_dpu1>;
};
displayport_phy: displayport_phy@11090904 {
compatible = "samsung,displayport-phy";
samsung,pmu-syscon = <&pmu_system_controller>;
isolation = <0x072C>;
#phy-cells = <1>;
};
displayport: displayport@0x11090000 {
compatible = "samsung,exynos-displayport";
reg = <0x0 0x11090000 0xFFFF>;
interrupts = <0 340 0>;
phys = <&displayport_phy 0>;
phy-names = "displayport_phy";
};
displayport_adma: displayport_adma@0x15A40000 {
compatible = "samsung,displayport-adma";
reg = <0x0 0x15A40000 0x1000>;
interrupt = <0 107 0>;
clocks = <&clock GATE_PDMA0>;
clock-names = "apb_pclk";
/* dma-mode; */
dmas = <&pdma0 9 0>;
dma-names = "tx";
};
decon_f: decon_f@0x12860000 {
compatible = "samsung,exynos8-decon";
#pb-id-cells = <4>;
reg = <0x0 0x12860000 0x10000>;
/* interrupt num */
interrupts = <0 142 0>, <0 143 0>, <0 144 0>, <0 149 0>, <0 430 0>,
<0 145 0>, <0 146 0>, <0 147 0>, <0 148 0>;
/* clock */
clock-names = "aclk";
clocks = <&clock GATE_DECON0>;
/* pinctrl */
pinctrl-names = "hw_te_on", "hw_te_off";
pinctrl-0 = <&decon_f_te_on>;
pinctrl-1 = <&decon_f_te_off>;
/* power domain */
samsung,power-domain = <&pd_dpu0>;
max_win = <6>;
default_win = <5>;
default_idma = <0>;
psr_mode = <2>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */
trig_mode = <0>; /* 0: hw trigger, 1: sw trigger */
dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */
/* 0: DSI, 1: eDP, 2:HDMI, 3: WB */
out_type = <0>;
/* 0: DSI0, 1: DSI1, 2: DSI2 */
out_idx = <0>;
#address-cells = <2>;
#size-cells = <1>;
ranges;
/* EINT for TE */
gpios = <&gpb0 1 0xf>;
/* sw te pending register */
te_eint {
/* NWEINT_GPB0_PEND (GPB0_0:TE_T, GPB0_1:TE_F, GPB0_2:TE_S) */
reg = <0x0 0x10980a00 0x4>;
};
cam-stat {
reg = <0x0 0x16484024 0x4>;
};
};
decon_s: decon_s@0x12A30000 {
compatible = "samsung,exynos8-decon";
#pb-id-cells = <4>;
reg = <0x0 0x12A30000 0x8000>;
/* interrupt num */
interrupts = <0 167 0>, <0 168 0>, <0 169 0>, <0 170 0>;
/* clock */
clock-names = "aclk", "busd", "busp";
clocks = <&clock GATE_DECON0>, <&clock UMUX_CLKCMU_DPU1_BUSD>,
<&clock UMUX_CLKCMU_DPU1_BUSP>;
/* power domain */
samsung,power-domain = <&pd_dpu1>;
max_win = <5>;
default_win = <3>;
default_idma = <2>;
psr_mode = <2>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */
trig_mode = <1>; /* 0: hw trigger, 1: sw trigger */
dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */
/* 0: DSI, 1: eDP, 2:DP, 3: WB */
out_type = <3>;
/* 0: DSI0, 1: DSI1, 2: DSI2 */
out_idx = <0>;
#address-cells = <2>;
#size-cells = <1>;
ranges;
};
decon_t: decon_t@0x12A40000 {
compatible = "samsung,exynos8-decon";
#pb-id-cells = <4>;
reg = <0x0 0x12A40000 0x8000>;
/* interrupt num */
interrupts = <0 171 0>, <0 172 0>, <0 173 0>, <0 174 0>, <0 175 0>;
/* clock */
clock-names = "aclk", "busd", "busp", "busc", "core";
clocks = <&clock GATE_DECON0>, <&clock UMUX_CLKCMU_DPU1_BUSD>,
<&clock UMUX_CLKCMU_DPU1_BUSP>, <&clock GATE_TREX_BUSC>, <&clock GATE_TREX_CORE>;
/* power domain */
samsung,power-domain = <&pd_dpu1>;
max_win = <5>;
default_win = <3>;
default_idma = <2>;
psr_mode = <0>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */
trig_mode = <1>; /* 0: hw trigger, 1: sw trigger */
dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */
/* 0: DSI, 1: eDP, 2:DP, 3: WB */
out_type = <2>;
/* 0: DSI0, 1: DSI1, 2: DSI2 */
out_idx = <0>;
#address-cells = <2>;
#size-cells = <1>;
ranges;
};
smfc: smfc@13B00000 {
compatible = "samsung,exynos8890-jpeg";
dma-coherent;
reg = <0x0 0x13B00000 0x1000>;
interrupts = <0 225 0>;
clocks = <&clock GATE_JPEG>;
clock-names = "gate";
iommus = <&sysmmu_g2d_2>;
samsung,power-domain = <&pd_g2d>;
};
exynos_adc: adc@15B70000 {
compatible = "samsung,exynos-adc-v3";
reg = <0x0 0x15B70000 0x100>;
interrupts = <0 104 0>;
#io-channel-cells = <1>;
io-channel-ranges;
clocks = <&clock GATE_ADCIF_BUSC_S0>;
clock-names = "gate_adcif";
};
scaler_0: scaler@0x13B10000 {
compatible = "samsung,exynos5-scaler";
dma-coherent;
reg = <0x0 0x13B10000 0x1300>;
interrupts = <0 226 0>;
clocks = <&clock GATE_M2MSCALER>;
clock-names = "gate";
iommus = <&sysmmu_g2d_2>;
samsung,power-domain = <&pd_g2d>;
};
ima: ima@0x1C000000 {
compatible = "samsung,exynos-ima";
reg = <0x0 0x13780000 0x80000>, /* CPU path */
<0x0 0x1C000000 0x80000>, /* DMA path */
<0x0 0x13520000 0x2000>, /* Sysreg */
<0x0 0x136D0000 0x1000>; /* Pre-register */
clocks = <&clock GATE_IVA_INTMEM>;
clock-names = "gate";
samsung,power-domain = <&pd_iva>;
};
iommu-domain_g2d {
compatible = "samsung,exynos-iommu-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges;
domain-clients = <&fimg2d_0>;
};
iommu-domain_smfc_scaler {
compatible = "samsung,exynos-iommu-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges;
domain-clients = <&smfc>, <&scaler_0>;
};
sysmmu_g2d_2: sysmmu@13B50000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x13B50000 0x3000>;
interrupts = <0 221 0>, <0 222 0>;
clock-names = "aclk";
clocks = <&clock GATE_SMMU_G2DD2>;
port-name = "Scaler, SMFC";
sysmmu,secure-irq;
sysmmu,secure_base = <0x13B60000>;
sysmmu,tlb_property =
/* 0~5 : M2MScaler */
<(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL32) SYSMMU_ID(0x1)>,
<(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL32) SYSMMU_ID(0x3)>,
<(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL32) SYSMMU_ID(0x5)>,
<(SYSMMU_PRIV_ID_NO_PREFETCH_WRITE | SYSMMU_BL32) SYSMMU_ID(0x11)>,
<(SYSMMU_PRIV_ID_NO_PREFETCH_WRITE | SYSMMU_BL32) SYSMMU_ID(0x13)>,
<(SYSMMU_PRIV_ID_NO_PREFETCH_WRITE | SYSMMU_BL32) SYSMMU_ID(0x15)>,
/* 6~9 : SMFC */
<(SYSMMU_PRIV_ADDR_NO_PREFETCH_READWRITE | SYSMMU_BL32) SYSMMU_NOID>,
<(SYSMMU_PRIV_ADDR_NO_PREFETCH_READWRITE | SYSMMU_BL32) SYSMMU_NOID>,
<(SYSMMU_PRIV_ADDR_NO_PREFETCH_READWRITE | SYSMMU_BL32) SYSMMU_NOID>,
<(SYSMMU_PRIV_ADDR_NO_PREFETCH_WRITE | SYSMMU_BL32) SYSMMU_NOID>;
#iommu-cells = <0>;
};
watchdog@10060000 {
compatible = "samsung,exynos8-wdt";
reg = <0x0 0x10060000 0x100>;
interrupts = <0 454 0>;
clocks = <&clock OSCCLK>, <&clock UMUX_CLKCMU_PERIS_BUS>;
clock-names = "rate_watchdog", "gate_watchdog";
timeout-sec = <30>;
samsung,syscon-phandle = <&pmu_system_controller>;
};
dwmmc_2: dwmmc2@11500000 {
compatible = "samsung,exynos-dw-mshc";
reg = <0x0 0x11500000 0x2000>;
interrupts = <0 341 0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock MMC_CARD>, <&clock GATE_MMC_CARD>;
clock-names = "ciu", "ciu_gate";
status = "disabled";
};
sec_pwm: pwm@104c0000 {
compatible = "samsung,s3c6400-pwm";
reg = <0x0 0x104c0000 0x1000>;
samsung,pwm-outputs = <0>, <1>, <2>, <3>, <4>;
#pwm-cells = <3>;
clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>,
<&clock_pwm 1>, <&clock_pwm 2>,
<&clock_pwm 5>, <&clock_pwm 6>,
<&clock_pwm 7>, <&clock_pwm 8>,
<&clock_pwm 10>, <&clock_pwm 11>,
<&clock_pwm 12>, <&clock_pwm 13>;
clock-names = "gate_timers",
"pwm-scaler0", "pwm-scaler1",
"pwm-tdiv0", "pwm-tdiv1",
"pwm-tdiv2", "pwm-tdiv3",
"pwm-tin0", "pwm-tin1",
"pwm-tin2", "pwm-tin3";
status = "ok";
};
clock_pwm: pwm-clock-controller@104c0000 {
compatible = "samsung,exynos-pwm-clock";
reg = <0x0 0x104c0000 0x50>;
#clock-cells = <1>;
};
coresight@17000000 {
compatible = "exynos,coresight";
base = <0x17000000>;
sj-offset = <0x6000>;
/* coresight component count */
funnel-num = <3>;
etf-num = <2>;
cl0_cpu0@400000 {
device_type = "cs";
dbg-offset = <0x410000>;
etm-offset = <0x440000>;
funnel-port = <0 0>;
};
cl0_cpu1@500000 {
device_type = "cs";
dbg-offset = <0x510000>;
etm-offset = <0x540000>;
funnel-port = <0 1>;
};
cl0_cpu2@600000 {
device_type = "cs";
dbg-offset = <0x610000>;
etm-offset = <0x640000>;
funnel-port = <0 2>;
};
cl0_cpu3@700000 {
device_type = "cs";
dbg-offset = <0x710000>;
etm-offset = <0x740000>;
funnel-port = <0 3>;
};
cl1_cpu0@800000 {
device_type = "cs";
dbg-offset = <0x810000>;
etm-offset = <0x840000>;
funnel-port = <1 0>;
};
cl1_cpu1@900000 {
device_type = "cs";
dbg-offset = <0x910000>;
etm-offset = <0x940000>;
funnel-port = <1 1>;
};
cl1_cpu2@A00000 {
device_type = "cs";
dbg-offset = <0xA10000>;
etm-offset = <0xA40000>;
funnel-port = <1 2>;
};
cl1_cpu3@B00000 {
device_type = "cs";
dbg-offset = <0xB10000>;
etm-offset = <0xB40000>;
funnel-port = <1 3>;
};
cs_etf0: cs_etf0@C000 {
device_type = "etf";
offset = <0x4000>;
funnel-port = <2 0>;
};
cs_etf1: cs_etf1@5000 {
device_type = "etf";
offset = <0x5000>;
funnel-port = <2 1>;
};
cs_funnel0@4000 {
device_type = "funnel";
offset = <0x7000>;
};
cs_funnel1@9000 {
device_type = "funnel";
offset = <0x8000>;
};
cs_funnelm2@9000 {
device_type = "funnel";
offset = <0x9000>;
};
cs_etr@B000 {
device_type = "etr";
offset = <0xA000>;
};
};
udc: usb@10C00000 {
compatible = "samsung,exynos8895-dwusb3";
clocks = <&clock GATE_USBTV_USB30DRD_LINK>, <&clock USBDRD30>;
clock-names = "aclk", "sclk";
reg = <0x0 0x10C00000 0x10000>;
#address-cells = <2>;
#size-cells = <1>;
ranges;
status = "disabled";
usbdrd_dwc3: dwc3 {
compatible = "synopsys,dwc3";
reg = <0x0 0x10C00000 0x10000>;
interrupts = <0 337 0>;
is_not_vbus_pad;
suspend_clk_freq = <66000000>;
enable_sprs_transfer;
phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
phy-names = "usb2-phy", "usb3-phy";
};
};
usbdrd_phy0: phy@10E00000 {
compatible = "samsung,exynos8895-usbdrd-phy";
reg = <0x0 0x10E00000 0x100>,
<0x0 0x10E10000 0x100>;
clocks = <&clock OSCCLK>, <&clock GATE_USBTV_USB30DRD_LINK>;
clock-names = "ext_xtal", "aclk";
samsung,pmu-syscon = <&pmu_system_controller>;
is_not_vbus_pad;
status = "disabled";
#phy-cells = <1>;
#address-cells = <2>;
#size-cells = <1>;
ranges;
change_refclk = <1>;
usbphy-refclk {
reg = <0x0 0x10E50070 0x10>;
offset = <0xC>;
mask = <0x1000000>;
value = <0x1000000>;
};
};
iommu-domain_aud {
compatible = "samsung,exynos-iommu-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges;
domain-clients = <&abox>;
};
sysmmu_aud0: sysmmu@13E30000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x13E30000 0x3000>;
interrupts = <0 445 0>;
qos = <15>;
clock-names = "aclk";
clocks = <&clock GATE_SMMU_ABOX>;
port-name = "Abox";
sysmmu,no-suspend;
sysmmu,tlb_property =
<(SYSMMU_PUBLIC_NO_PREFETCH | SYSMMU_BL1) SYSMMU_NOID>;
#iommu-cells = <0>;
};
abox_gic: abox_gic@0x13EF0000 {
compatible = "samsung,abox_gic";
reg = <0x0 0x13EF1000 0x1000>, <0x0 0x13EF2000 0x1004>;
reg-names = "gicd", "gicc";
interrupts = <0 442 0>;
};
abox: abox@0x13E50000 {
compatible = "samsung,abox";
reg = <0x0 0x13E50000 0x10000>, <0x0 0x13E20000 0x10000>, <0x0 0x13F00000 0x31000>;
reg-names = "sfr", "sysreg", "sram";
#address-cells = <2>;
#size-cells = <1>;
ranges;
pinctrl-names = "default", "idle";
pinctrl-0 = <&aud_codec_mclk &aud_codec_bus &aud_spk_bus
&aud_fm_bus &aud_bt_bus &aud_cdma_bus>;
pinctrl-1 = <&aud_codec_mclk_idle &aud_codec_bus_idle &aud_spk_bus_idle
&aud_fm_bus_idle &aud_bt_bus_idle &aud_cdma_bus_idle>;
samsung,power-domain = <&pd_abox>;
ipc_tx_offset = <0x30000>;
ipc_rx_offset = <0x30300>;
ipc_tx_ack_offset = <0x302FC>;
ipc_rx_ack_offset = <0x305FC>;
mailbox_offset = <0x30600>;
abox_gic = <&abox_gic>;
vts = <&vts>;
clocks = <&clock PLL_OUT_AUD>, <&clock DFS_ABOX>, <&clock DOUT_CLK_ABOX_AUDIF>,
<&clock DOUT_CLK_ABOX_UAIF0>, <&clock DOUT_CLK_ABOX_UAIF1>,
<&clock DOUT_CLK_ABOX_UAIF2>, <&clock DOUT_CLK_ABOX_UAIF3>,
<&clock DOUT_CLK_ABOX_UAIF4>, <&clock DOUT_CLK_ABOX_DSIF>,
<&clock DOUT_CLK_ABOX_DMIC>, <&clock GATE_UAIF0>,
<&clock GATE_UAIF1>, <&clock GATE_UAIF2>,
<&clock GATE_UAIF3>, <&clock GATE_UAIF4>,
<&clock GATE_DSIF>;
clock-names = "pll", "ca7", "audif",
"bclk0", "bclk1",
"bclk2", "bclk3",
"bclk4", "bclk5",
"dmic", "bclk0_gate",
"bclk1_gate", "bclk2_gate",
"bclk3_gate", "bclk4_gate",
"bclk5_gate";
iommus = <&sysmmu_aud0>;
pm_qos_int = <533000 400000 0 0 0>;
abox_rdma_0: abox_rdma@0x13E51000 {
compatible = "samsung,abox-rdma";
reg = <0x0 0x13E51000 0x100>;
abox = <&abox>;
id = <0>;
type = "normal";
pm_qos_lit = <715000 715000 0>; /* SUHQA UHQA NORMAL */
pm_qos_big = <1170000 1170000 0>; /* SUHQA UHQA NORMAL */
pm_qos_hmp = <1 1 0>; /* SUHQA UHQA NORMAL */
};
abox_rdma_1: abox_rdma@0x13E51100 {
compatible = "samsung,abox-rdma";
reg = <0x0 0x13E51100 0x100>;
abox = <&abox>;
id = <1>;
type = "normal";
pm_qos_lit = <715000 715000 0>; /* SUHQA UHQA NORMAL */
pm_qos_big = <1170000 1170000 0>; /* SUHQA UHQA NORMAL */
pm_qos_hmp = <1 1 0>; /* SUHQA UHQA NORMAL */
};
abox_rdma_2: abox_rdma@0x13E51200 {
compatible = "samsung,abox-rdma";
reg = <0x0 0x13E51200 0x100>;
abox = <&abox>;
id = <2>;
type = "normal";
pm_qos_lit = <715000 715000 0>; /* SUHQA UHQA NORMAL */
pm_qos_big = <1170000 1170000 0>; /* SUHQA UHQA NORMAL */
pm_qos_hmp = <1 1 0>; /* SUHQA UHQA NORMAL */
};
abox_rdma_3: abox_rdma@0x13E51300 {
compatible = "samsung,abox-rdma";
reg = <0x0 0x13E51300 0x100>;
abox = <&abox>;
id = <3>;
type = "sync";
};
abox_rdma_4: abox_rdma@0x13E51400 {
compatible = "samsung,abox-rdma";
reg = <0x0 0x13E51400 0x100>;
abox = <&abox>;
id = <4>;
type = "call";
};
abox_rdma_5: abox_rdma@0x13E51500 {
compatible = "samsung,abox-rdma";
reg = <0x0 0x13E51500 0x100>;
abox = <&abox>;
id = <5>;
type = "compress";
};
abox_rdma_6: abox_rdma@0x13E51600 {
compatible = "samsung,abox-rdma";
reg = <0x0 0x13E51600 0x100>;
abox = <&abox>;
id = <6>;
type = "realtime";
};
abox_rdma_7: abox_rdma@0x13E51700 {
compatible = "samsung,abox-rdma";
reg = <0x0 0x13E51700 0x100>;
abox = <&abox>;
id = <7>;
type = "realtime";
};
abox_wdma_0: abox_wdma@0x13E52000 {
compatible = "samsung,abox-wdma";
reg = <0x0 0x13E52000 0x100>;
abox = <&abox>;
id = <0>;
type = "normal";
};
abox_wdma_1: abox_wdma@0x13E52100 {
compatible = "samsung,abox-wdma";
reg = <0x0 0x13E52100 0x100>;
abox = <&abox>;
id = <1>;
type = "normal";
};
abox_wdma_2: abox_wdma@0x13E52200 {
compatible = "samsung,abox-wdma";
reg = <0x0 0x13E52200 0x100>;
abox = <&abox>;
id = <2>;
type = "call";
};
abox_wdma_3: abox_wdma@0x13E52300 {
compatible = "samsung,abox-wdma";
reg = <0x0 0x13E52300 0x100>;
abox = <&abox>;
id = <3>;
type = "realtime";
};
abox_wdma_4: abox_wdma@0x13E52400 {
compatible = "samsung,abox-wdma";
reg = <0x0 0x13E52400 0x100>;
abox = <&abox>;
id = <4>;
type = "vi-sensing";
};
abox_effect: abox_effect@0x13F2E000 {
compatible = "samsung,abox-effect";
reg = <0x0 0x13F2E000 0x1000>;
reg-names = "reg";
abox = <&abox>;
};
abox_debug: abox_debug@0 {
compatible = "samsung,abox-debug";
memory-region = <&abox_rmem>;
};
abox_vss: abox_vss@0 {
compatible = "samsung,abox-vss";
};
ext_bin_0: ext_bin@0 {
status = "okay";
samsung,name = "dsm.bin";
samsung,area = <1>; /* 0:SRAM, 1:DRAM, 2:VSS */
samsung,offset = <0x502000>;
};
ext_bin_1: ext_bin@1 {
status = "okay";
samsung,name = "AP_AUDIO_SLSI.bin";
samsung,area = <1>;
samsung,offset = <0x7F0000>;
};
ext_bin_2: ext_bin@2 {
status = "okay";
samsung,name = "APBargeIn_AUDIO_SLSI.bin";
samsung,area = <1>;
samsung,offset = <0x7EC000>;
};
ext_bin_3: ext_bin@3 {
status = "okay";
samsung,name = "SoundBoosterParam.bin";
samsung,area = <1>;
samsung,offset = <0x4FC000>;
};
ext_bin_4: ext_bin@4 {
status = "okay";
samsung,name = "APBiBF_AUDIO_SLSI.bin";
samsung,area = <1>;
samsung,offset = <0x7EF000>;
};
ext_bin_5: ext_bin@5 {
status = "okay";
samsung,name = "dsm_tune.bin";
samsung,area = <1>;
samsung,offset = <0x601000>;
};
ext_bin_6: ext_bin@6 {
status = "disabled";
samsung,name = "dummy.bin";
samsung,area = <1>;
samsung,offset = <0x800000>;
};
ext_bin_7: ext_bin@7 {
status = "disabled";
samsung,name = "dummy.bin";
samsung,area = <1>;
samsung,offset = <0x800000>;
};
};
mailbox_vts: mailbox@0x14040000 {
compatible = "samsung,mailbox-asoc";
reg = <0x0 0x14040000 0x10000>;
reg-names = "sfr";
interrupts = <0 23 0>;
interrupt-controller;
#interrupt-cells = <1>;
};
vts: vts@0x14020000 {
compatible = "samsung,vts";
reg = <0x0 0x14020000 0x10000>, <0x0 0x14100000 0x59800>,
<0x0 0x14070000 0x8>, <0x0 0x141F0000 0x50>;
reg-names = "sfr", "sram", "dmic", "gpr";
#address-cells = <2>;
#size-cells = <1>;
ranges;
pinctrl-names = "dmic_default", "amic_default", "idle";
pinctrl-0 = <&dmic_bus_clk &dmic_pdm>;
pinctrl-1 = <&amic_bus_clk &amic_pdm>;
pinctrl-2 = <&mic_bus_clk_idle &dmic_pdm_idle &amic_pdm_idle>;
samsung,power-domain = <&pd_vts>;
clocks = <&clock GATE_OSC_VTS>, <&clock DOUT_CLK_VTS_DMIC>,
<&clock DOUT_CLK_VTS_DMICIF>, <&clock DOUT_CLK_VTS_DMIC_DIV2>;
clock-names = "rco", "dmic", "dmic_if", "dmic_sync";
mailbox = <&mailbox_vts>;
interrupt-parent = <&mailbox_vts>;
interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
interrupt-names = "error", "boot_completed", "ipc_received", "voice_triggered", "trigger_period_elapsed", "record_period_elapsed";
vts_dma0: vts_dma@0x0 {
compatible = "samsung,vts-dma";
reg = <0x0 0x0 0x0>;
vts = <&vts>;
id = <0>;
type = "vts-trigger";
};
vts_dma1: vts_dma@0x1 {
compatible = "samsung,vts-dma";
reg = <0x0 0x1 0x0>;
vts = <&vts>;
id = <1>;
type = "vts-record";
};
};
pcie0@116A0000 {
compatible = "samsung,exynos-pcie";
gpios = <&gpj1 2 0x1 /* PERST */>;
reg = <0x0 0x116A0000 0x1000 /* elbi base */
0x0 0x116D0000 0x1000 /* phy base */
0x0 0x11421044 0x30 /* sysreg base */
0x0 0x11700000 0x1000 /* DBI base */
0x0 0x116C0000 0x1FC /* phy pcs base */
0x0 0x11BFF000 0x1000>; /* configuration space */
reg-names = "elbi", "phy", "sysreg", "dbi", "pcs", "config";
interrupts = <0 345 0>; /* IRQ_PULSE */
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,sysreg-phandle = <&sysreg_fsys1_controller>;
pinctrl-names = "default", "clkreq_output";
pinctrl-0 = <&pcie0_clkreq &pcie0_perst &pcie_wake &cfg_wlanen &wlan_host_wake>;
pinctrl-1 = <&pcie0_perst &pcie_wake &cfg_wlanen &wlan_host_wake>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x82000000 0 0x11800000 0 0x11800000 0 0x400000>; /* non-prefetchable memory */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 345 0x4>;
ip-ver = <0x889500>;
num-lanes = <1>;
msi-base = <200>;
ch-num = <0>;
pcie-clk-num = <0>;
phy-clk-num = <0>;
pcie-irq-toe-enable = <0>;
pcie-irq-toe-num = <10>;
pcie-irq-msi-cp-enable = <0>;
pcie-irq-msi-cp-base-bit = <16>;
pcie-irq-msi-cp-num = <4>;
pcie-pm-qos-int = <0>;
use-cache-coherency = "true";
use-msi = "false";
use-sicd = "true";
status = "disabled";
};
pcie1@116B0000 {
compatible = "samsung,exynos8895-pcie";
gpios = <&gpj1 6 0x1 /* PERST */>;
reg = <0x0 0x116B0000 0x1000 /* elbi base */
0x0 0x116D0000 0x1000 /* phy base */
0x0 0x15601044 0x30 /* sysreg base */
0x0 0x11710000 0x1000 /* DBI base */
0x0 0x116C0000 0x1FC /* phy pcs base */
0x0 0x11C00000 0x1000>; /* configuration space */
reg-names = "elbi", "phy", "sysreg", "dbi", "pcs", "config";
interrupts = <0 346 0>; /* IRQ_PULSE */
clocks = <&clock 770>;
clock-names = "gate_pciewifi1";
samsung,syscon-phandle = <&pmu_system_controller>;
pinctrl-names = "default", "clkreq_output";
pinctrl-0 = <&pcie1_clkreq &pcie1_perst>;
pinctrl-1 = <&pcie1_clkreq_output &pcie1_perst>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0 0x11C01000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x11C11000 0 0x11C11000 0 0x3EEFFF>; /* non-prefetchable memory */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 346 0x4>;
ip-ver = <0x889500>;
num-lanes = <1>;
msi-base = <200>;
ch-num = <1>;
pcie-clk-num = <1>;
phy-clk-num = <0>;
pcie-pm-qos-int = <0>;
use-cache-coherency = "true";
use-msi = "false";
use-sicd = "true";
status = "disabled";
};
/* Secure log */
seclog {
compatible = "samsung,exynos-seclog";
interrupts = <0 68 0>;
};
/* Secure RPMB */
ufs-srpmb {
compatible = "samsung,ufs-srpmb";
interrupts = <0 69 0>;
};
/* tbase */
tee {
compatible = "samsung,exynos-tee";
interrupts = <0 233 0>;
};
fips-fmp {
compatible = "samsung,exynos-fips-fmp";
};
mfc_0: mfc0@13CE0000 {
compatible = "samsung,mfc-v6";
reg = <0x0 0x13CE0000 0x10000>;
interrupts = <0 208 0>;
clock-names = "aclk_mfc";
clocks = <&clock GATE_MFC>;
iommus = <&sysmmu_mfc0_0>, <&sysmmu_mfc0_1>;
samsung,power-domain = <&pd_mfc>;
status = "ok";
ip_ver = <15>;
clock_rate = <400000000>;
min_rate = <100000>;
num_qos_steps = <8>;
max_mb = <4757298>;
mfc_qos_table {
mfc_qos_variant_0 {
thrd_mb = <0>;
freq_mfc = <89000>;
freq_int = <107000>;
freq_mif = <286000>;
freq_cpu = <0>;
freq_kfc = <0>;
mo_value = <0>;
mo_10bit_value = <0>;
time_fw = <923>;
};
mfc_qos_variant_1 {
thrd_mb = <259787>;
freq_mfc = <267000>;
freq_int = <267000>;
freq_mif = <421000>;
freq_cpu = <0>;
freq_kfc = <0>;
mo_value = <0>;
mo_10bit_value = <0>;
time_fw = <431>;
};
mfc_qos_variant_2 {
thrd_mb = <535550>;
freq_mfc = <400000>;
freq_int = <400000>;
freq_mif = <845000>;
freq_cpu = <0>;
freq_kfc = <0>;
mo_value = <0>;
mo_10bit_value = <0>;
time_fw = <261>;
};
mfc_qos_variant_3 {
thrd_mb = <1153791>;
freq_mfc = <400000>;
freq_int = <400000>;
freq_mif = <1352000>;
freq_cpu = <0>;
freq_kfc = <0>;
mo_value = <0>;
mo_10bit_value = <0>;
time_fw = <226>;
};
mfc_qos_variant_4 {
thrd_mb = <1884284>;
freq_mfc = <667000>;
freq_int = <533000>;
freq_mif = <1794000>;
freq_cpu = <0>;
freq_kfc = <0>;
mo_value = <0>;
mo_10bit_value = <0>;
time_fw = <161>;
};
mfc_qos_variant_5 {
thrd_mb = <2713968>;
freq_mfc = <667000>;
freq_int = <533000>;
freq_mif = <1014000>;
freq_cpu = <0>;
freq_kfc = <0>;
mo_value = <1>;
mo_10bit_value = <0>;
time_fw = <196>;
};
mfc_qos_variant_6 {
thrd_mb = <3267739>;
freq_mfc = <667000>;
freq_int = <533000>;
freq_mif = <1794000>;
freq_cpu = <0>;
freq_kfc = <0>;
mo_value = <1>;
mo_10bit_value = <0>;
time_fw = <161>;
};
mfc_qos_variant_7 {
thrd_mb = <4517358>;
freq_mfc = <667000>;
freq_int = <533000>;
freq_mif = <1794000>;
freq_cpu = <0>;
freq_kfc = <0>;
mo_value = <0>;
mo_10bit_value = <1>;
time_fw = <161>;
};
};
};
iommu-domain_mfc {
compatible = "samsung,exynos-iommu-bus";
#address-cells = <2>;
#size-cells = <1>;
domain-clients = <&mfc_0>;
};
sysmmu_mfc0_0: sysmmu@0x13c80000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x13c80000 0x3000>;
interrupts = <0 198 0>, <0 199 0>;
clock-names = "aclk";
clocks = <&clock GATE_SMMU_MFCD0>;
port-name = "MFC0";
sysmmu,secure-irq;
sysmmu,secure_base = <0x13C90000>;
sysmmu,tlb_property =
<(SYSMMU_PUBLIC_NO_PREFETCH | SYSMMU_BL4) SYSMMU_NOID>;
#iommu-cells = <0>;
};
sysmmu_mfc0_1: sysmmu@0x13ca0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x13ca0000 0x3000>;
interrupts = <0 201 0>, <0 202 0>;
clock-names = "aclk";
clocks = <&clock GATE_SMMU_MFCD1>;
port-name = "MFC1";
sysmmu,secure-irq;
sysmmu,secure_base = <0x13CB0000>;
sysmmu,tlb_property =
<(SYSMMU_PUBLIC_NO_PREFETCH | SYSMMU_BL4) SYSMMU_NOID>;
#iommu-cells = <0>;
};
iva: iva@0x13600000 {
compatible = "samsung,iva";
reg = <0x0 0x13600000 0x200000>;
iommus = <&sysmmu_iva>;
interrupt-names = "iva_mbox_irq";
interrupts = <0 236 0>;
clocks = <&clock GATE_IVA>;
clock-names = "clk_iva";
samsung,power-domain = <&pd_iva>;
mcu-info {
mem_size = <0x20000>;
shmem_size = <0x1000>;
print_delay = <0>; /* us */
};
};
sysmmu_iva: sysmmu@13530000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x13530000 0x3000>;
interrupts = <0 240 0>;
clock-names = "aclk";
clocks = <&clock GATE_SMMU_IVA>;
#iommu-cells = <0>;
};
score: score@134C0000 {
compatible = "samsung,score";
dma-coherent;
reg = <0x0 0x134C0000 0x20000>;
interrupts = <0 227 0>;
clocks = <&clock GATE_SCORE>;
clock-names = "dsp";
samsung,power-domain = <&pd_dsp>;
iommus = <&sysmmu_score0>;
};
#if 0
iommu-domain_score {
compatible = "samsung,exynos-iommu-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges;
domain-clients = <&score>;
};
#endif
iommu-domain_iva_score {
compatible = "samsung,exynos-iommu-bus";
#dma-address-cells = <1>;
#dma-size-cells = <1>;
/* start address, size : 0x80000000 - bug*/
dma-window = <0x80000000 0x70000000>;
domain-clients = <&iva>, <&score>;
};
sysmmu_score0: sysmmu@13430000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x13430000 0x3000>;
interrupts = <0 230 0>, <0 231 0>;
qos = <15>;
clock-names = "aclk";
clocks = <&clock GATE_SMMU_SCORE>;
port-name = "Score";
sysmmu,secure-irq;
sysmmu,secure_base = <0x13450000>;
sysmmu,tlb_property =
<(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x1)>,
<(SYSMMU_PUBLIC_NO_PREFETCH | SYSMMU_BL8) SYSMMU_NOID>;
#iommu-cells = <0>;
};
fimc_is: fimc_is@13140000 {
compatible = "samsung,exynos5-fimc-is";
#pb-id-cells = <6>;
reg = <0x0 0x12CE0000 0x10000>, /* CSIS-DMA */
<0x0 0x13030000 0x10000>, /* FIMC-3AAW */
<0x0 0x13130000 0x10000>, /* FIMC-3AA */
<0x0 0x13040000 0x10000>, /* FIMC_ISPLP */
<0x0 0x13140000 0x10000>, /* FIMC_ISPHQ */
<0x0 0x12C40000 0x10000>, /* FIMC_TPU0 */
<0x0 0x12C90000 0x10000>, /* FIMC_TPU1 */
<0x0 0x12C50000 0x10000>, /* MC_SCALER */
<0x0 0x12C60000 0x10000>, /* FIMC-VRA (Set A) */
<0x0 0x12C70000 0x10000>, /* FIMC-VRA (Set B) */
<0x0 0x12F00000 0x10000>, /* DCP */
<0x0 0x14300000 0x10000>; /* SRDZ */
interrupts = <0 294 0>, /* 3AAW_0 */
<0 295 0>, /* 3AAW_1 */
<0 301 0>, /* 3AA_0 */
<0 302 0>, /* 3AA_1 */
<0 296 0>, /* ISPLP_0 */
<0 297 0>, /* ISPLP_1 */
<0 303 0>, /* ISPHQ_0 */
<0 304 0>, /* ISPHQ_1 */
<0 272 0>, /* TPU0_0 */
<0 273 0>, /* TPU0_1 */
<0 284 0>, /* TPU1_0 */
<0 285 0>, /* TPU1_1 */
<0 274 0>, /* MC_SC_0 */
<0 275 0>, /* MC_SC_1 */
<0 276 0>, /* VRA_0 */
<0 277 0>, /* VRA_1 */
<0 242 0>, /* DCP_0 */
<0 243 0>, /* DCP_1 */
<0 85 0>; /* SRDZ */
samsung,power-domain = <&pd_dcam>;
clocks = <&clock GATE_ISP_EWGEN_ISPHQ>,
<&clock GATE_IS_ISPHQ_3AA>,
<&clock GATE_IS_ISPHQ_ISPHQ>,
<&clock GATE_IS_ISPHQ_QE_3AA>,
<&clock GATE_IS_ISPHQ_QE_ISPHQ>,
<&clock GATE_ISPHQ_CMU_ISPHQ>,
<&clock GATE_PMU_ISPHQ>,
<&clock GATE_SYSREG_ISPHQ>,
<&clock UMUX_CLKCMU_ISPHQ_BUS>,
<&clock GATE_ISP_EWGEN_ISPLP>,
<&clock GATE_IS_ISPLP_3AAW>,
<&clock GATE_IS_ISPLP_ISPLP>,
<&clock GATE_IS_ISPLP_QE_3AAW>,
<&clock GATE_IS_ISPLP_QE_ISPLP>,
<&clock GATE_IS_ISPLP_SMMU_ISPLP>,
<&clock GATE_IS_ISPLP_BCM_ISPLP>,
<&clock GATE_BTM_ISPLP>,
<&clock GATE_ISPLP_CMU_ISPLP>,
<&clock GATE_PMU_ISPLP>,
<&clock GATE_SYSREG_ISPLP>,
<&clock UMUX_CLKCMU_ISPLP_BUS>,
<&clock GATE_ISP_EWGEN_CAM>,
<&clock GATE_IS_CAM_CSIS0>,
<&clock GATE_IS_CAM_CSIS1>,
<&clock GATE_IS_CAM_CSIS2>,
<&clock GATE_IS_CAM_CSIS3>,
<&clock GATE_IS_CAM_MC_SCALER>,
<&clock GATE_IS_CAM_CSISX4_DMA>,
<&clock GATE_IS_CAM_SYSMMU_CAM0>,
<&clock GATE_IS_CAM_SYSMMU_CAM1>,
<&clock GATE_IS_CAM_BCM_CAM0>,
<&clock GATE_IS_CAM_BCM_CAM1>,
<&clock GATE_IS_CAM_TPU0>,
<&clock GATE_IS_CAM_VRA>,
<&clock GATE_IS_CAM_QE_TPU0>,
<&clock GATE_IS_CAM_QE_VRA>,
<&clock GATE_IS_CAM_BNS>,
<&clock GATE_IS_CAM_QE_CSISX4>,
<&clock GATE_IS_CAM_QE_TPU1>,
<&clock GATE_IS_CAM_TPU1>,
<&clock GATE_BTM_CAMD0>,
<&clock GATE_BTM_CAMD1>,
<&clock GATE_CAM_CMU_CAM>,
<&clock GATE_PMU_CAM>,
<&clock GATE_SYSREG_CAM>,
<&clock UMUX_CLKCMU_CAM_BUS>,
<&clock UMUX_CLKCMU_CAM_TPU0>,
<&clock UMUX_CLKCMU_CAM_VRA>,
<&clock UMUX_CLKCMU_CAM_TPU1>,
<&clock GATE_DCP>,
<&clock GATE_BTM_DCAM>,
<&clock GATE_DCAM_CMU_DCAM>,
<&clock GATE_PMU_DCAM>,
<&clock GATE_BCM_DCAM>,
<&clock GATE_SYSREG_DCAM>,
<&clock UMUX_CLKCMU_DCAM_BUS>,
<&clock UMUX_CLKCMU_DCAM_IMGD>,
<&clock GATE_SRDZ>,
<&clock GATE_BTM_SRDZ>,
<&clock GATE_PMU_SRDZ>,
<&clock GATE_BCM_SRDZ>,
<&clock GATE_SMMU_SRDZ>,
<&clock GATE_SRDZ_CMU_SRDZ>,
<&clock GATE_SYSREG_SRDZ>,
<&clock UMUX_CLKCMU_SRDZ_BUS>,
<&clock UMUX_CLKCMU_SRDZ_IMGD>,
<&clock CIS_CLK0>,
<&clock CIS_CLK1>,
<&clock CIS_CLK2>,
<&clock CIS_CLK3>,
<&clock GATE_DFTMUX_TOP_CIS_CLK0>,
<&clock GATE_DFTMUX_TOP_CIS_CLK1>,
<&clock GATE_DFTMUX_TOP_CIS_CLK2>,
<&clock GATE_DFTMUX_TOP_CIS_CLK3>;
clock-names = "GATE_ISP_EWGEN_ISPHQ",
"GATE_IS_ISPHQ_3AA",
"GATE_IS_ISPHQ_ISPHQ",
"GATE_IS_ISPHQ_QE_3AA",
"GATE_IS_ISPHQ_QE_ISPHQ",
"GATE_ISPHQ_CMU_ISPHQ",
"GATE_PMU_ISPHQ",
"GATE_SYSREG_ISPHQ",
"UMUX_CLKCMU_ISPHQ_BUS",
"GATE_ISP_EWGEN_ISPLP",
"GATE_IS_ISPLP_3AAW",
"GATE_IS_ISPLP_ISPLP",
"GATE_IS_ISPLP_QE_3AAW",
"GATE_IS_ISPLP_QE_ISPLP",
"GATE_IS_ISPLP_SMMU_ISPLP",
"GATE_IS_ISPLP_BCM_ISPLP",
"GATE_BTM_ISPLP",
"GATE_ISPLP_CMU_ISPLP",
"GATE_PMU_ISPLP",
"GATE_SYSREG_ISPLP",
"UMUX_CLKCMU_ISPLP_BUS",
"GATE_ISP_EWGEN_CAM",
"GATE_IS_CAM_CSIS0",
"GATE_IS_CAM_CSIS1",
"GATE_IS_CAM_CSIS2",
"GATE_IS_CAM_CSIS3",
"GATE_IS_CAM_MC_SCALER",
"GATE_IS_CAM_CSISX4_DMA",
"GATE_IS_CAM_SYSMMU_CAM0",
"GATE_IS_CAM_SYSMMU_CAM1",
"GATE_IS_CAM_BCM_CAM0",
"GATE_IS_CAM_BCM_CAM1",
"GATE_IS_CAM_TPU0",
"GATE_IS_CAM_VRA",
"GATE_IS_CAM_QE_TPU0",
"GATE_IS_CAM_QE_VRA",
"GATE_IS_CAM_BNS",
"GATE_IS_CAM_QE_CSISX4",
"GATE_IS_CAM_QE_TPU1",
"GATE_IS_CAM_TPU1",
"GATE_BTM_CAMD0",
"GATE_BTM_CAMD1",
"GATE_CAM_CMU_CAM",
"GATE_PMU_CAM",
"GATE_SYSREG_CAM",
"UMUX_CLKCMU_CAM_BUS",
"UMUX_CLKCMU_CAM_TPU0",
"UMUX_CLKCMU_CAM_VRA",
"UMUX_CLKCMU_CAM_TPU1",
"GATE_DCP",
"GATE_BTM_DCAM",
"GATE_DCAM_CMU_DCAM",
"GATE_PMU_DCAM",
"GATE_BCM_DCAM",
"GATE_SYSREG_DCAM",
"UMUX_CLKCMU_DCAM_BUS",
"UMUX_CLKCMU_DCAM_IMGD",
"GATE_SRDZ",
"GATE_BTM_SRDZ",
"GATE_PMU_SRDZ",
"GATE_BCM_SRDZ",
"GATE_SMMU_SRDZ",
"GATE_SRDZ_CMU_SRDZ",
"GATE_SYSREG_SRDZ",
"UMUX_CLKCMU_SRDZ_BUS",
"UMUX_CLKCMU_SRDZ_IMGD",
"CIS_CLK0",
"CIS_CLK1",
"CIS_CLK2",
"CIS_CLK3",
"MUX_CIS_CLK0",
"MUX_CIS_CLK1",
"MUX_CIS_CLK2",
"MUX_CIS_CLK3";
status = "ok";
iommus = <&sysmmu_cam0>, <&sysmmu_cam1>, <&sysmmu_isp>, <&sysmmu_dcam>;
#cooling-cells = <2>; /* min followed by max */
};
mipi_phy_csis0_m4s4_top: dphy_m4s4_csis0@0x12C21050 {
compatible = "samsung,mipi-phy-m4s4-top";
samsung,pmu-syscon = <&pmu_system_controller>;
isolation = <0x70C>; /* PMU address offset */
reg = <0x0 0x12C21050 0x4>; /* SYSREG address for reset */
reset = <0>; /* reset bit */
owner = <1>; /* 0: DSI, 1: CSI */
#phy-cells = <1>;
};
mipi_phy_csis2_m4s4_mod: dphy_m4s4_csis2@0x12C21050 {
compatible = "samsung,mipi-phy-m4s4-mod";
samsung,pmu-syscon = <&pmu_system_controller>;
isolation = <0x710>; /* PMU address offset */
reset = <1>; /* reset bit */
owner = <1>; /* 0: DSI, 1: CSI */
#phy-cells = <1>;
};
mipi_phy_csis1_m1s2s2: dphy_m1s2s2_csis1@0x12C21050 {
compatible = "samsung,mipi-phy-m1s2s2";
samsung,pmu-syscon = <&pmu_system_controller>;
isolation = <0x730>; /* PMU address offset */
reset = <2>; /* reset bit */
owner = <1>; /* 0: DSI, 1: CSI */
#phy-cells = <1>;
};
mipi_phy_csis3_m1s2s2: dphy_m1s2s2_csis3@0x12C21050 {
compatible = "samsung,mipi-phy-m1s2s2";
samsung,pmu-syscon = <&pmu_system_controller>;
isolation = <0x730>; /* PMU address offset */
reset = <3>; /* reset bit */
owner = <1>; /* 0: DSI, 1: CSI */
#phy-cells = <1>;
};
fimc_is_sensor0: fimc_is_sensor@12CA0000 {
/* BACK/CSIS0 */
compatible = "samsung,exynos5-fimc-is-sensor";
#pb-id-cells = <4>;
reg = <0x0 0x12CA0000 0x10000>, /* MIPI-CSI0 */
<0x0 0x12C80000 0x10000>; /* FIMC-BNS */
interrupts = <0 264 0>, /* MIPI-CSI0 */
<0 291 0>; /* FIMC-BNS */
samsung,power-domain = <&pd_cam>;
phys = <&mipi_phy_csis0_m4s4_top 0>;
phy-names = "csis_dphy";
clocks = <&clock CIS_CLK0>,
<&clock CIS_CLK1>,
<&clock CIS_CLK2>,
<&clock CIS_CLK3>,
<&clock GATE_DFTMUX_TOP_CIS_CLK0>,
<&clock GATE_DFTMUX_TOP_CIS_CLK1>,
<&clock GATE_DFTMUX_TOP_CIS_CLK2>,
<&clock GATE_DFTMUX_TOP_CIS_CLK3>,
<&clock GATE_IS_CAM_CSIS0>,
<&clock GATE_IS_CAM_CSIS1>,
<&clock GATE_IS_CAM_CSIS2>,
<&clock GATE_IS_CAM_CSIS3>;
clock-names = "CIS_CLK0",
"CIS_CLK1",
"CIS_CLK2",
"CIS_CLK3",
"MUX_CIS_CLK0",
"MUX_CIS_CLK1",
"MUX_CIS_CLK2",
"MUX_CIS_CLK3",
"GATE_IS_CAM_CSIS0",
"GATE_IS_CAM_CSIS1",
"GATE_IS_CAM_CSIS2",
"GATE_IS_CAM_CSIS3";
iommus = <&sysmmu_cam0>;
};
fimc_is_sensor1: fimc_is_sensor@12CB0000 {
compatible = "samsung,exynos5-fimc-is-sensor";
#pb-id-cells = <4>;
reg = <0x0 0x12CB0000 0x10000>, /* MIPI-CSI1 */
<0x0 0x12C80000 0x10000>; /* FIMC-BNS */
interrupts = <0 266 0>, /* MIPI-CSI1 */
<0 291 0>; /* FIMC-BNS */
samsung,power-domain = <&pd_cam>;
phys = <&mipi_phy_csis1_m1s2s2 0>;
phy-names = "csis_dphy";
clocks = <&clock CIS_CLK0>,
<&clock CIS_CLK1>,
<&clock CIS_CLK2>,
<&clock CIS_CLK3>,
<&clock GATE_DFTMUX_TOP_CIS_CLK0>,
<&clock GATE_DFTMUX_TOP_CIS_CLK1>,
<&clock GATE_DFTMUX_TOP_CIS_CLK2>,
<&clock GATE_DFTMUX_TOP_CIS_CLK3>,
<&clock GATE_IS_CAM_CSIS0>,
<&clock GATE_IS_CAM_CSIS1>,
<&clock GATE_IS_CAM_CSIS2>,
<&clock GATE_IS_CAM_CSIS3>;
clock-names = "CIS_CLK0",
"CIS_CLK1",
"CIS_CLK2",
"CIS_CLK3",
"MUX_CIS_CLK0",
"MUX_CIS_CLK1",
"MUX_CIS_CLK2",
"MUX_CIS_CLK3",
"GATE_IS_CAM_CSIS0",
"GATE_IS_CAM_CSIS1",
"GATE_IS_CAM_CSIS2",
"GATE_IS_CAM_CSIS3";
iommus = <&sysmmu_cam0>;
};
fimc_is_sensor2: fimc_is_sensor@12CC0000 {
/* DEPTH/CSIS2 */
compatible = "samsung,exynos5-fimc-is-sensor";
#pb-id-cells = <4>;
reg = <0x0 0x12CC0000 0x10000>, /* MIPI-CSI2 */
<0x0 0x12C80000 0x10000>; /* FIMC-BNS */
interrupts = <0 268 0>, /* MIPI-CSI2 */
<0 291 0>; /* FIMC-BNS */
samsung,power-domain = <&pd_cam>;
phys = <&mipi_phy_csis2_m4s4_mod 0>;
phy-names = "csis_dphy";
clocks = <&clock CIS_CLK0>,
<&clock CIS_CLK1>,
<&clock CIS_CLK2>,
<&clock CIS_CLK3>,
<&clock GATE_DFTMUX_TOP_CIS_CLK0>,
<&clock GATE_DFTMUX_TOP_CIS_CLK1>,
<&clock GATE_DFTMUX_TOP_CIS_CLK2>,
<&clock GATE_DFTMUX_TOP_CIS_CLK3>,
<&clock GATE_IS_CAM_CSIS0>,
<&clock GATE_IS_CAM_CSIS1>,
<&clock GATE_IS_CAM_CSIS2>,
<&clock GATE_IS_CAM_CSIS3>;
clock-names = "CIS_CLK0",
"CIS_CLK1",
"CIS_CLK2",
"CIS_CLK3",
"MUX_CIS_CLK0",
"MUX_CIS_CLK1",
"MUX_CIS_CLK2",
"MUX_CIS_CLK3",
"GATE_IS_CAM_CSIS0",
"GATE_IS_CAM_CSIS1",
"GATE_IS_CAM_CSIS2",
"GATE_IS_CAM_CSIS3";
iommus = <&sysmmu_cam0>;
};
fimc_is_sensor3: fimc_is_sensor@112CD000 {
/* IRIS/CSIS3 */
compatible = "samsung,exynos5-fimc-is-sensor";
#pb-id-cells = <4>;
reg = <0x0 0x12CD0000 0x10000>, /* MIPI-CSI3 */
<0x0 0x12C80000 0x10000>; /* FIMC-BNS */
interrupts = <0 270 0>, /* MIPI-CSI3 */
<0 291 0>; /* FIMC-BNS */
samsung,power-domain = <&pd_cam>;
phys = <&mipi_phy_csis3_m1s2s2 0>, <&mipi_phy_csis1_m1s2s2 0>;
phy-names = "csis_dphy", "extra_csis_dphy";
clocks = <&clock CIS_CLK0>,
<&clock CIS_CLK1>,
<&clock CIS_CLK2>,
<&clock CIS_CLK3>,
<&clock GATE_DFTMUX_TOP_CIS_CLK0>,
<&clock GATE_DFTMUX_TOP_CIS_CLK1>,
<&clock GATE_DFTMUX_TOP_CIS_CLK2>,
<&clock GATE_DFTMUX_TOP_CIS_CLK3>,
<&clock GATE_IS_CAM_CSIS0>,
<&clock GATE_IS_CAM_CSIS1>,
<&clock GATE_IS_CAM_CSIS2>,
<&clock GATE_IS_CAM_CSIS3>;
clock-names = "CIS_CLK0",
"CIS_CLK1",
"CIS_CLK2",
"CIS_CLK3",
"MUX_CIS_CLK0",
"MUX_CIS_CLK1",
"MUX_CIS_CLK2",
"MUX_CIS_CLK3",
"GATE_IS_CAM_CSIS0",
"GATE_IS_CAM_CSIS1",
"GATE_IS_CAM_CSIS2",
"GATE_IS_CAM_CSIS3";
iommus = <&sysmmu_cam0>;
};
iommu-domain_cam {
compatible = "samsung,exynos-iommu-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges;
domain-clients = <&fimc_is>, <&fimc_is_sensor0>, <&fimc_is_sensor1>,
<&fimc_is_sensor2>, <&fimc_is_sensor3>;
};
sysmmu_cam0: sysmmu@12D10000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x12D10000 0x3000>;
interrupts = <0 279 0>, <0 280 0>;
qos = <15>;
clock-names = "aclk";
clocks = <&clock GATE_IS_CAM_SYSMMU_CAM0>;
port-name = "CAM0";
sysmmu,secure-irq;
sysmmu,secure_base = <0x12D00000>;
/* Dual CAM scenario */
sysmmu,tlb_property =
/* 0~9 : CSIS0~3 */
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x0, 0x3F)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x4, 0x3F)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x8, 0x3F)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x10, 0x3F)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x14, 0x3F)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x18, 0x3F)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x20, 0x3F)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x24, 0x3F)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x28, 0x3F)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x30, 0x3F)>,
/* 10~13 : TPU1_ID */
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL4) SYSMMU_ID(0x7)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID(0x3)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID(0x7)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID(0xB)>,
/* 14~17 : TPU0_ID */
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL4) SYSMMU_ID(0x5)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID(0x1)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID(0x5)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID(0x9)>,
/* 18~19 : VRA Ch0 */
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL4) SYSMMU_ID(0x6)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID(0x6)>,
/* 20~21 : TPU1_ADDR */
<(SYSMMU_PRIV_ADDR_PREFETCH_ASCENDING_READ | SYSMMU_BL4) SYSMMU_NOID>,
<(SYSMMU_PRIV_ADDR_PREFETCH_ASCENDING_READ | SYSMMU_BL4) SYSMMU_NOID>,
/* 22~23 : TPU0_ADDR */
<(SYSMMU_PRIV_ADDR_PREFETCH_ASCENDING_READ | SYSMMU_BL4) SYSMMU_NOID>,
<(SYSMMU_PRIV_ADDR_PREFETCH_ASCENDING_READ | SYSMMU_BL4) SYSMMU_NOID>,
/* 24~27 : VRA Ch1 */
<(SYSMMU_PUBLIC_PREFETCH_ASCENDING | SYSMMU_BL1) SYSMMU_NOID>;
#iommu-cells = <0>;
};
sysmmu_cam1: sysmmu@12D20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x12D20000 0x3000>;
interrupts = <0 282 0>;
qos = <15>;
clock-names = "aclk";
clocks = <&clock GATE_IS_CAM_SYSMMU_CAM1>;
port-name = "CAM1";
sysmmu,tlb_property =
/* 0~17 : MCScaler */
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x0)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x1)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x2)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x0)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x1)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x2)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x3)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x4)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x5)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x6)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x7)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x8)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x9)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xA)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xB)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xC)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xD)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xE)>,
/* 18~19 : SBB */
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x3)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xF)>;
#iommu-cells = <0>;
};
sysmmu_isp: sysmmu@13050000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x13050000 0x3000>;
interrupts = <0 298 0>, <0 299 0>;
qos = <15>;
clock-names = "aclk";
clocks = <&clock GATE_IS_ISPLP_SMMU_ISPLP>;
port-name = "ISP";
sysmmu,secure-irq;
sysmmu,secure_base = <0x13060000>;
sysmmu,tlb_property =
/* 0~11 : 3AAW */
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x0)>,
<(SYSMMU_PRIV_ID_NO_PREFETCH_WRITE | SYSMMU_BL2) SYSMMU_ID(0x0)>,
<(SYSMMU_PRIV_ID_NO_PREFETCH_WRITE | SYSMMU_BL2) SYSMMU_ID(0x4)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x24)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xC)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x20)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x8)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x18)>,
<(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL2) SYSMMU_ID(0x4)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x14)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x1C)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x10)>,
/* 12~14 : ISPLP */
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x2)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x1)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x5)>,
/* 15~20 : 3AA */
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x2)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x2)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xA)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x22)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x12)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x1A)>,
/* 21~28 : ISPHQ */
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x6)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x1E)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x26)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x26)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x16)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x2E)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x6)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xE)>,
/* 29 : 3AAW/ISPLP/ISPHQ */
<(SYSMMU_PUBLIC_NO_PREFETCH | SYSMMU_BL2) SYSMMU_NOID>;
#iommu-cells = <0>;
};
sysmmu_dcam: sysmmu@14230000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x14230000 0x3000>;
interrupts = <0 248 0>, <0 249 0>;
qos = <15>;
clock-names = "aclk";
clocks = <&clock GATE_SMMU_SRDZ>;
port-name = "DCP, SRDZ";
sysmmu,secure-irq;
sysmmu,secure_base = <0x14250000>;
sysmmu,tlb_property =
/* 0~10 : DCP */
<(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL16) SYSMMU_ID(0x1)>,
<(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL16) SYSMMU_ID(0x3)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL8) SYSMMU_ID(0x5)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL8) SYSMMU_ID(0x7)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL8) SYSMMU_ID(0x9)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL8) SYSMMU_ID(0x1)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL8) SYSMMU_ID(0x3)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL8) SYSMMU_ID(0x5)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL8) SYSMMU_ID(0x7)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL8) SYSMMU_ID(0x9)>,
<(SYSMMU_PRIV_ID_NO_PREFETCH_WRITE | SYSMMU_BL16) SYSMMU_ID(0xB)>,
/* 11~15 : SRDZ */
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL8) SYSMMU_ID(0x0)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL16) SYSMMU_ID(0x2)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL16) SYSMMU_ID(0x6)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL16) SYSMMU_ID(0x0)>,
<(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL16) SYSMMU_ID(0x2)>;
#iommu-cells = <0>;
};
earlytmu: earlytmu@10080000 {
compatible = "samsung,exynos8895-earlytmu";
reg = <0x0 0x10080000 0x400>;
};
tmuctrl_0: MNGS@10080000 {
compatible = "samsung,exynos8895-tmu";
reg = <0x0 0x10080000 0x400>;
interrupts = <0 451 0>;
tmu_name = "MNGS";
id = <0>;
sensors = <61>;
sensing_mode = "balance";
hotplug_enable = <1>;
hotplug_in_threshold = <91>;
hotplug_out_threshold = <96>;
#include "exynos8895-tmu-sensor-conf.dtsi"
};
tmuctrl_1: APOLLO@10080000 {
compatible = "samsung,exynos8895-tmu";
reg = <0x0 0x10080000 0x400>;
interrupts = <0 451 0>;
tmu_name = "APOLLO";
id = <1>;
sensors = <2>;
sensing_mode = "max";
#include "exynos8895-tmu-sensor-conf.dtsi"
};
tmuctrl_2: GPU@10084000 {
compatible = "samsung,exynos8895-tmu";
reg = <0x0 0x10084000 0x400>;
interrupts = <0 452 0>;
tmu_name = "GPU";
id = <2>;
sensors = <1>;
sensing_mode = "max";
/* gpu cooling related table */
/* flags, driver_data(index), frequency */
gpu_idx_num = <6>;
gpu_cooling_table = < 0 0 546000
0 1 455000
0 2 385000
0 3 338000
0 4 260000
0 5 TABLE_END>;
#include "exynos8895-tmu-sensor-conf.dtsi"
};
tmuctrl_3: ISP@10084000 {
compatible = "samsung,exynos8895-tmu";
reg = <0x0 0x10084000 0x400>;
interrupts = <0 452 0>;
tmu_name = "ISP";
id = <3>;
sensors = <6>;
sensing_mode = "max";
#include "exynos8895-tmu-sensor-conf.dtsi"
};
thermal-zones {
mngs_thermal: mngs-thermal {
zone_name = "MNGS_THERMAL";
polling-delay-passive = <50>;
polling-delay = <1000>;
thermal-sensors = <&tmuctrl_0>;
governor = "power_allocator";
sustainable-power = <2000>;
k_po = <100>;
k_pu = <85>;
k_i = <100>;
i_max = <1500>;
integral_cutoff = <28>;
trips {
mngs_cold: mngs-cold {
temperature = <20000>;
hysteresis = <5000>; /* millicelsius */
type = "active";
};
mngs_alert0: mngs-alert0 {
temperature = <55000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "active";
};
mngs_alert1: mngs-alert1 {
temperature = <83000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "passive";
};
mngs_hot: mngs-hot {
temperature = <115000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "hot";
};
};
cooling-maps {
map0 {
trip = <&mngs_alert0>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&mngs_alert1>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
apo_thermal: APOLLO {
zone_name = "APO_THERMAL";
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tmuctrl_1>;
trips {
apo_alert0: apo-alert0 {
temperature = <20000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
apo_alert1: apo-alert1 {
temperature = <76000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
apo_alert2: apo-alert2 {
temperature = <81000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
apo_alert3: apo-alert3 {
temperature = <86000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
apo_alert4: apo-alert4 {
temperature = <91000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
apo_alert5: apo-alert5 {
temperature = <96000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
apo_alert6: apo-alert6 {
temperature = <101000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
apo_hot: apo-hot {
temperature = <115000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "hot";
};
};
cooling-maps {
map0 {
trip = <&apo_alert0>;
/* Corresponds to 1586MHz at freq_table */
cooling-device = <&cpu0 0 0>;
};
map1 {
trip = <&apo_alert1>;
/* Corresponds to 1482MHz at freq_table */
cooling-device = <&cpu0 0 0>;
};
map2 {
trip = <&apo_alert2>;
/* Corresponds to 1378MHz at freq_table */
cooling-device = <&cpu0 0 0>;
};
map3 {
trip = <&apo_alert3>;
/* Corresponds to 1170MHz at freq_table */
cooling-device = <&cpu0 0 0>;
};
map4 {
trip = <&apo_alert4>;
/* Corresponds to 1066MHz at freq_table */
cooling-device = <&cpu0 0 0>;
};
map5 {
trip = <&apo_alert5>;
/* Corresponds to 442MHz at freq_table */
cooling-device = <&cpu0 0 0>;
};
map6 {
trip = <&apo_alert6>;
/* Corresponds to 442MHz at freq_table */
cooling-device = <&cpu0 0 0>;
};
map7 {
trip = <&apo_hot>;
/* Corresponds to 442MHz at freq_table */
cooling-device = <&cpu0 0 0>;
};
};
};
gpu_thermal: GPU {
zone_name = "GPU_THERMAL";
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&tmuctrl_2>;
governor = "power_allocator";
sustainable-power = <2000>;
k_po = <60>;
k_pu = <100>;
k_i = <50>;
i_max = <500>;
integral_cutoff = <10>;
trips {
gpu_cold: gpu-cold {
temperature = <20000>;
hysteresis = <5000>; /* millicelsius */
type = "active";
};
gpu_alert0: gpu-alert0 {
temperature = <78000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "active";
};
gpu_alert1: gpu-alert1 {
temperature = <88000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "passive";
};
gpu_hot: gpu-hot {
temperature = <115000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "hot";
};
};
cooling-maps {
map0 {
trip = <&gpu_alert0>;
cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&gpu_alert1>;
cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
isp_thermal: ISP {
zone_name = "ISP_THERMAL";
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tmuctrl_3>;
trips {
isp_alert0: isp-alert0 {
temperature = <20000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
isp_alert1: isp-alert1 {
temperature = <91000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
isp_alert2: isp-alert2 {
temperature = <96000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
isp_alert3: isp-alert3 {
temperature = <101000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
isp_hot: isp-hot {
temperature = <115000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "hot";
};
};
cooling-maps {
map0 {
trip = <&isp_alert0>;
/* Corresponds to No limit */
cooling-device = <&fimc_is 0 0>;
};
map1 {
trip = <&isp_alert1>;
/* Corresponds to No limit */
cooling-device = <&fimc_is 0 0>;
};
map2 {
trip = <&isp_alert2>;
/* Corresponds to 15fps at freq_table */
cooling-device = <&fimc_is 0 0>;
};
map3 {
trip = <&isp_alert3>;
/* Corresponds to 5fps at freq_table */
cooling-device = <&fimc_is 0 0>;
};
map4 {
trip = <&isp_hot>;
/* Corresponds to HW trip */
cooling-device = <&fimc_is 0 0>;
};
};
};
};
input_booster {
status = "okay";
compatible = "input_booster";
#address-cells = <1>;
#size-cells = <0>;
booster_key@1 {
input_booster,label = "KEY";
input_booster,type = <0>; /* BOOSTER_DEVICE_KEY */
input_booster,levels = <1>;
/* Frequency table */
/* for level : 1_Head */
input_booster,cpu_freqs = <1066000>;
input_booster,hmp_boost = <1>;
input_booster,kfc_freqs = <0>;
input_booster,mif_freqs = <0>;
input_booster,int_freqs = <0>;
/* Time table */
input_booster,head_times = <500>;
input_booster,tail_times = <500>;
input_booster,phase_times = <0>;
};
booster_key@2 {
input_booster,label = "TOUCHKEY";
input_booster,type = <1>; /* BOOSTER_DEVICE_TOUCHKEY */
input_booster,levels = <1>;
/* Frequency table */
/* for level : 1_Head */
input_booster,cpu_freqs = <1066000>;
input_booster,hmp_boost = <1>;
input_booster,kfc_freqs = <0>;
input_booster,mif_freqs = <0>;
input_booster,int_freqs = <0>;
/* Time table */
input_booster,head_times = <0>;
input_booster,tail_times = <200>;
input_booster,phase_times = <0>;
};
booster_key@3 {
input_booster,label = "TOUCH";
input_booster,type = <2>; /* BOOSTER_DEVICE_TOUCH */
input_booster,levels = <1 2 3>;
/* Frequency table */
/* for level : 1_Head, 2_Head, 2_Tail */
input_booster,cpu_freqs = <1066000 1066000 858000>;
input_booster,hmp_boost = <1 1 1>;
input_booster,kfc_freqs = <832000 832000 832000>;
input_booster,mif_freqs = <0 0 0>;
input_booster,int_freqs = <0 0 0>;
/* Time table */
input_booster,head_times = <130 130 0>;
input_booster,tail_times = <0 0 500>;
input_booster,phase_times = <0 0 0>;
};
booster_key@4 { // Input Booster +
input_booster,label = "MULTITOUCH";
input_booster,type = <3>; /* BOOSTER_DEVICE_MULTITOUCH */
input_booster,levels = <1 2>;
/* Frequency table */
/* for level : 1_Head 2_Tail*/
input_booster,cpu_freqs = <1066000 858000>;
input_booster,hmp_boost = <1 1>;
input_booster,kfc_freqs = <832000 832000>;
input_booster,mif_freqs = <0 0>;
input_booster,int_freqs = <0 0>;
/* Time table */
input_booster,head_times = <1000 0>;
input_booster,tail_times = <0 500>;
input_booster,phase_times = <0 0>;
};
booster_key@5 {
input_booster,label = "KEYBOARD";
input_booster,type = <4>; /* BOOSTER_DEVICE_KEYBOARD */
input_booster,levels = <1 2>;
/* Frequency table */
/* for level : 1_Head 2_Tail*/
input_booster,cpu_freqs = <1066000 1066000>;
input_booster,hmp_boost = <1 1>;
input_booster,kfc_freqs = <832000 832000>;
input_booster,mif_freqs = <0 0>;
input_booster,int_freqs = <0 0>;
/* Time table */
input_booster,head_times = <130 130>;
input_booster,tail_times = <0 0>;
input_booster,phase_times = <0 0>;
};
booster_key@6 {
input_booster,label = "MOUSE";
input_booster,type = <5>; /* BOOSTER_DEVICE_MOUSE */
input_booster,levels = <1 2>;
/* Frequency table */
/* for level : 1_Head 2_Tail*/
input_booster,cpu_freqs = <1066000 858000>;
input_booster,hmp_boost = <1 1>;
input_booster,kfc_freqs = <832000 832000>;
input_booster,mif_freqs = <0 0>;
input_booster,int_freqs = <0 0>;
/* Time table */
input_booster,head_times = <130 0>;
input_booster,tail_times = <0 500>;
input_booster,phase_times = <0 0>;
};
booster_key@7 {
input_booster,label = "MOUSE WHEEL";
input_booster,type = <6>; /* BOOSTER_DEVICE_MOUSE */
input_booster,levels = <1 2>;
/* Frequency table */
/* for level : 1_Head 2_Tail*/
input_booster,cpu_freqs = <1066000 0>;
input_booster,hmp_boost = <1 0>;
input_booster,kfc_freqs = <832000 0>;
input_booster,mif_freqs = <0 0>;
input_booster,int_freqs = <0 0>;
/* Time table */
input_booster,head_times = <130 0>;
input_booster,tail_times = <0 0>;
input_booster,phase_times = <0 0>;
};
booster_key@8 {
input_booster,label = "PEN HOVER";
input_booster,type = <7>; /* BOOSTER_DEVICE_MOUSE */
input_booster,levels = <1 2>;
/* Frequency table */
/* for level : 1_Head 2_Tail*/
input_booster,cpu_freqs = <1066000 858000>;
input_booster,hmp_boost = <1 1>;
input_booster,kfc_freqs = <832000 832000>;
input_booster,mif_freqs = <0 0>;
input_booster,int_freqs = <0 0>;
/* Time table */
input_booster,head_times = <130 0>;
input_booster,tail_times = <0 500>;
input_booster,phase_times = <0 0>;
};
booster_key@9 {
input_booster,label = "PEN";
input_booster,type = <8>; /* BOOSTER_DEVICE_MOUSE */
input_booster,levels = <1 2>;
/* Frequency table */
/* for level : 1_Head 2_Tail*/
input_booster,cpu_freqs = <1469000 858000>;
input_booster,hmp_boost = <1 1>;
input_booster,kfc_freqs = <832000 832000>;
input_booster,bimc_freqs = <0 0>;
/* Time table */
input_booster,head_times = <200 0>;
input_booster,tail_times = <0 600>;
};
booster_key@10 {
input_booster,label = "KEY_TWO";
input_booster,type = <9>; /* BOOSTER_DEVICE_KEY */
input_booster,levels = <1>;
/* Frequency table */
/* for level : 1_Head */
input_booster,cpu_freqs = <1469000>;
input_booster,hmp_boost = <1>;
input_booster,kfc_freqs = <0>;
input_booster,mif_freqs = <0>;
input_booster,int_freqs = <0>;
/* Time table */
input_booster,head_times = <700>;
input_booster,tail_times = <700>;
input_booster,phase_times = <0>;
}; // Input Booster -
/* If you need to add new key type, add it this position */
};
rtc@16490000 {
compatible = "samsung,exynos8-rtc";
reg = <0x0 0x16490000 0x100>;
interrupts = <0 79 0>, <0 78 0>;
};
};
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