130 lines
3.7 KiB
Diff
130 lines
3.7 KiB
Diff
From 72112b91624dca6c636bd3a592471642d3988b27 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 20 Jul 2012 19:09:01 +0200
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Subject: [PATCH 111/123] MTD: MIPS: lantiq: Add NAND support on Lantiq FALCON
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SoC.
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The driver uses plat_nand. As the platform_device is loaded from DT, we need
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to lookup the node and attach our falocn specific "struct platform_nand_data"
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to it.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
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Cc: linux-mtd@lists.infradead.org
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---
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drivers/mtd/nand/Kconfig | 8 ++++
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drivers/mtd/nand/Makefile | 1 +
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drivers/mtd/nand/falcon_nand.c | 82 ++++++++++++++++++++++++++++++++++++++++
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3 files changed, 91 insertions(+)
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create mode 100644 drivers/mtd/nand/falcon_nand.c
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--- a/drivers/mtd/nand/Kconfig
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+++ b/drivers/mtd/nand/Kconfig
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@@ -572,4 +572,12 @@ config MTD_NAND_XWAY
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Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
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to the External Bus Unit (EBU).
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+config MTD_NAND_FALCON
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+ tristate "Support for NAND on Lantiq FALC-ON SoC"
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+ depends on LANTIQ && SOC_FALCON
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+ select MTD_NAND_PLATFORM
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+ help
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+ Enables support for NAND Flash chips on Lantiq FALC-ON SoCs. NAND is
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+ attached to the External Bus Unit (EBU).
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+
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endif # MTD_NAND
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--- a/drivers/mtd/nand/Makefile
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+++ b/drivers/mtd/nand/Makefile
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@@ -53,5 +53,6 @@ obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
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obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
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obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
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obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
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+obj-$(CONFIG_MTD_NAND_FALCON) += falcon_nand.o
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nand-objs := nand_base.o nand_bbt.o
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--- /dev/null
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+++ b/drivers/mtd/nand/falcon_nand.c
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@@ -0,0 +1,82 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
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+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/mtd/nand.h>
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+#include <linux/of_platform.h>
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+
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+#include <lantiq_soc.h>
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+
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+/* nand flash */
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+/* address lines used for NAND control signals */
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+#define NAND_ADDR_ALE 0x10000
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+#define NAND_ADDR_CLE 0x20000
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+/* Ready/Busy Status */
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+#define MODCON_STS 0x0002
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+/* Ready/Busy Status Edge */
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+#define MODCON_STSEDGE 0x0004
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+#define LTQ_EBU_MODCON 0x000C
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+
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+static const char *part_probes[] = { "cmdlinepart", "ofpart", NULL };
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+
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+static int falcon_nand_ready(struct mtd_info *mtd)
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+{
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+ u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON);
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+
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+ return (((modcon & (MODCON_STS | MODCON_STSEDGE)) ==
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+ (MODCON_STS | MODCON_STSEDGE)));
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+}
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+
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+static void falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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+{
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+ struct nand_chip *this = mtd->priv;
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+ unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
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+
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+ if (ctrl & NAND_CTRL_CHANGE) {
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+ nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE);
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+
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+ if (ctrl & NAND_CLE)
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+ nandaddr |= NAND_ADDR_CLE;
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+ if (ctrl & NAND_ALE)
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+ nandaddr |= NAND_ADDR_ALE;
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+
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+ this->IO_ADDR_W = (void __iomem *) nandaddr;
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+ }
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+
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+ if (cmd != NAND_CMD_NONE)
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+ writeb(cmd, this->IO_ADDR_W);
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+}
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+
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+static struct platform_nand_data falcon_nand_data = {
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+ .chip = {
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+ .nr_chips = 1,
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+ .chip_delay = 25,
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+ .part_probe_types = part_probes,
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+ },
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+ .ctrl = {
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+ .cmd_ctrl = falcon_hwcontrol,
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+ .dev_ready = falcon_nand_ready,
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+ }
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+};
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+
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+static int __init falcon_register_nand(void)
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+{
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+ struct device_node *node;
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+ struct platform_device *pdev;
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+
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+ node = of_find_compatible_node(NULL, NULL, "lantiq,nand-falcon");
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+ if (!node)
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+ return -1;
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+ pdev = of_find_device_by_node(node);
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+ if (pdev)
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+ pdev->dev.platform_data = &falcon_nand_data;
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+ of_node_put(node);
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+ return 0;
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+}
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+
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+arch_initcall(falcon_register_nand);
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