02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
106 lines
3.2 KiB
Diff
106 lines
3.2 KiB
Diff
From a8e8c90a3cc81c6a7a44ff7fb18ceb71978c9155 Mon Sep 17 00:00:00 2001
|
|
From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
|
|
Date: Thu, 13 Feb 2014 18:21:23 +0200
|
|
Subject: [PATCH 066/182] spi: qup: Add device tree bindings information
|
|
|
|
The Qualcomm Universal Peripheral (QUP) core is an
|
|
AHB slave that provides a common data path (an output
|
|
FIFO and an input FIFO) for serial peripheral interface
|
|
(SPI) mini-core.
|
|
|
|
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
|
|
Signed-off-by: Mark Brown <broonie@linaro.org>
|
|
---
|
|
.../devicetree/bindings/spi/qcom,spi-qup.txt | 85 ++++++++++++++++++++
|
|
1 file changed, 85 insertions(+)
|
|
create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
|
|
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
|
|
@@ -0,0 +1,85 @@
|
|
+Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
|
|
+
|
|
+The QUP core is an AHB slave that provides a common data path (an output FIFO
|
|
+and an input FIFO) for serial peripheral interface (SPI) mini-core.
|
|
+
|
|
+SPI in master mode supports up to 50MHz, up to four chip selects, programmable
|
|
+data path from 4 bits to 32 bits and numerous protocol variants.
|
|
+
|
|
+Required properties:
|
|
+- compatible: Should contain "qcom,spi-qup-v2.1.1" or "qcom,spi-qup-v2.2.1"
|
|
+- reg: Should contain base register location and length
|
|
+- interrupts: Interrupt number used by this controller
|
|
+
|
|
+- clocks: Should contain the core clock and the AHB clock.
|
|
+- clock-names: Should be "core" for the core clock and "iface" for the
|
|
+ AHB clock.
|
|
+
|
|
+- #address-cells: Number of cells required to define a chip select
|
|
+ address on the SPI bus. Should be set to 1.
|
|
+- #size-cells: Should be zero.
|
|
+
|
|
+Optional properties:
|
|
+- spi-max-frequency: Specifies maximum SPI clock frequency,
|
|
+ Units - Hz. Definition as per
|
|
+ Documentation/devicetree/bindings/spi/spi-bus.txt
|
|
+
|
|
+SPI slave nodes must be children of the SPI master node and can contain
|
|
+properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
|
|
+
|
|
+Example:
|
|
+
|
|
+ spi_8: spi@f9964000 { /* BLSP2 QUP2 */
|
|
+
|
|
+ compatible = "qcom,spi-qup-v2";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0xf9964000 0x1000>;
|
|
+ interrupts = <0 102 0>;
|
|
+ spi-max-frequency = <19200000>;
|
|
+
|
|
+ clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
|
|
+ clock-names = "core", "iface";
|
|
+
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi8_default>;
|
|
+
|
|
+ device@0 {
|
|
+ compatible = "arm,pl022-dummy";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ reg = <0>; /* Chip select 0 */
|
|
+ spi-max-frequency = <19200000>;
|
|
+ spi-cpol;
|
|
+ };
|
|
+
|
|
+ device@1 {
|
|
+ compatible = "arm,pl022-dummy";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ reg = <1>; /* Chip select 1 */
|
|
+ spi-max-frequency = <9600000>;
|
|
+ spi-cpha;
|
|
+ };
|
|
+
|
|
+ device@2 {
|
|
+ compatible = "arm,pl022-dummy";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ reg = <2>; /* Chip select 2 */
|
|
+ spi-max-frequency = <19200000>;
|
|
+ spi-cpol;
|
|
+ spi-cpha;
|
|
+ };
|
|
+
|
|
+ device@3 {
|
|
+ compatible = "arm,pl022-dummy";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ reg = <3>; /* Chip select 3 */
|
|
+ spi-max-frequency = <19200000>;
|
|
+ spi-cpol;
|
|
+ spi-cpha;
|
|
+ spi-cs-high;
|
|
+ };
|
|
+ };
|