f07e572f64
bcm2708: boot tested on RPi B+ v1.2 bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G bcm2710: boot tested on RPi 3B v1.2 bcm2711: boot tested on RPi 4B v1.1 4G Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
124 lines
4.2 KiB
Diff
124 lines
4.2 KiB
Diff
From a3fddd6eaaa8740aceeeefea6548d5313412a062 Mon Sep 17 00:00:00 2001
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From: Jacopo Mondi <jacopo+renesas@jmondi.org>
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Date: Tue, 16 Jun 2020 16:12:42 +0200
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Subject: [PATCH] media: i2c: adv748x: Adjust TXA data lanes number
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Upstream https://patchwork.linuxtv.org/patch/64673/
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When outputting SD-Core output through the TXA MIPI CSI-2 interface,
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the number of enabled data lanes should be reduced in order to guarantee
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that the two video formats produced by the SD-Core (480i and 576i)
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generate a MIPI CSI-2 link clock frequency compatible with the MIPI D-PHY
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specifications.
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Limit the number of enabled data lanes to 2, which is guaranteed to
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support 480i and 576i formats.
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Cache the number of enabled data lanes to be able to report it through
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the new get_mbus_config operation.
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Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
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Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
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Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
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---
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drivers/media/i2c/adv748x/adv748x-core.c | 31 ++++++++++++++++++------
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drivers/media/i2c/adv748x/adv748x.h | 1 +
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2 files changed, 25 insertions(+), 7 deletions(-)
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--- a/drivers/media/i2c/adv748x/adv748x-core.c
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+++ b/drivers/media/i2c/adv748x/adv748x-core.c
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@@ -241,10 +241,10 @@ static int adv748x_power_up_tx(struct ad
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int ret = 0;
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/* Enable n-lane MIPI */
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- adv748x_write_check(state, page, 0x00, 0x80 | tx->num_lanes, &ret);
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+ adv748x_write_check(state, page, 0x00, 0x80 | tx->active_lanes, &ret);
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/* Set Auto DPHY Timing */
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- adv748x_write_check(state, page, 0x00, 0xa0 | tx->num_lanes, &ret);
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+ adv748x_write_check(state, page, 0x00, 0xa0 | tx->active_lanes, &ret);
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/* ADI Required Write */
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if (tx->src == &state->hdmi.sd) {
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@@ -270,7 +270,7 @@ static int adv748x_power_up_tx(struct ad
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usleep_range(2000, 2500);
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/* Power-up CSI-TX */
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- adv748x_write_check(state, page, 0x00, 0x20 | tx->num_lanes, &ret);
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+ adv748x_write_check(state, page, 0x00, 0x20 | tx->active_lanes, &ret);
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usleep_range(1000, 1500);
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/* ADI Required Writes */
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@@ -292,7 +292,7 @@ static int adv748x_power_down_tx(struct
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adv748x_write_check(state, page, 0x1e, 0x00, &ret);
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/* Enable n-lane MIPI */
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- adv748x_write_check(state, page, 0x00, 0x80 | tx->num_lanes, &ret);
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+ adv748x_write_check(state, page, 0x00, 0x80 | tx->active_lanes, &ret);
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/* i2c_mipi_pll_en - 1'b1 */
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adv748x_write_check(state, page, 0xda, 0x01, &ret);
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@@ -357,14 +357,29 @@ static int adv748x_link_setup(struct med
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if (state->afe.tx) {
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/* AFE Requires TXA enabled, even when output to TXB */
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io10 |= ADV748X_IO_10_CSI4_EN;
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- if (is_txa(tx))
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+ if (is_txa(tx)) {
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+ /*
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+ * Output from the SD-core (480i and 576i) from the TXA
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+ * interface requires reducing the number of enabled
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+ * data lanes in order to guarantee a valid link
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+ * frequency.
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+ */
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+ tx->active_lanes = min(tx->num_lanes, 2U);
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io10 |= ADV748X_IO_10_CSI4_IN_SEL_AFE;
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- else
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+ } else {
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+ /* TXB has a single data lane, no need to adjust. */
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io10 |= ADV748X_IO_10_CSI1_EN;
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+ }
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}
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- if (state->hdmi.tx)
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+ if (state->hdmi.tx) {
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+ /*
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+ * Restore the number of active lanes, in case we have gone
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+ * through an AFE->TXA streaming sessions.
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+ */
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+ tx->active_lanes = tx->num_lanes;
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io10 |= ADV748X_IO_10_CSI4_EN;
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+ }
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return io_clrset(state, ADV748X_IO_10, io10_mask, io10);
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}
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@@ -596,6 +611,7 @@ static int adv748x_parse_csi2_lanes(stru
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}
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state->txa.num_lanes = num_lanes;
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+ state->txa.active_lanes = num_lanes;
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adv_dbg(state, "TXA: using %u lanes\n", state->txa.num_lanes);
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}
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@@ -607,6 +623,7 @@ static int adv748x_parse_csi2_lanes(stru
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}
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state->txb.num_lanes = num_lanes;
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+ state->txb.active_lanes = num_lanes;
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adv_dbg(state, "TXB: using %u lanes\n", state->txb.num_lanes);
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}
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--- a/drivers/media/i2c/adv748x/adv748x.h
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+++ b/drivers/media/i2c/adv748x/adv748x.h
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@@ -79,6 +79,7 @@ struct adv748x_csi2 {
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unsigned int page;
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unsigned int port;
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unsigned int num_lanes;
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+ unsigned int active_lanes;
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struct media_pad pads[ADV748X_CSI2_NR_PADS];
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struct v4l2_ctrl_handler ctrl_hdl;
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