131 lines
4.7 KiB
Diff
131 lines
4.7 KiB
Diff
From e9898a39fce7db84ae56329d4f90da92af3bd584 Mon Sep 17 00:00:00 2001
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From: P33M <P33M@github.com>
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Date: Wed, 24 Sep 2014 11:57:51 +0100
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Subject: [PATCH 091/114] dwc_otg: FIQ support on SMP. Set up FIQ stack and
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handler on Core 0 only.
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---
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drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 96 ++++++++++++++--------------
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1 file changed, 49 insertions(+), 47 deletions(-)
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--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
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@@ -397,7 +397,55 @@ static struct fiq_handler fh = {
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.name = "usb_fiq",
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};
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+static void hcd_init_fiq(void *cookie)
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+{
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+ dwc_otg_device_t *otg_dev = cookie;
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+ dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
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+ struct pt_regs regs;
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+
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+ if (claim_fiq(&fh)) {
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+ DWC_ERROR("Can't claim FIQ");
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+ BUG();
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+ }
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+ DWC_WARN("FIQ at 0x%08x", (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop));
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+ DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));
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+ set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);
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+ memset(®s,0,sizeof(regs));
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+
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+ regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state;
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+ if (fiq_fsm_enable) {
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+ regs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels;
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+ //regs.ARM_r10 = dwc_otg_hcd->dma;
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+ regs.ARM_fp = (long) dwc_otg_fiq_fsm;
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+ } else {
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+ regs.ARM_fp = (long) dwc_otg_fiq_nop;
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+ }
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+
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+ regs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4);
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+
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+// __show_regs(®s);
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+ set_fiq_regs(®s);
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+ //Set the mphi periph to the required registers
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+ dwc_otg_hcd->fiq_state->mphi_regs.base = otg_dev->os_dep.mphi_base;
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+ dwc_otg_hcd->fiq_state->mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c;
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+ dwc_otg_hcd->fiq_state->mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28;
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+ dwc_otg_hcd->fiq_state->mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c;
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+ dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50;
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+ dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
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+ DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
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+ //Enable mphi peripheral
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+ writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
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+#ifdef DEBUG
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+ if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000)
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+ DWC_WARN("MPHI periph has been enabled");
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+ else
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+ DWC_WARN("MPHI periph has NOT been enabled");
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+#endif
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+ // Enable FIQ interrupt from USB peripheral
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+ enable_fiq(INTERRUPT_VC_USB);
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+ local_fiq_enable();
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+}
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/**
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* Initializes the HCD. This function allocates memory for and initializes the
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@@ -412,7 +460,6 @@ int hcd_init(dwc_bus_dev_t *_dev)
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dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
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int retval = 0;
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u64 dmamask;
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- struct pt_regs regs;
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DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT otg_dev=%p\n", otg_dev);
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@@ -464,52 +511,7 @@ int hcd_init(dwc_bus_dev_t *_dev)
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}
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if (fiq_enable)
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- {
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- if (claim_fiq(&fh)) {
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- DWC_ERROR("Can't claim FIQ");
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- goto error2;
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- }
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-
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- DWC_WARN("FIQ at 0x%08x", (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop));
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- DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));
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-
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- set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);
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- memset(®s,0,sizeof(regs));
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-
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- regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state;
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- if (fiq_fsm_enable) {
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- regs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels;
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- //regs.ARM_r10 = dwc_otg_hcd->dma;
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- regs.ARM_fp = (long) dwc_otg_fiq_fsm;
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- } else {
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- regs.ARM_fp = (long) dwc_otg_fiq_nop;
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- }
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-
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- regs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4);
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-
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-// __show_regs(®s);
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- set_fiq_regs(®s);
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-
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- //Set the mphi periph to the required registers
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- dwc_otg_hcd->fiq_state->mphi_regs.base = otg_dev->os_dep.mphi_base;
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- dwc_otg_hcd->fiq_state->mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c;
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- dwc_otg_hcd->fiq_state->mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28;
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- dwc_otg_hcd->fiq_state->mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c;
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- dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50;
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- dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
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- DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
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- //Enable mphi peripheral
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- writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
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-#ifdef DEBUG
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- if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000)
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- DWC_WARN("MPHI periph has been enabled");
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- else
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- DWC_WARN("MPHI periph has NOT been enabled");
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-#endif
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- // Enable FIQ interrupt from USB peripheral
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- enable_fiq(INTERRUPT_VC_USB);
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- local_fiq_enable();
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- }
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+ smp_call_function_single(0, hcd_init_fiq, otg_dev, 1);
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otg_dev->hcd->otg_dev = otg_dev;
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