758a4d1766
This patch contains updated driver for Atheros NAND Flash Controller written originally by Gabor Juhos for ar71xx (aka 'ar934x-nfc'). ath79 version has adapted to work with kernel 4.19 and Device Tree. It has also been renamed to 'ar934x-nand' to avoid confusion with Near-Field Communication technology. Controller is present on Atheros AR934x SoCs and required for accessing internal flash storage on routers like Netgear WNDR4300. This port preserves all NAND programming code while moving platform configuration to Device Tree and replacing some kernel functions marked for retirement by 4.19. Suitable definition is included in 'ar934x.dtsi' ('nand@1b000200' section). Most important changes to ar71xx version are: * old kernel sections of code removed * 'bool swap_dma' provided by platform data is now set by boolean DT property 'qca,nand-swap-dma' * board-supplied (mach-*.c code) platform data removed - its elements become either unused, redundant or replaced by DT methods (like reset) * IRQ is reserved by devm_request_irq() so free_irq() is not needed anymore * calls to deprecated nand_scan_ident() + nand_scan_tail() function pair replaced by using recommended nand_scan() with attach_chip() callback * ECC is set to hardware by default, can be overriden by standard DT 'nand-ecc-*' properties (software Hamming or BCH are other options) This driver has been successfully tested on Netgear WNDR4300 running experimental ath79 OpenWrt master branch. Signed-off-by: Michal Cieslakiewicz <michal.cieslakiewicz@wp.pl> [add reset control] Signed-off-by: David Bauer <mail@david-bauer.net>
272 lines
4.6 KiB
Plaintext
272 lines
4.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include <dt-bindings/clock/ath79-clk.h>
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#include "ath79.dtsi"
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/ {
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compatible = "qca,ar9340";
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "mips,mips74Kc";
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clocks = <&pll ATH79_CLK_CPU>;
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reg = <0>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ref: ref {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-output-names = "ref";
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};
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};
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ahb: ahb {
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compatible = "simple-bus";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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apb: apb {
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compatible = "simple-bus";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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ddr_ctrl: memory-controller@18000000 {
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compatible = "qca,ar9340-ddr-controller",
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"qca,ar7240-ddr-controller";
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reg = <0x18000000 0x12c>;
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#qca,ddr-wb-channel-cells = <1>;
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};
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uart: uart@18020000 {
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compatible = "ns16550a";
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reg = <0x18020000 0x2c>;
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interrupts = <3>;
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clocks = <&pll ATH79_CLK_REF>;
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clock-names = "uart";
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reg-io-width = <4>;
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reg-shift = <2>;
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no-loopback-test;
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status = "disabled";
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};
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gpio: gpio@18040000 {
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compatible = "qca,ar9340-gpio";
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reg = <0x18040000 0x2c>;
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interrupts = <2>;
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ngpios = <23>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pinmux: pinmux@1804002c {
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compatible = "pinctrl-single";
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reg = <0x1804002c 0x44>;
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#size-cells = <0>;
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x1>;
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#pinctrl-cells = <2>;
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jtag_disable_pins: pinmux_jtag_disable_pins {
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pinctrl-single,bits = <0x40 0x2 0x2>;
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};
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};
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pll: pll-controller@18050000 {
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compatible = "qca,ar9340-pll", "syscon";
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reg = <0x18050000 0x4c>;
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#clock-cells = <1>;
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clocks = <&ref>;
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clock-names = "ref";
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clock-output-names = "cpu", "ddr", "ahb";
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};
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wdt: wdt@18060008 {
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compatible = "qca,ar9340-wdt", "qca,ar7130-wdt";
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reg = <0x18060008 0x8>;
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interrupts = <4>;
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clocks = <&pll ATH79_CLK_AHB>;
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clock-names = "wdt";
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};
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rst: reset-controller@1806001c {
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compatible = "qca,ar9340-reset", "qca,ar7100-reset";
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reg = <0x1806001c 0x4>;
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#reset-cells = <1>;
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};
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};
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nand: nand@1b000200 {
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compatible = "qca,ar934x-nand";
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reg = <0x1b000200 0xb8>;
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interrupts = <21>;
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interrupt-parent = <&miscintc>;
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resets = <&rst 14>;
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reset-names = "nand";
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nand-ecc-mode = "hw";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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gmac: gmac@18070000 {
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compatible = "qca,ar9340-gmac";
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reg = <0x18070000 0x14>;
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};
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wmac: wmac@18100000 {
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compatible = "qca,ar9340-wmac";
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reg = <0x18100000 0x20000>;
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status = "disabled";
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};
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usb: usb@1b000000 {
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compatible = "generic-ehci";
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reg = <0x1b000000 0x1d8>;
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interrupts = <3>;
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resets = <&rst 5>;
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reset-names = "usb-host";
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has-transaction-translator;
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caps-offset = <0x100>;
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phy-names = "usb-phy";
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phys = <&usb_phy>;
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status = "disabled";
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};
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spi: spi@1f000000 {
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compatible = "qca,ar9340-spi", "qca,ar7100-spi";
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reg = <0x1f000000 0x1c>;
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clocks = <&pll ATH79_CLK_AHB>;
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clock-names = "ahb";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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usb_phy: usb-phy {
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compatible = "qca,ar9340-usb-phy", "qca,ar7200-usb-phy";
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reset-names = "usb-phy", "usb-suspend-override";
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resets = <&rst 4>, <&rst 3>;
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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&mdio0 {
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compatible = "qca,ar9340-mdio";
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};
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ð0 {
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compatible = "qca,ar9340-eth", "syscon";
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pll-data = <0x16000000 0x00000101 0x00001616>;
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pll-reg = <0x4 0x2c 17>;
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pll-handle = <&pll>;
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resets = <&rst 9>, <&rst 22>;
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reset-names = "mac", "mdio";
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};
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&mdio1 {
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status = "okay";
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compatible = "qca,ar9340-mdio";
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resets = <&rst 23>;
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reset-names = "mdio";
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builtin-switch;
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builtin_switch: switch0@1f {
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compatible = "qca,ar8229";
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reg = <0x1f>;
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resets = <&rst 8>;
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reset-names = "switch";
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phy-mode = "gmii";
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qca,mib-poll-interval = <500>;
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qca,phy4-mii-enable;
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mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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swphy0: ethernet-phy@0 {
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reg = <0>;
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phy-mode = "mii";
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};
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swphy4: ethernet-phy@4 {
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reg = <4>;
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phy-mode = "mii";
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};
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};
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};
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};
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ð1 {
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compatible = "qca,ar9340-eth", "syscon";
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resets = <&rst 13>;
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reset-names = "mac";
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phy-mode = "gmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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