ca49bcadae
Instead of setting the l2c_aux_val variable in the board code make it possible to set these through device tree and make use of that. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 46129
130 lines
4.5 KiB
Diff
130 lines
4.5 KiB
Diff
From 5b290ec2074c68b9f4f8f8789fa9b3e1782869e7 Mon Sep 17 00:00:00 2001
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From: Russell King <rmk+kernel@arm.linux.org.uk>
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Date: Fri, 15 May 2015 12:03:29 +0100
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Subject: [PATCH 74/74] ARM: l2c: avoid passing auxiliary control register
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through enable method
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Avoid passing the auxiliary control register value through the enable
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method. In the resume path, we have to read the value stored in
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l2x0_saved_regs.aux_ctrl, only to have it immediately written back by
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l2c_enable(). We can avoid this if we have __l2c_init() save the value
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directly to l2x0_saved_regs.aux_ctrl before calling the specific enable
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method.
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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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---
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arch/arm/mm/cache-l2x0.c | 32 +++++++++++++++++---------------
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1 file changed, 17 insertions(+), 15 deletions(-)
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--- a/arch/arm/mm/cache-l2x0.c
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+++ b/arch/arm/mm/cache-l2x0.c
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@@ -38,7 +38,7 @@ struct l2c_init_data {
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unsigned way_size_0;
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unsigned num_lock;
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void (*of_parse)(const struct device_node *, u32 *, u32 *);
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- void (*enable)(void __iomem *, u32, unsigned);
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+ void (*enable)(void __iomem *, unsigned);
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void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
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void (*save)(void __iomem *);
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void (*configure)(void __iomem *);
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@@ -118,12 +118,10 @@ static void l2c_configure(void __iomem *
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* Enable the L2 cache controller. This function must only be
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* called when the cache controller is known to be disabled.
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*/
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-static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock)
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+static void l2c_enable(void __iomem *base, unsigned num_lock)
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{
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unsigned long flags;
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- l2x0_saved_regs.aux_ctrl = aux;
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-
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if (outer_cache.configure)
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outer_cache.configure(&l2x0_saved_regs);
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else
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@@ -160,7 +158,7 @@ static void l2c_resume(void)
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/* Do not touch the controller if already enabled. */
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if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
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- l2c_enable(base, l2x0_saved_regs.aux_ctrl, l2x0_data->num_lock);
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+ l2c_enable(base, l2x0_data->num_lock);
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}
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/*
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@@ -390,16 +388,16 @@ static void l2c220_sync(void)
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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-static void l2c220_enable(void __iomem *base, u32 aux, unsigned num_lock)
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+static void l2c220_enable(void __iomem *base, unsigned num_lock)
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{
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/*
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* Always enable non-secure access to the lockdown registers -
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* we write to them as part of the L2C enable sequence so they
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* need to be accessible.
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*/
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- aux |= L220_AUX_CTRL_NS_LOCKDOWN;
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+ l2x0_saved_regs.aux_ctrl |= L220_AUX_CTRL_NS_LOCKDOWN;
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- l2c_enable(base, aux, num_lock);
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+ l2c_enable(base, num_lock);
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}
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static void l2c220_unlock(void __iomem *base, unsigned num_lock)
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@@ -612,10 +610,11 @@ static int l2c310_cpu_enable_flz(struct
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return NOTIFY_OK;
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}
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-static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock)
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+static void __init l2c310_enable(void __iomem *base, unsigned num_lock)
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{
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unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK;
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bool cortex_a9 = read_cpuid_part() == ARM_CPU_PART_CORTEX_A9;
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+ u32 aux = l2x0_saved_regs.aux_ctrl;
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if (rev >= L310_CACHE_ID_RTL_R2P0) {
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if (cortex_a9) {
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@@ -658,9 +657,9 @@ static void __init l2c310_enable(void __
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* we write to them as part of the L2C enable sequence so they
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* need to be accessible.
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*/
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- aux |= L310_AUX_CTRL_NS_LOCKDOWN;
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+ l2x0_saved_regs.aux_ctrl = aux | L310_AUX_CTRL_NS_LOCKDOWN;
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- l2c_enable(base, aux, num_lock);
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+ l2c_enable(base, num_lock);
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/* Read back resulting AUX_CTRL value as it could have been altered. */
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aux = readl_relaxed(base + L2X0_AUX_CTRL);
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@@ -872,8 +871,11 @@ static int __init __l2c_init(const struc
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* Check if l2x0 controller is already enabled. If we are booting
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* in non-secure mode accessing the below registers will fault.
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*/
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- if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
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- data->enable(l2x0_base, aux, data->num_lock);
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+ if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
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+ l2x0_saved_regs.aux_ctrl = aux;
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+
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+ data->enable(l2x0_base, data->num_lock);
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+ }
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outer_cache = fns;
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@@ -1388,7 +1390,7 @@ static void aurora_save(void __iomem *ba
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* For Aurora cache in no outer mode, enable via the CP15 coprocessor
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* broadcasting of cache commands to L2.
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*/
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-static void __init aurora_enable_no_outer(void __iomem *base, u32 aux,
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+static void __init aurora_enable_no_outer(void __iomem *base,
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unsigned num_lock)
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{
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u32 u;
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@@ -1399,7 +1401,7 @@ static void __init aurora_enable_no_oute
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isb();
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- l2c_enable(base, aux, num_lock);
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+ l2c_enable(base, num_lock);
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}
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static void __init aurora_fixup(void __iomem *base, u32 cache_id,
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