116 lines
3.3 KiB
C
116 lines
3.3 KiB
C
#include "xhci-mtk.h"
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#include "xhci-mtk-power.h"
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#include "xhci.h"
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#include <linux/kernel.h> /* printk() */
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#include <linux/slab.h>
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#include <linux/delay.h>
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static int g_num_u3_port;
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static int g_num_u2_port;
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void enableXhciAllPortPower(struct xhci_hcd *xhci){
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int i;
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u32 port_id, temp;
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u32 __iomem *addr;
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g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
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g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
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for(i=1; i<=g_num_u3_port; i++){
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port_id=i;
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addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
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temp = xhci_readl(xhci, addr);
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temp = xhci_port_state_to_neutral(temp);
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temp |= PORT_POWER;
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xhci_writel(xhci, temp, addr);
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}
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for(i=1; i<=g_num_u2_port; i++){
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port_id=i+g_num_u3_port;
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addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
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temp = xhci_readl(xhci, addr);
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temp = xhci_port_state_to_neutral(temp);
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temp |= PORT_POWER;
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xhci_writel(xhci, temp, addr);
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}
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}
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void enableAllClockPower(){
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int i;
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u32 temp;
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g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
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g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
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//2. Enable xHC
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writel(readl(SSUSB_IP_PW_CTRL) | (SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
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writel(readl(SSUSB_IP_PW_CTRL) & (~SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
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writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
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//1. Enable target ports
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for(i=0; i<g_num_u3_port; i++){
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temp = readl(SSUSB_U3_CTRL(i));
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temp = temp & (~SSUSB_U3_PORT_PDN) & (~SSUSB_U3_PORT_DIS);
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writel(temp, SSUSB_U3_CTRL(i));
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}
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for(i=0; i<g_num_u2_port; i++){
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temp = readl(SSUSB_U2_CTRL(i));
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temp = temp & (~SSUSB_U2_PORT_PDN) & (~SSUSB_U2_PORT_DIS);
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writel(temp, SSUSB_U2_CTRL(i));
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}
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msleep(100);
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}
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//(X)disable clock/power of a port
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//(X)if all ports are disabled, disable IP ctrl power
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//disable all ports and IP clock/power, this is just mention HW that the power/clock of port
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//and IP could be disable if suspended.
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//If doesn't not disable all ports at first, the IP clock/power will never be disabled
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//(some U2 and U3 ports are binded to the same connection, that is, they will never enter suspend at the same time
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//port_index: port number
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//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
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void disablePortClockPower(void){
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int i;
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u32 temp;
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g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
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g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
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for(i=0; i<g_num_u3_port; i++){
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temp = readl(SSUSB_U3_CTRL(i));
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temp = temp | (SSUSB_U3_PORT_PDN);
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writel(temp, SSUSB_U3_CTRL(i));
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}
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for(i=0; i<g_num_u2_port; i++){
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temp = readl(SSUSB_U2_CTRL(i));
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temp = temp | (SSUSB_U2_PORT_PDN);
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writel(temp, SSUSB_U2_CTRL(i));
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}
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writel(readl(SSUSB_IP_PW_CTRL_1) | (SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
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}
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//if IP ctrl power is disabled, enable it
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//enable clock/power of a port
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//port_index: port number
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//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
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void enablePortClockPower(int port_index, int port_rev){
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int i;
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u32 temp;
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writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
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if(port_rev == 0x3){
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temp = readl(SSUSB_U3_CTRL(port_index));
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temp = temp & (~SSUSB_U3_PORT_PDN);
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writel(temp, SSUSB_U3_CTRL(port_index));
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}
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else if(port_rev == 0x2){
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temp = readl(SSUSB_U2_CTRL(port_index));
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temp = temp & (~SSUSB_U2_PORT_PDN);
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writel(temp, SSUSB_U2_CTRL(port_index));
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}
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}
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