Openwrt/target/linux/ramips/dts/mt7620a_zte_q7.dts
Adrian Schmutzler 48047b3a5c ramips/mt7620: Name DTS files based on scheme
As introduced with ath79, DTS files for ramips will now be labelled
soc_vendor_device.dts(i). With this change, DTS files can be
selected automatically without further manual links.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2019-07-10 17:36:29 +02:00

126 lines
1.8 KiB
Plaintext

/dts-v1/;
#include "mt7620a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
compatible = "zte,q7", "ralink,mt7620a-soc";
model = "ZTE Q7";
aliases {
led-boot = &led_status_blue;
led-failsafe = &led_status_blue;
led-running = &led_status_blue;
led-upgrade = &led_status_blue;
};
leds {
compatible = "gpio-leds";
statred {
label = "zte-q7:red:status";
gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
};
led_status_blue: statblue {
label = "zte-q7:blue:status";
gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys-polled";
poll-interval = <20>;
reset {
label = "reset";
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&spi0 {
status = "okay";
m25p80@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x30000>;
read-only;
};
partition@30000 {
label = "u-boot-env";
reg = <0x30000 0x10000>;
read-only;
};
factory: partition@40000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
};
partition@50000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x50000 0x7b0000>;
};
};
};
};
&pinctrl {
state_default: pinctrl0 {
gpio {
ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled";
ralink,function = "gpio";
};
};
};
&ethernet {
mtd-mac-address = <&factory 0x4>;
mediatek,portmap = "wllll";
};
&wmac {
ralink,mtd-eeprom = <&factory 0>;
};
&sdhci {
status = "okay";
};
&ehci {
status = "okay";
};
&ohci {
status = "okay";
};
&gsw {
mediatek,port4 = "ephy";
};