d4b4c7d102
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 34881
83 lines
1.9 KiB
C
83 lines
1.9 KiB
C
/*
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* AR8216 switch driver platform data
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*
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* Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef AR8216_PLATFORM_H
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#define AR8216_PLATFORM_H
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enum ar8327_pad_mode {
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AR8327_PAD_NC = 0,
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AR8327_PAD_MAC2MAC_MII,
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AR8327_PAD_MAC2MAC_GMII,
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AR8327_PAD_MAC_SGMII,
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AR8327_PAD_MAC2PHY_MII,
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AR8327_PAD_MAC2PHY_GMII,
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AR8327_PAD_MAC_RGMII,
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AR8327_PAD_PHY_GMII,
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AR8327_PAD_PHY_RGMII,
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AR8327_PAD_PHY_MII,
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};
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enum ar8327_clk_delay_sel {
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AR8327_CLK_DELAY_SEL0 = 0,
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AR8327_CLK_DELAY_SEL1,
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AR8327_CLK_DELAY_SEL2,
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AR8327_CLK_DELAY_SEL3,
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};
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struct ar8327_pad_cfg {
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enum ar8327_pad_mode mode;
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bool rxclk_sel;
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bool txclk_sel;
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bool pipe_rxclk_sel;
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bool txclk_delay_en;
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bool rxclk_delay_en;
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bool sgmii_delay_en;
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enum ar8327_clk_delay_sel txclk_delay_sel;
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enum ar8327_clk_delay_sel rxclk_delay_sel;
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};
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enum ar8327_port_speed {
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AR8327_PORT_SPEED_10 = 0,
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AR8327_PORT_SPEED_100,
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AR8327_PORT_SPEED_1000,
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};
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struct ar8327_port_cfg {
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int force_link:1;
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enum ar8327_port_speed speed;
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int txpause:1;
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int rxpause:1;
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int duplex:1;
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};
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struct ar8327_led_cfg {
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u32 led_ctrl0;
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u32 led_ctrl1;
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u32 led_ctrl2;
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u32 led_ctrl3;
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bool open_drain;
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};
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struct ar8327_platform_data {
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struct ar8327_pad_cfg *pad0_cfg;
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struct ar8327_pad_cfg *pad5_cfg;
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struct ar8327_pad_cfg *pad6_cfg;
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struct ar8327_port_cfg port0_cfg;
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struct ar8327_port_cfg port6_cfg;
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struct ar8327_led_cfg *led_cfg;
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};
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#endif /* AR8216_PLATFORM_H */ |