52 lines
1.8 KiB
Diff
52 lines
1.8 KiB
Diff
From 52a1c4e3aa9027040c1adc69303aaffc3c2cbaab Mon Sep 17 00:00:00 2001
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Thu, 16 May 2013 17:55:21 +0200
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Subject: [PATCH 05/29] clk: mvebu: add more PCIe clocks for Armada XP
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The current revision of the datasheet only mentions the gatable clocks
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for the PCIe 0.0, 0.1, 0.2 and 0.3 interfaces, and forgot to mention
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the ones for the PCIe 1.0, 1.1, 1.2, 1.3, 2.0 and 3.0
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interfaces. After confirmation with Marvell engineers, this patch adds
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the missing gatable clocks for those PCIe interfaces.
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It also changes the name of the previously existing PCIe gatable
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clocks, in order to match the naming using the datasheets.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Cc: Mike Turquette <mturquette@linaro.org>
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Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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---
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drivers/clk/mvebu/clk-gating-ctrl.c | 14 ++++++++++----
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1 file changed, 10 insertions(+), 4 deletions(-)
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--- a/drivers/clk/mvebu/clk-gating-ctrl.c
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+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
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@@ -137,10 +137,14 @@ static const struct mvebu_soc_descr __in
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{ "ge2", NULL, 2 },
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{ "ge1", NULL, 3 },
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{ "ge0", NULL, 4 },
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- { "pex0", NULL, 5 },
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- { "pex1", NULL, 6 },
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- { "pex2", NULL, 7 },
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- { "pex3", NULL, 8 },
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+ { "pex00", NULL, 5 },
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+ { "pex01", NULL, 6 },
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+ { "pex02", NULL, 7 },
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+ { "pex03", NULL, 8 },
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+ { "pex10", NULL, 9 },
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+ { "pex11", NULL, 10 },
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+ { "pex12", NULL, 11 },
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+ { "pex13", NULL, 12 },
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{ "bp", NULL, 13 },
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{ "sata0lnk", NULL, 14 },
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{ "sata0", "sata0lnk", 15 },
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@@ -152,6 +156,8 @@ static const struct mvebu_soc_descr __in
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{ "xor0", NULL, 22 },
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{ "crypto", NULL, 23 },
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{ "tdm", NULL, 25 },
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+ { "pex20", NULL, 26 },
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+ { "pex30", NULL, 27 },
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{ "xor1", NULL, 28 },
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{ "sata1lnk", NULL, 29 },
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{ "sata1", "sata1lnk", 30 },
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