66f8f30f47
Update patches with their upstream versions. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 37098
347 lines
12 KiB
Diff
347 lines
12 KiB
Diff
From 33cab1696444a8e333cf0490bfe04c32d583fd51 Mon Sep 17 00:00:00 2001
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From: Maxime Bizon <mbizon@freebox.fr>
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Date: Tue, 4 Jun 2013 20:53:34 +0000
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Subject: [PATCH 2/3] bcm63xx_enet: split DMA channel register accesses
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The current bcm63xx_enet driver always uses bcmenet_shared_base whenever
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it needs to access DMA channel configuration space or access the DMA
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channel state RAM. Split these register in 3 parts to be more accurate:
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- global DMA configuration
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- per DMA channel configuration space
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- per DMA channel state RAM space
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This is preliminary to support new chips where the global DMA
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configuration remains the same, but there is a varying number of DMA
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channels located at a different memory offset.
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Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/bcm63xx/dev-enet.c | 23 +++-
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 4 +-
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drivers/net/ethernet/broadcom/bcm63xx_enet.c | 139 +++++++++++++---------
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3 files changed, 105 insertions(+), 61 deletions(-)
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--- a/arch/mips/bcm63xx/dev-enet.c
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+++ b/arch/mips/bcm63xx/dev-enet.c
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@@ -19,6 +19,16 @@ static struct resource shared_res[] = {
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.end = -1, /* filled at runtime */
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.flags = IORESOURCE_MEM,
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},
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+ {
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+ .start = -1, /* filled at runtime */
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+ .end = -1, /* filled at runtime */
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .start = -1, /* filled at runtime */
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+ .end = -1, /* filled at runtime */
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+ .flags = IORESOURCE_MEM,
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+ },
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};
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static struct platform_device bcm63xx_enet_shared_device = {
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@@ -110,10 +120,15 @@ int __init bcm63xx_enet_register(int uni
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if (!shared_device_registered) {
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shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
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shared_res[0].end = shared_res[0].start;
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- if (BCMCPU_IS_6338())
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- shared_res[0].end += (RSET_ENETDMA_SIZE / 2) - 1;
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- else
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- shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
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+ shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
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+
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+ shared_res[1].start = bcm63xx_regset_address(RSET_ENETDMAC);
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+ shared_res[1].end = shared_res[1].start;
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+ shared_res[1].end += RSET_ENETDMAC_SIZE(16) - 1;
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+
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+ shared_res[2].start = bcm63xx_regset_address(RSET_ENETDMAS);
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+ shared_res[2].end = shared_res[2].start;
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+ shared_res[2].end += RSET_ENETDMAS_SIZE(16) - 1;
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ret = platform_device_register(&bcm63xx_enet_shared_device);
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if (ret)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -187,7 +187,9 @@ enum bcm63xx_regs_set {
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#define BCM_6358_RSET_SPI_SIZE 1804
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#define BCM_6368_RSET_SPI_SIZE 1804
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#define RSET_ENET_SIZE 2048
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-#define RSET_ENETDMA_SIZE 2048
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+#define RSET_ENETDMA_SIZE 256
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+#define RSET_ENETDMAC_SIZE(chans) (16 * (chans))
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+#define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
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#define RSET_ENETSW_SIZE 65536
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#define RSET_UART_SIZE 24
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#define RSET_UDC_SIZE 256
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--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
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+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
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@@ -41,8 +41,8 @@ static int copybreak __read_mostly = 128
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module_param(copybreak, int, 0);
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MODULE_PARM_DESC(copybreak, "Receive copy threshold");
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-/* io memory shared between all devices */
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-static void __iomem *bcm_enet_shared_base;
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+/* io registers memory shared between all devices */
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+static void __iomem *bcm_enet_shared_base[3];
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/*
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* io helpers to access mac registers
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@@ -63,13 +63,35 @@ static inline void enet_writel(struct bc
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*/
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static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
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{
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- return bcm_readl(bcm_enet_shared_base + off);
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+ return bcm_readl(bcm_enet_shared_base[0] + off);
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}
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static inline void enet_dma_writel(struct bcm_enet_priv *priv,
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u32 val, u32 off)
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{
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- bcm_writel(val, bcm_enet_shared_base + off);
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+ bcm_writel(val, bcm_enet_shared_base[0] + off);
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+}
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+
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+static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off)
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+{
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+ return bcm_readl(bcm_enet_shared_base[1] + off);
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+}
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+
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+static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
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+ u32 val, u32 off)
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+{
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+ bcm_writel(val, bcm_enet_shared_base[1] + off);
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+}
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+
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+static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off)
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+{
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+ return bcm_readl(bcm_enet_shared_base[2] + off);
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+}
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+
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+static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
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+ u32 val, u32 off)
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+{
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+ bcm_writel(val, bcm_enet_shared_base[2] + off);
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}
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/*
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@@ -353,8 +375,8 @@ static int bcm_enet_receive_queue(struct
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bcm_enet_refill_rx(dev);
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/* kick rx dma */
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- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
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- ENETDMA_CHANCFG_REG(priv->rx_chan));
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+ enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
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+ ENETDMAC_CHANCFG_REG(priv->rx_chan));
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}
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return processed;
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@@ -429,10 +451,10 @@ static int bcm_enet_poll(struct napi_str
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dev = priv->net_dev;
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/* ack interrupts */
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- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
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- ENETDMA_IR_REG(priv->rx_chan));
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- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
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- ENETDMA_IR_REG(priv->tx_chan));
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+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
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+ ENETDMAC_IR_REG(priv->rx_chan));
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+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
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+ ENETDMAC_IR_REG(priv->tx_chan));
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/* reclaim sent skb */
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tx_work_done = bcm_enet_tx_reclaim(dev, 0);
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@@ -451,10 +473,10 @@ static int bcm_enet_poll(struct napi_str
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napi_complete(napi);
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/* restore rx/tx interrupt */
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- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
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- ENETDMA_IRMASK_REG(priv->rx_chan));
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- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
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- ENETDMA_IRMASK_REG(priv->tx_chan));
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+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
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+ ENETDMAC_IRMASK_REG(priv->rx_chan));
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+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
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+ ENETDMAC_IRMASK_REG(priv->tx_chan));
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return rx_work_done;
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}
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@@ -497,8 +519,8 @@ static irqreturn_t bcm_enet_isr_dma(int
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priv = netdev_priv(dev);
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/* mask rx/tx interrupts */
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- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
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- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
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+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
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+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
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napi_schedule(&priv->napi);
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@@ -557,8 +579,8 @@ static int bcm_enet_start_xmit(struct sk
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wmb();
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/* kick tx dma */
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- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
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- ENETDMA_CHANCFG_REG(priv->tx_chan));
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+ enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
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+ ENETDMAC_CHANCFG_REG(priv->tx_chan));
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/* stop queue if no more desc available */
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if (!priv->tx_desc_count)
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@@ -833,8 +855,8 @@ static int bcm_enet_open(struct net_devi
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/* mask all interrupts and request them */
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enet_writel(priv, 0, ENET_IRMASK_REG);
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- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
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- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
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+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
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+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
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ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
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if (ret)
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@@ -921,28 +943,28 @@ static int bcm_enet_open(struct net_devi
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}
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/* write rx & tx ring addresses */
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- enet_dma_writel(priv, priv->rx_desc_dma,
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- ENETDMA_RSTART_REG(priv->rx_chan));
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- enet_dma_writel(priv, priv->tx_desc_dma,
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- ENETDMA_RSTART_REG(priv->tx_chan));
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+ enet_dmas_writel(priv, priv->rx_desc_dma,
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+ ENETDMAS_RSTART_REG(priv->rx_chan));
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+ enet_dmas_writel(priv, priv->tx_desc_dma,
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+ ENETDMAS_RSTART_REG(priv->tx_chan));
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/* clear remaining state ram for rx & tx channel */
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- enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
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- enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
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- enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
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- enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
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- enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
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- enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
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+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
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+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
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+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
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+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
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+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
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+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
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/* set max rx/tx length */
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enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
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enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
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/* set dma maximum burst len */
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- enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
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- ENETDMA_MAXBURST_REG(priv->rx_chan));
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- enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
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- ENETDMA_MAXBURST_REG(priv->tx_chan));
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+ enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
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+ ENETDMAC_MAXBURST_REG(priv->rx_chan));
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+ enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
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+ ENETDMAC_MAXBURST_REG(priv->tx_chan));
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/* set correct transmit fifo watermark */
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enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
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@@ -960,26 +982,26 @@ static int bcm_enet_open(struct net_devi
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val |= ENET_CTL_ENABLE_MASK;
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enet_writel(priv, val, ENET_CTL_REG);
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enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
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- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
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- ENETDMA_CHANCFG_REG(priv->rx_chan));
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+ enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
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+ ENETDMAC_CHANCFG_REG(priv->rx_chan));
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/* watch "mib counters about to overflow" interrupt */
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enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
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enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
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/* watch "packet transferred" interrupt in rx and tx */
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- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
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- ENETDMA_IR_REG(priv->rx_chan));
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- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
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- ENETDMA_IR_REG(priv->tx_chan));
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+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
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+ ENETDMAC_IR_REG(priv->rx_chan));
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+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
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+ ENETDMAC_IR_REG(priv->tx_chan));
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/* make sure we enable napi before rx interrupt */
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napi_enable(&priv->napi);
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- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
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- ENETDMA_IRMASK_REG(priv->rx_chan));
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- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
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- ENETDMA_IRMASK_REG(priv->tx_chan));
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+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
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+ ENETDMAC_IRMASK_REG(priv->rx_chan));
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+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
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+ ENETDMAC_IRMASK_REG(priv->tx_chan));
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if (priv->has_phy)
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phy_start(priv->phydev);
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@@ -1059,14 +1081,14 @@ static void bcm_enet_disable_dma(struct
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{
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int limit;
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- enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
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+ enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG_REG(chan));
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limit = 1000;
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do {
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u32 val;
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- val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
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- if (!(val & ENETDMA_CHANCFG_EN_MASK))
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+ val = enet_dmac_readl(priv, ENETDMAC_CHANCFG_REG(chan));
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+ if (!(val & ENETDMAC_CHANCFG_EN_MASK))
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break;
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udelay(1);
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} while (limit--);
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@@ -1092,8 +1114,8 @@ static int bcm_enet_stop(struct net_devi
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/* mask all interrupts */
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enet_writel(priv, 0, ENET_IRMASK_REG);
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- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
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- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
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+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
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+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
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/* make sure no mib update is scheduled */
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cancel_work_sync(&priv->mib_update_task);
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@@ -1638,7 +1660,7 @@ static int bcm_enet_probe(struct platfor
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/* stop if shared driver failed, assume driver->probe will be
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* called in the same order we register devices (correct ?) */
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- if (!bcm_enet_shared_base)
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+ if (!bcm_enet_shared_base[0])
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return -ENODEV;
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res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@@ -1884,14 +1906,19 @@ struct platform_driver bcm63xx_enet_driv
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static int bcm_enet_shared_probe(struct platform_device *pdev)
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{
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struct resource *res;
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+ void __iomem *p[3];
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+ unsigned int i;
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- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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- if (!res)
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- return -ENODEV;
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+ memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
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- bcm_enet_shared_base = devm_request_and_ioremap(&pdev->dev, res);
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- if (!bcm_enet_shared_base)
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- return -ENOMEM;
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+ for (i = 0; i < 3; i++) {
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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+ p[i] = devm_ioremap_resource(&pdev->dev, res);
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+ if (!p[i])
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+ return -ENOMEM;
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+ }
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+
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+ memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
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return 0;
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}
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