Openwrt/target/linux/ar7
2007-09-11 14:50:43 +00:00
..
base-files/default/etc
files disable dsp freq use for vlynq bus clock init, disable external clocking (it locks up on c54apra2+) and revert to internal clocking trying various clock divisors. cleanup: * remove volative and use readl & writel accessors instead * use set_irq_chip & friends for irq setup * use kzalloc instead of kmalloc * secure VINT_VECTOR macro argument * remove unused vlynq_local_id function 2007-09-11 14:50:43 +00:00
image
patches-2.6.22 AR7 will also be running in big-endian on zyxel devices 2007-09-11 06:43:59 +00:00
profiles
src
base-files.mk
config-2.6.22
Makefile