cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
74 lines
2.5 KiB
Diff
74 lines
2.5 KiB
Diff
From 57d3edbdcfee9b677452744bba5c4f08b476872a Mon Sep 17 00:00:00 2001
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From: Marc Kleine-Budde <mkl@pengutronix.de>
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Date: Fri, 1 Mar 2019 15:38:05 +0100
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Subject: [PATCH] can: flexcan: flexcan_irq(): add support for TX mailbox in
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iflag1
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The flexcan IP core has up to 64 mailboxes, each one has a corresponding
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interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
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imask1 or imask2 registers.
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The driver will always use the last mailbox for TX, which falls into the iflag2
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register.
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To support CANFD the payload size has to increase to 64 bytes and the number of
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mailboxes will decrease so much that the TX mailbox will be handled in the
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iflag1 register.
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This patch add support to handle the TX mailbox independent whether it's
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in iflag1 or iflag2 by introducing th flexcan_read_reg_iflag_tx()
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function, similar to flexcan_read_reg_iflag_rx(), for the read path.
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For the write path the function flexcan_write64() is added.
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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---
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drivers/net/can/flexcan.c | 17 +++++++++++++++--
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1 file changed, 15 insertions(+), 2 deletions(-)
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--- a/drivers/net/can/flexcan.c
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+++ b/drivers/net/can/flexcan.c
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@@ -791,11 +791,24 @@ static inline u64 flexcan_read64_mask(st
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return reg & mask;
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}
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+static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
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+{
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+ if (upper_32_bits(val))
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+ priv->write(upper_32_bits(val), addr - 4);
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+ if (lower_32_bits(val))
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+ priv->write(lower_32_bits(val), addr);
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+}
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+
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static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
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{
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return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
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}
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+static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
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+{
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+ return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
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+}
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+
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static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
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{
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return container_of(offload, struct flexcan_priv, offload);
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@@ -932,7 +945,7 @@ static irqreturn_t flexcan_irq(int irq,
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}
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}
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- reg_iflag_tx = (u64)priv->read(®s->iflag2) << 32;
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+ reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
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/* transmission complete interrupt */
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if (reg_iflag_tx & priv->tx_mask) {
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@@ -947,7 +960,7 @@ static irqreturn_t flexcan_irq(int irq,
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/* after sending a RTR frame MB is in RX mode */
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priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
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&priv->tx_mb->can_ctrl);
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- priv->write(priv->tx_mask >> 32, ®s->iflag2);
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+ flexcan_write64(priv, priv->tx_mask, ®s->iflag1);
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netif_wake_queue(dev);
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}
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