cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
97 lines
3.4 KiB
Diff
97 lines
3.4 KiB
Diff
From 30da8769107ce2112f3dc356fd06f0fa5bed7742 Mon Sep 17 00:00:00 2001
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From: Alex Marginean <alexandru.marginean@nxp.com>
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Date: Mon, 6 Jan 2020 17:57:10 +0200
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Subject: [PATCH] drivers: net: phy: aquantia: Add XFI counters
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Adds XFI counters and enables counters for AQR112/412. These are gen 3
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PHYs, the register map is compatible with AQR107 which is gen 2.
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Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
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---
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drivers/net/phy/aquantia_main.c | 27 ++++++++++++++++++++++++---
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1 file changed, 24 insertions(+), 3 deletions(-)
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--- a/drivers/net/phy/aquantia_main.c
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+++ b/drivers/net/phy/aquantia_main.c
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@@ -25,6 +25,12 @@
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#define PHY_ID_AQR112 0x03a1b662
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#define PHY_ID_AQR412 0x03a1b712
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+/* PCS counters */
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+#define MDIO_C45_PCS_STAT_XFI_TX_GOOD_FRAMES 0xc860
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+#define MDIO_C45_PCS_STAT_XFI_TX_BAD_FRAMES 0xc862
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+#define MDIO_C45_PCS_STAT_XFI_RX_GOOD_FRAMES 0xe860
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+#define MDIO_C45_PCS_STAT_XFI_RX_BAD_FRAMES 0xe862
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+
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#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
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#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
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#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
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@@ -153,9 +159,12 @@ struct aqr107_hw_stat {
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const char *name;
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int reg;
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int size;
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+ int devad;
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};
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-#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
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+#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s, \
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+ MDIO_MMD_C22EXT}
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+#define C45_PCS_STAT(n, r, s) { n, MDIO_C45_PCS_STAT_ ## r, s, MDIO_MMD_PCS }
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static const struct aqr107_hw_stat aqr107_hw_stats[] = {
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SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
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SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
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@@ -167,6 +176,10 @@ static const struct aqr107_hw_stat aqr10
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SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
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SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
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SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
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+ C45_PCS_STAT("xfi_rx_good_frames", XFI_RX_GOOD_FRAMES, 26),
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+ C45_PCS_STAT("xfi_rx_bad_frames", XFI_RX_BAD_FRAMES, 26),
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+ C45_PCS_STAT("xfi_tx_good_frames", XFI_TX_GOOD_FRAMES, 26),
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+ C45_PCS_STAT("xfi_tx_bad_frames", XFI_TX_BAD_FRAMES, 26),
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};
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#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
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@@ -196,13 +209,13 @@ static u64 aqr107_get_stat(struct phy_de
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u64 ret;
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int val;
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- val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
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+ val = phy_read_mmd(phydev, stat->devad, stat->reg);
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if (val < 0)
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return U64_MAX;
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ret = val & GENMASK(len_l - 1, 0);
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if (len_h) {
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- val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
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+ val = phy_read_mmd(phydev, stat->devad, stat->reg + 1);
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if (val < 0)
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return U64_MAX;
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@@ -768,18 +781,26 @@ static struct phy_driver aqr_driver[] =
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{
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PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
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.name = "Aquantia AQR112",
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+ .probe = aqr107_probe,
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.config_aneg = aqr_config_aneg_set_prot,
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.config_intr = aqr_config_intr,
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.ack_interrupt = aqr_ack_interrupt,
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.read_status = aqr_read_status,
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+ .get_sset_count = aqr107_get_sset_count,
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+ .get_strings = aqr107_get_strings,
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+ .get_stats = aqr107_get_stats,
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},
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{
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PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
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.name = "Aquantia AQR412",
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+ .probe = aqr107_probe,
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.config_aneg = aqr_config_aneg_set_prot,
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.config_intr = aqr_config_intr,
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.ack_interrupt = aqr_ack_interrupt,
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.read_status = aqr_read_status,
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+ .get_sset_count = aqr107_get_sset_count,
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+ .get_strings = aqr107_get_strings,
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+ .get_stats = aqr107_get_stats,
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},
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};
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