167 lines
5.2 KiB
Diff
167 lines
5.2 KiB
Diff
From e1a3ace7260fad338a76595b116a6bf5b5627aa2 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Thu, 7 Mar 2013 12:20:10 +0100
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Subject: [PATCH 1/7] MIPS: BCM63XX: remove duplicate spi register definitions
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BCM6338 and BCM6348, and BCM6358 and everything after that share the
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same register layout. To not have to redefine them for each new chip
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and keep the code size small, only use the definitions for the first
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chip with the certain layout.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/bcm63xx/dev-spi.c | 24 +++---------
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.../include/asm/mach-bcm63xx/bcm63xx_dev_spi.h | 10 +----
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 40 +-------------------
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3 files changed, 10 insertions(+), 64 deletions(-)
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--- a/arch/mips/bcm63xx/dev-spi.c
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+++ b/arch/mips/bcm63xx/dev-spi.c
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@@ -22,10 +22,6 @@
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/*
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* register offsets
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*/
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-static const unsigned long bcm6338_regs_spi[] = {
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- __GEN_SPI_REGS_TABLE(6338)
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-};
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-
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static const unsigned long bcm6348_regs_spi[] = {
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__GEN_SPI_REGS_TABLE(6348)
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};
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@@ -34,23 +30,15 @@ static const unsigned long bcm6358_regs_
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__GEN_SPI_REGS_TABLE(6358)
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};
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-static const unsigned long bcm6368_regs_spi[] = {
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- __GEN_SPI_REGS_TABLE(6368)
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-};
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-
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const unsigned long *bcm63xx_regs_spi;
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EXPORT_SYMBOL(bcm63xx_regs_spi);
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static __init void bcm63xx_spi_regs_init(void)
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{
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- if (BCMCPU_IS_6338())
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- bcm63xx_regs_spi = bcm6338_regs_spi;
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- if (BCMCPU_IS_6348())
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+ if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
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bcm63xx_regs_spi = bcm6348_regs_spi;
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- if (BCMCPU_IS_6358())
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+ if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
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bcm63xx_regs_spi = bcm6358_regs_spi;
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- if (BCMCPU_IS_6368())
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- bcm63xx_regs_spi = bcm6368_regs_spi;
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}
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#else
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static __init void bcm63xx_spi_regs_init(void) { }
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@@ -93,10 +81,10 @@ int __init bcm63xx_spi_register(void)
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spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
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if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
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- spi_resources[0].end += BCM_6338_RSET_SPI_SIZE - 1;
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- spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE;
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- spi_pdata.msg_type_shift = SPI_6338_MSG_TYPE_SHIFT;
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- spi_pdata.msg_ctl_width = SPI_6338_MSG_CTL_WIDTH;
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+ spi_resources[0].end += BCM_6348_RSET_SPI_SIZE - 1;
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+ spi_pdata.fifo_size = SPI_6348_MSG_DATA_SIZE;
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+ spi_pdata.msg_type_shift = SPI_6348_MSG_TYPE_SHIFT;
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+ spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;
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}
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if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
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@@ -71,18 +71,12 @@ static inline unsigned long bcm63xx_spir
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return bcm63xx_regs_spi[reg];
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#else
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-#ifdef CONFIG_BCM63XX_CPU_6338
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- __GEN_SPI_RSET(6338)
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-#endif
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-#ifdef CONFIG_BCM63XX_CPU_6348
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+#if defined(CONFIG_BCM63XX_CPU_6338) || defined(CONFIG_BCM63XX_CPU_6348)
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__GEN_SPI_RSET(6348)
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#endif
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-#ifdef CONFIG_BCM63XX_CPU_6358
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+#if defined(CONFIG_BCM63XX_CPU_6358) || defined(CONFIG_BCM63XX_CPU_6368)
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__GEN_SPI_RSET(6358)
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#endif
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-#ifdef CONFIG_BCM63XX_CPU_6368
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- __GEN_SPI_RSET(6368)
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-#endif
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#endif
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return 0;
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}
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1223,24 +1223,7 @@
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* _REG relative to RSET_SPI
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*************************************************************************/
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-/* BCM 6338 SPI core */
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-#define SPI_6338_CMD 0x00 /* 16-bits register */
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-#define SPI_6338_INT_STATUS 0x02
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-#define SPI_6338_INT_MASK_ST 0x03
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-#define SPI_6338_INT_MASK 0x04
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-#define SPI_6338_ST 0x05
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-#define SPI_6338_CLK_CFG 0x06
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-#define SPI_6338_FILL_BYTE 0x07
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-#define SPI_6338_MSG_TAIL 0x09
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-#define SPI_6338_RX_TAIL 0x0b
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-#define SPI_6338_MSG_CTL 0x40 /* 8-bits register */
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-#define SPI_6338_MSG_CTL_WIDTH 8
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-#define SPI_6338_MSG_DATA 0x41
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-#define SPI_6338_MSG_DATA_SIZE 0x3f
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-#define SPI_6338_RX_DATA 0x80
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-#define SPI_6338_RX_DATA_SIZE 0x3f
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-
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-/* BCM 6348 SPI core */
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+/* BCM 6338/6348 SPI core */
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#define SPI_6348_CMD 0x00 /* 16-bits register */
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#define SPI_6348_INT_STATUS 0x02
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#define SPI_6348_INT_MASK_ST 0x03
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@@ -1257,7 +1240,7 @@
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#define SPI_6348_RX_DATA 0x80
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#define SPI_6348_RX_DATA_SIZE 0x3f
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-/* BCM 6358 SPI core */
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+/* BCM 6358/6368 SPI core */
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#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
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#define SPI_6358_MSG_CTL_WIDTH 16
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#define SPI_6358_MSG_DATA 0x02
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@@ -1274,23 +1257,6 @@
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#define SPI_6358_MSG_TAIL 0x709
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#define SPI_6358_RX_TAIL 0x70B
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-/* BCM 6358 SPI core */
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-#define SPI_6368_MSG_CTL 0x00 /* 16-bits register */
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-#define SPI_6368_MSG_CTL_WIDTH 16
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-#define SPI_6368_MSG_DATA 0x02
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-#define SPI_6368_MSG_DATA_SIZE 0x21e
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-#define SPI_6368_RX_DATA 0x400
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-#define SPI_6368_RX_DATA_SIZE 0x220
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-#define SPI_6368_CMD 0x700 /* 16-bits register */
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-#define SPI_6368_INT_STATUS 0x702
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-#define SPI_6368_INT_MASK_ST 0x703
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-#define SPI_6368_INT_MASK 0x704
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-#define SPI_6368_ST 0x705
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-#define SPI_6368_CLK_CFG 0x706
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-#define SPI_6368_FILL_BYTE 0x707
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-#define SPI_6368_MSG_TAIL 0x709
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-#define SPI_6368_RX_TAIL 0x70B
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-
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/* Shared SPI definitions */
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/* Message configuration */
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@@ -1298,10 +1264,8 @@
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#define SPI_HD_W 0x01
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#define SPI_HD_R 0x02
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#define SPI_BYTE_CNT_SHIFT 0
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-#define SPI_6338_MSG_TYPE_SHIFT 6
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#define SPI_6348_MSG_TYPE_SHIFT 6
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#define SPI_6358_MSG_TYPE_SHIFT 14
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-#define SPI_6368_MSG_TYPE_SHIFT 14
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/* Command */
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#define SPI_CMD_NOOP 0x00
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