8ad0ba3a07
Move PCIe controller outside down to SoC level to avoid resource mapping problems. Also add more detailed error handling when mapping registers. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
50 lines
1.4 KiB
Diff
50 lines
1.4 KiB
Diff
--- a/drivers/ata/Kconfig
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+++ b/drivers/ata/Kconfig
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@@ -492,6 +492,13 @@ config SATA_VITESSE
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If unsure, say N.
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+config SATA_OXNAS
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+ tristate "PLXTECH NAS782X SATA support"
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+ help
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+ This option enables support for Nas782x Serial ATA controller.
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+
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+ If unsure, say N.
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+
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comment "PATA SFF controllers with BMDMA"
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config PATA_ALI
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--- a/drivers/ata/Makefile
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+++ b/drivers/ata/Makefile
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@@ -46,6 +46,7 @@ obj-$(CONFIG_SATA_SVW) += sata_svw.o
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obj-$(CONFIG_SATA_ULI) += sata_uli.o
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obj-$(CONFIG_SATA_VIA) += sata_via.o
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obj-$(CONFIG_SATA_VITESSE) += sata_vsc.o
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+obj-$(CONFIG_SATA_OXNAS) += sata_oxnas.o
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# SFF PATA w/ BMDMA
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obj-$(CONFIG_PATA_ALI) += pata_ali.o
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--- a/arch/arm/boot/dts/ox820.dtsi
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+++ b/arch/arm/boot/dts/ox820.dtsi
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@@ -398,5 +398,20 @@
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plxtech,pcie-outbound-offset = <0x174>;
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status = "disabled";
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};
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+
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+ sata: sata@45900000 {
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+ compatible = "plxtech,nas782x-sata";
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+ /* ports dmactl sgdma */
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+ reg = <0x45900000 0x20000>, <0x459A0000 0x40>, <0x459B0000 0x20>,
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+ /* core phy descriptors (optional) */
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+ <0x459E0000 0x2000>, <0x44900000 0x0C>, <0x50000000 0x1000>;
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+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&stdclk CLK_820_SATA>;
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+ resets = <&reset RESET_SATA>, <&reset RESET_SATA_LINK>, <&reset RESET_SATA_PHY>;
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+ reset-names = "sata", "link", "phy";
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+ nr-ports = <1>;
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+ status = "disabled";
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+ };
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+
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};
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};
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