40 lines
1.3 KiB
Diff
40 lines
1.3 KiB
Diff
--- a/drivers/net/wireless/ath/ath9k/hw.c
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+++ b/drivers/net/wireless/ath/ath9k/hw.c
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@@ -1280,7 +1280,8 @@ int ath9k_hw_reset(struct ath_hw *ah, st
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macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
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/* For chips on which RTC reset is done, save TSF before it gets cleared */
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- if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
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+ if (AR_SREV_9100(ah) ||
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+ (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
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tsf = ath9k_hw_gettsf64(ah);
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saveLedState = REG_READ(ah, AR_CFG_LED) &
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@@ -1312,7 +1313,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
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}
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/* Restore TSF */
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- if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
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+ if (tsf)
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ath9k_hw_settsf64(ah, tsf);
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if (AR_SREV_9280_10_OR_LATER(ah))
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@@ -1325,6 +1326,17 @@ int ath9k_hw_reset(struct ath_hw *ah, st
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if (r)
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return r;
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+ /*
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+ * Some AR91xx SoC devices frequently fail to accept TSF writes
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+ * right after the chip reset. When that happens, write a new
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+ * value after the initvals have been applied, with an offset
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+ * based on measured time differences
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+ */
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+ if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
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+ tsf += 1500;
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+ ath9k_hw_settsf64(ah, tsf);
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+ }
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+
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/* Setup MFP options for CCMP */
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if (AR_SREV_9280_20_OR_LATER(ah)) {
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/* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
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