Felix Fietkau 0b296d3808 ar71xx: use correct PLL configuration register bitmask for QCA956x SoC. ... Incorrect value causes clock inaccuracy as huge as 1/60. Signed-off-by: Dmitry Ivanov <dima@ubnt.com> Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 47363		2015-11-02 18:20:51 +00:00
..
base-files
files
generic
image	ar71xx: Add support for wdr7500v3	2015-11-02 10:17:15 +00:00
mikrotik
nand
patches-4.1	ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.	2015-11-02 18:20:51 +00:00
base-files.mk
config-4.1
Makefile
modules.mk