667f6c7f49
Manually rebased patches:
bcm27xx/patches-5.4/950-0135-spi-spi-bcm2835-Disable-forced-software-CS.patch
generic-backport/744-v5.5-net-sfp-soft-status-and-control-support.patch
layerscape/patches-5.4/819-uart-0005-tty-serial-fsl_lpuart-enable-dma-mode-for-imx8qxp.patch
mvebu/patches-5.4/521-arm64-dts-marvell-espressobin-Add-ethernet-switch-al.patch
Removed:
layerscape/patches-5.4/819-uart-0012-tty-serial-lpuart-add-LS1028A-support.patch
All modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711,
lantiq/Easybox 904 xDSL, x86_64
Run-tested: ipq806x/R7800, lantiq/Easybox 904 xDSL, x86_64
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
Co-developed-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
259 lines
4.4 KiB
Diff
259 lines
4.4 KiB
Diff
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
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@@ -53,6 +53,13 @@
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};
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};
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+ gsw: gsw@0 {
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+ compatible = "mediatek,mt753x";
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+ mediatek,ethsys = <ðsys>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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leds {
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compatible = "gpio-leds";
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@@ -146,6 +153,36 @@
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};
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};
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+&gsw {
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+ mediatek,mdio = <&mdio>;
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+ mediatek,portmap = "wllll";
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+ mediatek,mdio_master_pinmux = <0>;
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+ reset-gpios = <&pio 54 0>;
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+ interrupt-parent = <&pio>;
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+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "okay";
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+
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+ port5: port@5 {
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+ compatible = "mediatek,mt753x-port";
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+ reg = <5>;
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+ phy-mode = "rgmii";
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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+
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+ port6: port@6 {
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+ compatible = "mediatek,mt753x-port";
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+ reg = <6>;
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+ phy-mode = "sgmii";
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+ fixed-link {
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+ speed = <2500>;
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+ full-duplex;
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+ };
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+ };
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+};
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+
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -1,7 +1,6 @@
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/*
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- * Copyright (c) 2017 MediaTek Inc.
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- * Author: Ming Huang <ming.huang@mediatek.com>
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- * Sean Wang <sean.wang@mediatek.com>
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+ * Copyright (c) 2018 MediaTek Inc.
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+ * Author: Ryder Lee <ryder.lee@mediatek.com>
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*
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* SPDX-License-Identifier: (GPL-2.0 OR MIT)
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*/
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@@ -14,7 +13,7 @@
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#include "mt6380.dtsi"
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/ {
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- model = "MediaTek MT7622 RFB1 board";
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+ model = "MT7622_MT7531 RFB";
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compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
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aliases {
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@@ -23,7 +22,7 @@
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chosen {
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stdout-path = "serial0:115200n8";
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- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
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+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
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};
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cpus {
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@@ -40,23 +39,36 @@
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gpio-keys {
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compatible = "gpio-keys";
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- poll-interval = <100>;
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factory {
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label = "factory";
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linux,code = <BTN_0>;
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- gpios = <&pio 0 0>;
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+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
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};
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wps {
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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- gpios = <&pio 102 0>;
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+ gpios = <&pio 102 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+
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+ green {
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+ label = "bpi-r64:pio:green";
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+ gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ red {
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+ label = "bpi-r64:pio:red";
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+ gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
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};
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};
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memory {
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- reg = <0 0x40000000 0 0x20000000>;
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+ reg = <0 0x40000000 0 0x40000000>;
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};
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reg_1p8v: regulator-1p8v {
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@@ -101,23 +113,82 @@
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};
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ð {
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- pinctrl-names = "default";
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- pinctrl-0 = <ð_pins>;
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status = "okay";
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+ gmac0: mac@0 {
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+ compatible = "mediatek,eth-mac";
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+ reg = <0>;
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+ phy-mode = "2500base-x";
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+
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+ fixed-link {
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+ speed = <2500>;
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+ full-duplex;
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+ pause;
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+ };
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+ };
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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- phy-handle = <&phy5>;
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+ phy-mode = "rgmii";
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ pause;
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+ };
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};
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- mdio-bus {
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+ mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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- phy5: ethernet-phy@5 {
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- reg = <5>;
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- phy-mode = "sgmii";
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+ switch@0 {
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+ compatible = "mediatek,mt7531";
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+ reg = <0>;
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+ reset-gpios = <&pio 54 0>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ label = "lan1";
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ label = "lan2";
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ label = "lan3";
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ label = "lan4";
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+ };
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+
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+ port@4 {
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+ reg = <4>;
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+ label = "wan";
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+ };
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+
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+ port@6 {
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+ reg = <6>;
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+ label = "cpu";
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+ ethernet = <&gmac0>;
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+ phy-mode = "2500base-x";
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+
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+ fixed-link {
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+ speed = <2500>;
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+ full-duplex;
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+ pause;
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+ };
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+ };
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+ };
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};
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};
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};
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@@ -185,15 +256,28 @@
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&pcie {
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pinctrl-names = "default";
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- pinctrl-0 = <&pcie0_pins>;
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+ pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
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status = "okay";
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pcie@0,0 {
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status = "okay";
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};
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+
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+ pcie@1,0 {
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+ status = "okay";
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+ };
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};
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&pio {
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+ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
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+ * SATA functions. i.e. output-high: PCIe, output-low: SATA
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+ */
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+ asm_sel {
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+ gpio-hog;
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+ gpios = <90 GPIO_ACTIVE_HIGH>;
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+ output-high;
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+ };
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+
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/* eMMC is shared pin with parallel NAND */
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emmc_pins_default: emmc-pins-default {
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mux {
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@@ -460,11 +544,11 @@
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};
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&sata {
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- status = "okay";
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+ status = "disable";
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};
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&sata_phy {
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- status = "okay";
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+ status = "disable";
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};
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&spi0 {
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