029093a302
This target has full device tree support, thus reducing the number of patches needed for bcm63xx, in which there's a patch for every board. The intention is to start with a minimal amount of downstream patches and start upstreaming all of them. Current status: - Enabling EHCI/OHCI on BCM6358 causes a kernel panic. - BCM63268 lacks Timer Clocks/Reset support. - No PCI/PCIe drivers. - No ethernet drivers. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
35 lines
1.2 KiB
Diff
35 lines
1.2 KiB
Diff
From cf0d2fbaae9e962d91a321de75e0d4f9f9ccbdfe Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
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Date: Thu, 21 Jan 2021 18:17:37 +0100
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Subject: [PATCH] nand: brcmnand: fix OOB R/W with Hamming ECC
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Hamming ECC doesn't cover the OOB data, so reading or writing OOB shall
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always be done without ECC enabled.
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This is a problem when adding JFFS2 cleanmarkers to erased blocks. When JFFS2
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clenmarkers are added to the OOB with ECC enabled, OOB bytes will be changed
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from ff ff ff to 00 00 00, reporting incorrect ECC errors.
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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---
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drivers/mtd/nand/raw/brcmnand/brcmnand.c | 6 ++++++
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1 file changed, 6 insertions(+)
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--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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@@ -2688,6 +2688,12 @@ static int brcmnand_attach_chip(struct n
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ret = brcmstb_choose_ecc_layout(host);
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+ /* If OOB is written with ECC enabled it will cause ECC errors */
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+ if (is_hamming_ecc(host->ctrl, &host->hwcfg)) {
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+ chip->ecc.write_oob = brcmnand_write_oob_raw;
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+ chip->ecc.read_oob = brcmnand_read_oob_raw;
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+ }
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+
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return ret;
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}
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