6bf179b270
Switch to the mainline Lantiq PCIe PHY driver and update the vr9.dtsi
accordingly.
The Lantiq IRQ SMP support added upstream required changes to the SoC
dtsi as well.
Following changes are made to the Lantiq kernel patches:
0005-lantiq_etop-pass-struct-device-to-DMA-API-functions.patch
0006-MIPS-lantiq-pass-struct-device-to-DMA-API-functions.patch
applied upstream
0008-MIPS-lantiq-backport-old-timer-code.patch
access_ok API update because it lost it's type (which was the first)
parameter in upstream commit 96d4f267e40f95 ("Remove 'type' argument
from access_ok() function")
0024-MIPS-lantiq-autoselect-soc-rev-matching-fw.patch
merged into 0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch
0024-MIPS-lantiq-revert-DSA-switch-driver-PMU-clock-chang.patch
revert upstream changes required for upstream xrx200 ethernet and
xrx200 (DSA) switch driver but breaking our driver
0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch
required for our driver but dropped upstream, add former upstream
version
0028-NET-lantiq-various-etop-fixes.patch
now has to use the phy_set_max_speed API instead of modifying
phydev->supported. Also call ltq_dma_enable_irq() in
ltq_etop_open() based on upstream commit cc973aecf0b054 ("MIPS:
lantiq: Do not enable IRQs in dma open")
Signed-off-by: Mathias Kresin <dev@kresin.me>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
31 lines
720 B
Diff
31 lines
720 B
Diff
--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -422,6 +422,20 @@ static void clkdev_add_clkout(void)
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}
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}
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+static void set_phy_clock_source(struct device_node *np_cgu)
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+{
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+ u32 phy_clk_src, ifcc;
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+
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+ if (!np_cgu)
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+ return;
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+
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+ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src))
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+ return;
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+
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+ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c);
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+ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr);
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+}
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+
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/* bring up all register ranges that we need for basic system control */
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void __init ltq_soc_init(void)
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{
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@@ -585,4 +599,6 @@ void __init ltq_soc_init(void)
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clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
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}
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usb_set_clock();
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+
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+ set_phy_clock_source(np_cgu);
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}
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