c9ae111a20
This is a backport of the patches accepted to the Linux mainline related to mvebu SoC (Armada XP and Armada 370) between Linux v3.12, and Linux v3.13. This work mainly covers: * Finishes work for sharing the pxa nand driver(drivers/mtd/nand/pxa3xx_nand.c) between the PXA family, and the Armada family. * timer initialization update, and access function for the Armada family. * Generic IRQ handling backporting. * Some bug fixes. Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com> CC: Luka Perkov <luka@openwrt.org> SVN-Revision: 39566
75 lines
2.5 KiB
Diff
75 lines
2.5 KiB
Diff
From 496f307424d3958ef43ad06ae6a0be98ede2a92c Mon Sep 17 00:00:00 2001
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From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Date: Thu, 7 Nov 2013 12:17:16 -0300
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Subject: [PATCH 137/203] mtd: nand: pxa3xx: Split FIFO size from to-be-read
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FIFO count
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Introduce a fifo_size field to represent the size of the controller's
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FIFO buffer, and use it to distinguish that size from the amount
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of data bytes to be read from the FIFO.
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This is important to support devices with pages larger than the
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controller's internal FIFO, that need to read the pages in FIFO-sized
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chunks.
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In particular, the current code is at least confusing, for it mixes
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all the different sizes involved: FIFO size, page size and data size.
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This commit starts the cleaning by removing the info->page_size field
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that is not currently used. The host->page_size field should also
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be removed and use always mtd->writesize instead. Follow up commits
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will clean this up.
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Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Tested-by: Daniel Mack <zonque@gmail.com>
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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---
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drivers/mtd/nand/pxa3xx_nand.c | 12 +++++++-----
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1 file changed, 7 insertions(+), 5 deletions(-)
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--- a/drivers/mtd/nand/pxa3xx_nand.c
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+++ b/drivers/mtd/nand/pxa3xx_nand.c
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@@ -201,8 +201,8 @@ struct pxa3xx_nand_info {
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int use_spare; /* use spare ? */
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int is_ready;
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- unsigned int page_size; /* page size of attached chip */
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- unsigned int data_size; /* data size in FIFO */
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+ unsigned int fifo_size; /* max. data size in the FIFO */
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+ unsigned int data_size; /* data to be read from FIFO */
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unsigned int oob_size;
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int retcode;
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@@ -307,16 +307,15 @@ static void pxa3xx_nand_set_timing(struc
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static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
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{
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- struct pxa3xx_nand_host *host = info->host[info->cs];
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int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
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- info->data_size = host->page_size;
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+ info->data_size = info->fifo_size;
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if (!oob_enable) {
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info->oob_size = 0;
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return;
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}
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- switch (host->page_size) {
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+ switch (info->fifo_size) {
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case 2048:
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info->oob_size = (info->use_ecc) ? 40 : 64;
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break;
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@@ -933,9 +932,12 @@ static int pxa3xx_nand_detect_config(str
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uint32_t ndcr = nand_readl(info, NDCR);
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if (ndcr & NDCR_PAGE_SZ) {
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+ /* Controller's FIFO size */
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+ info->fifo_size = 2048;
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host->page_size = 2048;
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host->read_id_bytes = 4;
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} else {
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+ info->fifo_size = 512;
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host->page_size = 512;
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host->read_id_bytes = 2;
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}
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