64b53247c4
Refresh patches. Remove upstreamed patch: generic/pending/181-net-usb-add-lte-modem-wistron-neweb-d18q1.patch Update patches that no longer applies: generic/hack/901-debloat_sock_diag.patch Compile-tested on: x86/64. Runtime-tested on: x86/64. Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
201 lines
4.7 KiB
Diff
201 lines
4.7 KiB
Diff
From d41d41bfcbd8ad4bcbb1b433f7d5c3b613c58419 Mon Sep 17 00:00:00 2001
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From: Sean Wang <sean.wang@mediatek.com>
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Date: Mon, 22 Jan 2018 16:58:36 +0800
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Subject: [PATCH 223/224] arm64: dts: mt7622: add mmc related device nodes
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add mmc device nodes and proper setup for used pins
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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Signed-off-by: Jimin Wang <jimin.wang@mediatek.com>
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---
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arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 106 +++++++++++++++++++++++++++
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arch/arm64/boot/dts/mediatek/mt7622.dtsi | 20 +++++
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2 files changed, 126 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -8,6 +8,7 @@
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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+#include <dt-bindings/gpio/gpio.h>
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#include "mt7622.dtsi"
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#include "mt6380.dtsi"
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@@ -53,6 +54,14 @@
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reg = <0 0x40000000 0 0x3F000000>;
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};
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+ reg_1p8v: regulator-1p8v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-1.8V";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-always-on;
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+ };
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+
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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@@ -89,6 +98,23 @@
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function = "emmc", "emmc_rst";
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groups = "emmc";
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};
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+
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+ /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
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+ * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
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+ * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
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+ */
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+ conf-cmd-dat {
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+ pins = "NDL0", "NDL1", "NDL2",
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+ "NDL3", "NDL4", "NDL5",
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+ "NDL6", "NDL7", "NRB";
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+ input-enable;
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+ bias-pull-up;
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+ };
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+
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+ conf-clk {
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+ pins = "NCLE";
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+ bias-pull-down;
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+ };
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};
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emmc_pins_uhs: emmc-pins-uhs {
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@@ -96,6 +122,21 @@
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function = "emmc";
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groups = "emmc";
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};
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+
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+ conf-cmd-dat {
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+ pins = "NDL0", "NDL1", "NDL2",
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+ "NDL3", "NDL4", "NDL5",
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+ "NDL6", "NDL7", "NRB";
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+ input-enable;
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+ drive-strength = <4>;
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+ bias-pull-up;
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+ };
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+
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+ conf-clk {
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+ pins = "NCLE";
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+ drive-strength = <4>;
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+ bias-pull-down;
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+ };
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};
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eth_pins: eth-pins {
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@@ -194,6 +235,27 @@
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function = "sd";
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groups = "sd_0";
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};
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+
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+ /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
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+ * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
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+ * DAT2, DAT3, CMD, CLK for SD respectively.
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+ */
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+ conf-cmd-data {
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+ pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
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+ "I2S2_IN","I2S4_OUT";
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+ input-enable;
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+ drive-strength = <8>;
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+ bias-pull-up;
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+ };
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+ conf-clk {
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+ pins = "I2S3_OUT";
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+ drive-strength = <12>;
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+ bias-pull-down;
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+ };
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+ conf-cd {
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+ pins = "TXD3";
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+ bias-pull-up;
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+ };
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};
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sd0_pins_uhs: sd0-pins-uhs {
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@@ -201,6 +263,18 @@
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function = "sd";
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groups = "sd_0";
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};
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+
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+ conf-cmd-data {
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+ pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
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+ "I2S2_IN","I2S4_OUT";
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+ input-enable;
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+ bias-pull-up;
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+ };
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+
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+ conf-clk {
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+ pins = "I2S3_OUT";
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+ bias-pull-down;
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+ };
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};
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/* Serial NAND is shared pin with SPI-NOR */
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@@ -311,6 +385,38 @@
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status = "okay";
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};
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+&mmc0 {
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+ pinctrl-names = "default", "state_uhs";
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+ pinctrl-0 = <&emmc_pins_default>;
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+ pinctrl-1 = <&emmc_pins_uhs>;
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+ status = "okay";
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+ bus-width = <8>;
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+ max-frequency = <50000000>;
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+ cap-mmc-highspeed;
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+ mmc-hs200-1_8v;
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+ vmmc-supply = <®_3p3v>;
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+ vqmmc-supply = <®_1p8v>;
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+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
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+ assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
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+ non-removable;
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+};
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+
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+&mmc1 {
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+ pinctrl-names = "default", "state_uhs";
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+ pinctrl-0 = <&sd0_pins_default>;
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+ pinctrl-1 = <&sd0_pins_uhs>;
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+ status = "okay";
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+ bus-width = <4>;
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+ max-frequency = <50000000>;
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+ cap-sd-highspeed;
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+ r_smpl = <1>;
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+ cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
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+ vmmc-supply = <®_3p3v>;
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+ vqmmc-supply = <®_3p3v>;
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+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
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+ assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
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+};
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+
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&nandc {
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pinctrl-names = "default";
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pinctrl-0 = <¶llel_nand_pins>;
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -527,6 +527,26 @@
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status = "disabled";
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};
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+ mmc0: mmc@11230000 {
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+ compatible = "mediatek,mt7622-mmc";
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+ reg = <0 0x11230000 0 0x1000>;
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+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
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+ <&topckgen CLK_TOP_MSDC50_0_SEL>;
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+ clock-names = "source", "hclk";
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+ status = "disabled";
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+ };
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+
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+ mmc1: mmc@11240000 {
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+ compatible = "mediatek,mt7622-mmc";
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+ reg = <0 0x11240000 0 0x1000>;
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+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
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+ <&topckgen CLK_TOP_AXI_SEL>;
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+ clock-names = "source", "hclk";
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+ status = "disabled";
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+ };
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+
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ssusbsys: ssusbsys@1a000000 {
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compatible = "mediatek,mt7622-ssusbsys",
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"syscon";
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