531 lines
11 KiB
C
531 lines
11 KiB
C
/*
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* Broadcom SiliconBackplane chipcommon serial flash interface
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*
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* Copyright 2007, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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*/
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#include <typedefs.h>
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#include <osl.h>
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#include <sbutils.h>
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#include <sbconfig.h>
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#include <sbchipc.h>
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#include <bcmdevs.h>
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#include <sflash.h>
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/* Private global state */
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static struct sflash sflash;
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/* Issue a serial flash command */
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static INLINE void
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sflash_cmd (osl_t * osh, chipcregs_t * cc, uint opcode)
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{
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W_REG (osh, &cc->flashcontrol, SFLASH_START | opcode);
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while (R_REG (osh, &cc->flashcontrol) & SFLASH_BUSY);
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}
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/* Initialize serial flash access */
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struct sflash *
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sflash_init (sb_t * sbh, chipcregs_t * cc)
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{
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uint32 id, id2;
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osl_t *osh;
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ASSERT (sbh);
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osh = sb_osh (sbh);
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bzero (&sflash, sizeof (sflash));
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sflash.type = sbh->cccaps & CC_CAP_FLASH_MASK;
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switch (sflash.type)
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{
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case SFLASH_ST:
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/* Probe for ST chips */
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sflash_cmd (osh, cc, SFLASH_ST_DP);
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sflash_cmd (osh, cc, SFLASH_ST_RES);
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id = R_REG (osh, &cc->flashdata);
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switch (id)
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{
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case 0x11:
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/* ST M25P20 2 Mbit Serial Flash */
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sflash.blocksize = 64 * 1024;
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sflash.numblocks = 4;
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break;
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case 0x12:
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/* ST M25P40 4 Mbit Serial Flash */
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sflash.blocksize = 64 * 1024;
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sflash.numblocks = 8;
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break;
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case 0x13:
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/* ST M25P80 8 Mbit Serial Flash */
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sflash.blocksize = 64 * 1024;
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sflash.numblocks = 16;
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break;
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case 0x14:
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/* ST M25P16 16 Mbit Serial Flash */
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sflash.blocksize = 64 * 1024;
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sflash.numblocks = 32;
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break;
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case 0x15:
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/* ST M25P32 32 Mbit Serial Flash */
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sflash.blocksize = 64 * 1024;
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sflash.numblocks = 64;
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break;
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case 0x16:
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/* ST M25P64 64 Mbit Serial Flash */
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sflash.blocksize = 64 * 1024;
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sflash.numblocks = 128;
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break;
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case 0xbf:
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W_REG (osh, &cc->flashaddress, 1);
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sflash_cmd (osh, cc, SFLASH_ST_RES);
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id2 = R_REG (osh, &cc->flashdata);
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if (id2 == 0x44)
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{
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/* SST M25VF80 4 Mbit Serial Flash */
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sflash.blocksize = 64 * 1024;
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sflash.numblocks = 8;
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}
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break;
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}
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break;
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case SFLASH_AT:
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/* Probe for Atmel chips */
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sflash_cmd (osh, cc, SFLASH_AT_STATUS);
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id = R_REG (osh, &cc->flashdata) & 0x3c;
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switch (id)
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{
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case 0xc:
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/* Atmel AT45DB011 1Mbit Serial Flash */
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sflash.blocksize = 256;
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sflash.numblocks = 512;
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break;
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case 0x14:
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/* Atmel AT45DB021 2Mbit Serial Flash */
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sflash.blocksize = 256;
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sflash.numblocks = 1024;
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break;
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case 0x1c:
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/* Atmel AT45DB041 4Mbit Serial Flash */
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sflash.blocksize = 256;
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sflash.numblocks = 2048;
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break;
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case 0x24:
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/* Atmel AT45DB081 8Mbit Serial Flash */
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sflash.blocksize = 256;
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sflash.numblocks = 4096;
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break;
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case 0x2c:
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/* Atmel AT45DB161 16Mbit Serial Flash */
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sflash.blocksize = 512;
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sflash.numblocks = 4096;
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break;
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case 0x34:
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/* Atmel AT45DB321 32Mbit Serial Flash */
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sflash.blocksize = 512;
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sflash.numblocks = 8192;
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break;
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case 0x3c:
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/* Atmel AT45DB642 64Mbit Serial Flash */
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sflash.blocksize = 1024;
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sflash.numblocks = 8192;
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break;
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}
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break;
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}
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sflash.size = sflash.blocksize * sflash.numblocks;
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return sflash.size ? &sflash : NULL;
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}
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/* Read len bytes starting at offset into buf. Returns number of bytes read. */
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int
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sflash_read (sb_t * sbh, chipcregs_t * cc, uint offset, uint len, uchar * buf)
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{
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uint8 *from, *to;
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int cnt, i;
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osl_t *osh;
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ASSERT (sbh);
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if (!len)
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return 0;
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if ((offset + len) > sflash.size)
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return -22;
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if ((len >= 4) && (offset & 3))
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cnt = 4 - (offset & 3);
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else if ((len >= 4) && ((uintptr) buf & 3))
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cnt = 4 - ((uintptr) buf & 3);
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else
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cnt = len;
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osh = sb_osh (sbh);
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from = (uint8 *) (uintptr) OSL_UNCACHED (SB_FLASH2 + offset);
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to = (uint8 *) buf;
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if (cnt < 4)
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{
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for (i = 0; i < cnt; i++)
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{
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*to = R_REG (osh, from);
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from++;
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to++;
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}
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return cnt;
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}
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while (cnt >= 4)
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{
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*(uint32 *) to = R_REG (osh, (uint32 *) from);
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from += 4;
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to += 4;
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cnt -= 4;
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}
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return (len - cnt);
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}
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/* Poll for command completion. Returns zero when complete. */
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int
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sflash_poll (sb_t * sbh, chipcregs_t * cc, uint offset)
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{
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osl_t *osh;
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ASSERT (sbh);
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osh = sb_osh (sbh);
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if (offset >= sflash.size)
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return -22;
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switch (sflash.type)
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{
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case SFLASH_ST:
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/* Check for ST Write In Progress bit */
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sflash_cmd (osh, cc, SFLASH_ST_RDSR);
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return R_REG (osh, &cc->flashdata) & SFLASH_ST_WIP;
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case SFLASH_AT:
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/* Check for Atmel Ready bit */
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sflash_cmd (osh, cc, SFLASH_AT_STATUS);
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return !(R_REG (osh, &cc->flashdata) & SFLASH_AT_READY);
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}
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return 0;
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}
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/* Write len bytes starting at offset into buf. Returns number of bytes
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* written. Caller should poll for completion.
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*/
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int
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sflash_write (sb_t * sbh, chipcregs_t * cc, uint offset, uint len,
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const uchar * buf)
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{
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struct sflash *sfl;
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int ret = 0;
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bool is4712b0;
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uint32 page, byte, mask;
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osl_t *osh;
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ASSERT (sbh);
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osh = sb_osh (sbh);
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if (!len)
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return 0;
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if ((offset + len) > sflash.size)
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return -22;
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sfl = &sflash;
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switch (sfl->type)
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{
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case SFLASH_ST:
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is4712b0 = (sbh->chip == BCM4712_CHIP_ID) && (sbh->chiprev == 3);
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/* Enable writes */
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sflash_cmd (osh, cc, SFLASH_ST_WREN);
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if (is4712b0)
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{
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mask = 1 << 14;
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W_REG (osh, &cc->flashaddress, offset);
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W_REG (osh, &cc->flashdata, *buf++);
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/* Set chip select */
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OR_REG (osh, &cc->gpioout, mask);
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/* Issue a page program with the first byte */
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sflash_cmd (osh, cc, SFLASH_ST_PP);
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ret = 1;
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offset++;
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len--;
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while (len > 0)
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{
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if ((offset & 255) == 0)
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{
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/* Page boundary, drop cs and return */
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AND_REG (osh, &cc->gpioout, ~mask);
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if (!sflash_poll (sbh, cc, offset))
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{
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/* Flash rejected command */
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return -11;
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}
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return ret;
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}
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else
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{
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/* Write single byte */
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sflash_cmd (osh, cc, *buf++);
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}
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ret++;
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offset++;
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len--;
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}
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/* All done, drop cs if needed */
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if ((offset & 255) != 1)
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{
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/* Drop cs */
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AND_REG (osh, &cc->gpioout, ~mask);
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if (!sflash_poll (sbh, cc, offset))
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{
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/* Flash rejected command */
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return -12;
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}
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}
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}
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else if (sbh->ccrev >= 20)
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{
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W_REG (NULL, &cc->flashaddress, offset);
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W_REG (NULL, &cc->flashdata, *buf++);
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/* Issue a page program with CSA bit set */
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sflash_cmd (osh, cc, SFLASH_ST_CSA | SFLASH_ST_PP);
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ret = 1;
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offset++;
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len--;
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while (len > 0)
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{
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if ((offset & 255) == 0)
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{
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/* Page boundary, poll droping cs and return */
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W_REG (NULL, &cc->flashcontrol, 0);
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if (!sflash_poll (sbh, cc, offset))
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{
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/* Flash rejected command */
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return -11;
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}
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return ret;
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}
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else
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{
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/* Write single byte */
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sflash_cmd (osh, cc, SFLASH_ST_CSA | *buf++);
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}
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ret++;
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offset++;
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len--;
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}
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/* All done, drop cs if needed */
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if ((offset & 255) != 1)
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{
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/* Drop cs, poll */
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W_REG (NULL, &cc->flashcontrol, 0);
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if (!sflash_poll (sbh, cc, offset))
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{
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/* Flash rejected command */
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return -12;
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}
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}
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}
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else
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{
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ret = 1;
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W_REG (osh, &cc->flashaddress, offset);
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W_REG (osh, &cc->flashdata, *buf);
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/* Page program */
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sflash_cmd (osh, cc, SFLASH_ST_PP);
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}
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break;
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case SFLASH_AT:
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mask = sfl->blocksize - 1;
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page = (offset & ~mask) << 1;
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byte = offset & mask;
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/* Read main memory page into buffer 1 */
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if (byte || (len < sfl->blocksize))
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{
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W_REG (osh, &cc->flashaddress, page);
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sflash_cmd (osh, cc, SFLASH_AT_BUF1_LOAD);
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/* 250 us for AT45DB321B */
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SPINWAIT (sflash_poll (sbh, cc, offset), 1000);
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ASSERT (!sflash_poll (sbh, cc, offset));
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}
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/* Write into buffer 1 */
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for (ret = 0; (ret < (int) len) && (byte < sfl->blocksize); ret++)
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{
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W_REG (osh, &cc->flashaddress, byte++);
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W_REG (osh, &cc->flashdata, *buf++);
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sflash_cmd (osh, cc, SFLASH_AT_BUF1_WRITE);
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}
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/* Write buffer 1 into main memory page */
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W_REG (osh, &cc->flashaddress, page);
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sflash_cmd (osh, cc, SFLASH_AT_BUF1_PROGRAM);
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break;
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}
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return ret;
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}
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/* Erase a region. Returns number of bytes scheduled for erasure.
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* Caller should poll for completion.
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*/
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int
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sflash_erase (sb_t * sbh, chipcregs_t * cc, uint offset)
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{
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struct sflash *sfl;
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osl_t *osh;
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ASSERT (sbh);
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osh = sb_osh (sbh);
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if (offset >= sflash.size)
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return -22;
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sfl = &sflash;
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switch (sfl->type)
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{
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case SFLASH_ST:
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sflash_cmd (osh, cc, SFLASH_ST_WREN);
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W_REG (osh, &cc->flashaddress, offset);
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sflash_cmd (osh, cc, SFLASH_ST_SE);
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return sfl->blocksize;
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case SFLASH_AT:
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W_REG (osh, &cc->flashaddress, offset << 1);
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sflash_cmd (osh, cc, SFLASH_AT_PAGE_ERASE);
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return sfl->blocksize;
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}
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return 0;
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}
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/*
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* writes the appropriate range of flash, a NULL buf simply erases
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* the region of flash
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*/
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int
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sflash_commit (sb_t * sbh, chipcregs_t * cc, uint offset, uint len,
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const uchar * buf)
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{
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struct sflash *sfl;
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uchar *block = NULL, *cur_ptr, *blk_ptr;
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uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
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uint blk_offset, blk_len, copied;
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int bytes, ret = 0;
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osl_t *osh;
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ASSERT (sbh);
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osh = sb_osh (sbh);
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/* Check address range */
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if (len <= 0)
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return 0;
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sfl = &sflash;
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if ((offset + len) > sfl->size)
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return -1;
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blocksize = sfl->blocksize;
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mask = blocksize - 1;
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/* Allocate a block of mem */
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if (!(block = MALLOC (osh, blocksize)))
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return -1;
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while (len)
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{
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/* Align offset */
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cur_offset = offset & ~mask;
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cur_length = blocksize;
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cur_ptr = block;
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remainder = blocksize - (offset & mask);
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if (len < remainder)
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cur_retlen = len;
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else
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cur_retlen = remainder;
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/* buf == NULL means erase only */
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if (buf)
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{
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/* Copy existing data into holding block if necessary */
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if ((offset & mask) || (len < blocksize))
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{
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blk_offset = cur_offset;
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blk_len = cur_length;
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blk_ptr = cur_ptr;
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/* Copy entire block */
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while (blk_len)
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{
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copied =
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sflash_read (sbh, cc, blk_offset, blk_len, blk_ptr);
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blk_offset += copied;
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blk_len -= copied;
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blk_ptr += copied;
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}
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}
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|
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/* Copy input data into holding block */
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memcpy (cur_ptr + (offset & mask), buf, cur_retlen);
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}
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|
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/* Erase block */
|
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if ((ret = sflash_erase (sbh, cc, (uint) cur_offset)) < 0)
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goto done;
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while (sflash_poll (sbh, cc, (uint) cur_offset));
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|
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/* buf == NULL means erase only */
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if (!buf)
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{
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offset += cur_retlen;
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len -= cur_retlen;
|
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continue;
|
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}
|
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|
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/* Write holding block */
|
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while (cur_length > 0)
|
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{
|
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if ((bytes = sflash_write (sbh, cc,
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(uint) cur_offset,
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(uint) cur_length,
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(uchar *) cur_ptr)) < 0)
|
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{
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ret = bytes;
|
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goto done;
|
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}
|
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while (sflash_poll (sbh, cc, (uint) cur_offset));
|
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cur_offset += bytes;
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cur_length -= bytes;
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cur_ptr += bytes;
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}
|
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|
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offset += cur_retlen;
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len -= cur_retlen;
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buf += cur_retlen;
|
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}
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|
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ret = len;
|
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done:
|
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if (block)
|
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MFREE (osh, block, blocksize);
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return ret;
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}
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