0e73da37d5
Broadcom submitted new SMP patches for this SoC to upstream Linux, add them to OpenWrt. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 47687
70 lines
2.3 KiB
Diff
70 lines
2.3 KiB
Diff
From 204b9dbd7c4bd5a223fd104b9cba56c12fe04add Mon Sep 17 00:00:00 2001
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From: Kapil Hali <kapilh@broadcom.com>
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Date: Wed, 19 Aug 2015 13:42:23 -0400
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Subject: [PATCH 130/134] dt-bindings: add SMP enable-method for Broadcom NSP
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Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
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Northstar Plus CPU to the 32-bit ARM CPU device tree binding
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documentation file and create a new binding documentation for
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Northstar Plus CPU.
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Signed-off-by: Kapil Hali <kapilh@broadcom.com>
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---
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.../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++++++++++++++++++++++
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Documentation/devicetree/bindings/arm/cpus.txt | 1 +
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2 files changed, 40 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
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@@ -0,0 +1,39 @@
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+Broadcom Northstar Plus SoC CPU Enable Method
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+---------------------------------------------
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+This binding defines the enable method used for starting secondary
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+CPUs in the following Broadcom SoCs:
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+ BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
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+
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+The enable method is specified by defining the following required
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+properties in the "cpus" device tree node:
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+ - enable-method = "brcm,bcm-nsp-smp";
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+ - secondary-boot-reg = <...>;
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+
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+The secondary-boot-reg property is a u32 value that specifies the
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+physical address of the register which should hold the common
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+entry point for a secondary CPU. This entry is cpu node specific
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+and should be added per cpu. E.g., in case of NSP (BCM58625) which
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+is a dual core CPU SoC, this entry should be added to cpu1 node.
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+
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+
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+Example:
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ enable-method = "brcm,bcm-nsp-smp";
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+
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+ cpu0: cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a9";
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+ next-level-cache = <&L2>;
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+ reg = <0>;
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+ };
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+
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+ cpu1: cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a9";
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+ next-level-cache = <&L2>;
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+ reg = <1>;
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+ secondary-boot-reg = <0xffff042c>;
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+ };
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+ };
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--- a/Documentation/devicetree/bindings/arm/cpus.txt
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+++ b/Documentation/devicetree/bindings/arm/cpus.txt
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@@ -189,6 +189,7 @@ nodes to be present and contain the prop
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can be one of:
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"allwinner,sun6i-a31"
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"arm,psci"
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+ "brcm,bcm-nsp-smp"
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"brcm,brahma-b15"
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"marvell,armada-375-smp"
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"marvell,armada-380-smp"
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